CN101021739A - Reset system and reset method - Google Patents

Abstract

The invention provides a reset system and a reset method, in particular to a reset system for completing the reset operation of an integrated circuit chip, which comprises the following steps: a delay module for receiving a reset source signal and a reference clock signal to generate a system reset signal and a synchronization signal; the clock control signal generation module receives the system reset signal, the synchronous signal and the reference clock signal to generate a clock control signal, and the clock control signal generation module enables the clock control signal to be effective after the received synchronous signal is changed from an effective state to a failure state; and a latch unit for determining whether to output the system clock signal according to the received reference clock signal and the clock control signal. The invention realizes the synchronous operation of asynchronous reset by controlling the output of the system clock signal sent to the integrated circuit chip, thereby not needing to add a delay buffer in a circuit connection path, further reducing the complexity of circuit design and simultaneously reducing the area of the chip.

Description

Reset system and reset method

technical field

The invention relates to an integrated circuit design method, in particular to a reset system and reset method applied in integrated circuit design.

Background technique

With the development of integrated circuit design technology, the design scale of single-chip circuits has become larger, and the design complexity has also increased. At present, in the design of integrated circuits, especially in the design of large-scale integrated circuits represented by SOC chips (system on chip, system on chip), synchronous timing design methods are usually used to control the logic output of each module of the chip. The synchronous timing design means that inside the chip of the integrated circuit, all flip-flops work on the same clock signal, and the inversion of states of all flip-flops also occurs at the same moment.

However, in the actual process, due to the different paths that the clock signal takes to reach each flip-flop, the delay of the clock signal on each flip-flop is different, resulting in the time when the clock signal arrives at each flip-flop is not the same, and thus cannot guarantee All flip-flop states are flipped at the same instant. Therefore, the logical state of the system is likely to be confused, and thus the integrated circuit design cannot meet the expected requirements. As shown in Figure 1, in order to ensure that the clock signal reaches each flip-flop at the same time, the prior art usually compensates the transmission path from the clock signal clock_in to each flip-flop FF1-FFn by inserting a clock tree, so that the clock signal clock_in can reach all flip-flops at the same time.

Similarly, as shown in FIG. 1 , in the prior art, a method similar to inserting a clock tree is usually used to ensure that the reset source signal rst_in arrives synchronously at each flip-flop in the design chip 1 , that is, flip-flops FF1˜FFn. Each flip-flop is provided with a reset terminal RST for receiving the reset source signal rst_in, so as to prompt the flip-flops FF1˜FFn to respectively perform reset operations according to the reset source signal rst_in. Generally speaking, the circuit connection paths from the reset source signal rst_in to the reset terminals RST of the flip-flops FF1˜FFn, ie, P1, P2 . . . Pn are different. For convenience of description, it is assumed that the path P1 from the reset source signal rst_in to the flip-flop FF1 is the shortest, and the path Pn from the reset source signal rst_in to the flip-flop FFn is the longest. In order to enable the flip-flops FF1 to FFn to perform reset operations synchronously, in the prior art, two delay buffers Buf are inserted in the path P1, and one delay buffer Buf is inserted in the path P2 at the same time, so that the reset source signal rst_in passes through a predetermined After a time delay, it reaches the flip-flops FF1 and FF2, and prompts the flip-flops FF1-FFn to perform reset operation synchronously.

However, since a certain number of delay buffers must be inserted in the above-mentioned reset system according to the length of the circuit connection path from the reset source signal to the flip-flop, the complexity of IC chip design and chip area are increased. Especially for large-scale integrated circuit chip design, if the received reset source signal is still synchronized by adding a delay buffer, it will greatly increase the design difficulty and cost of the integrated circuit chip.

Contents of the invention

The object of the present invention is to provide an integrated circuit reset system and an integrated circuit reset method, which can be applied to large-scale integrated circuits and have lower cost.

The present invention provides a reset system for completing the reset operation of an integrated circuit chip, which includes: a delay module receiving a reset source signal and a reference clock signal to generate a system reset signal and a synchronization signal; a clock The control signal generation module receives the system reset signal, the synchronization signal and the reference clock signal to generate a clock control signal, and the clock control signal generation module makes all the The above clock control signal is valid; and a latch unit determines whether to output the system clock signal according to the received reference clock signal and the clock control signal.

The invention provides a reset method for completing the reset operation of an integrated circuit chip, which includes: generating a synchronization signal synchronized with a reference clock signal according to a reset source signal; performing a delay operation on the synchronization signal to obtain a system reset signal; generate a clock control signal according to the synchronization signal and the system reset signal to determine whether to output a system clock signal; and output the system reset signal to perform a reset operation, wherein when the synchronization signal changes from a valid state to an invalid After the state, make the clock control signal valid, so that the output system clock signal is in an invalid state.

The present invention realizes the synchronous operation of the asynchronous reset by controlling the output of the system clock signal sent to the integrated circuit chip, so there is no need to add a delay buffer in the circuit connection path, thereby reducing the complexity of the circuit design and reducing the chip's area.

Description of drawings

FIG. 1 is a schematic structural diagram of a reset system in the prior art.

FIG. 2 is a schematic structural diagram of a reset system according to an embodiment of the present invention.

FIG. 3 is a timing diagram of control signals of the reset system shown in FIG. 2 .

FIG. 4 is a schematic structural diagram of a reset system according to another embodiment of the present invention.

Detailed ways

The above and other objects and features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings exemplarily showing an example.

The invention completes the synchronous operation of the asynchronous reset of the integrated circuit by controlling the output of the system clock signal. The reset system of the present invention will be described in detail below with reference to the accompanying drawings.

Please refer to FIG. 2 , the reset system 100 according to an embodiment of the present invention generates a system reset signal 111 and a system clock signal 311 to the design chip 500 according to the received reset source signal rst_in and the reference clock signal clock_in, so that the design chip 500 The flip-flops FF1 ~ FFn of the reset operation.

The reset system 100 of this embodiment includes a delay module 1 , a clock control signal generation module 2 , and a latch unit 3 . The delay module 1 performs synchronization and delay operations on the reset source signal rst_in according to the received reference clock signal clock_in, and outputs a synchronization signal 101 and a system reset signal 111 . The flip-flops FF1 - FFn in the design chip 500 perform a reset operation according to the system reset signal 111 . The clock control signal generation module 2 receives the synchronization signal 101 and the system reset signal 111 to output a clock control signal 221 . The latch unit 3 receives the clock control signal 221 and the reference clock signal clock_in, and determines whether to output the system clock signal 311 according to the clock control signal 221 .

The delay module 1 can be further divided into a synchronization unit 10 and a delay unit 11 . The synchronization unit 10 is composed of a flip-flop D1 and a flip-flop D2. The input terminal of the flip-flop D1 receives the voltage VDD and a reference clock signal clock_in, and the reset terminal RST receives the reset source signal rst_in for reset operation. The flip-flop D2 receives the signal output by the flip-flop D1 and the reference clock signal clock_in to output the synchronization signal 101 , and performs a reset operation according to the reset source signal rst_in. As known to those skilled in the art, the reset source signal rst_in achieves the effect of synchronizing with the reference clock signal clock_in after the operation of the flip-flop D1 and the flip-flop D2, and when the reset source signal rst_in is active (assuming that the low level is active), The synchronization signal 101 output by the flip-flop D2 is at low level. The delay unit 11 receives the synchronization signal 101 , the reference clock signal clock_in and the reset source signal rst_in to delay the synchronization signal 101 . In this embodiment, the delay module 11 is composed of three sequentially connected flip-flops D3, D4, and D5, so that the system reset signal 111 output by the flip-flop D5 is delayed by 3 times relative to the synchronization signal 101 received by the flip-flop D3 clock cycle.

The clock control signal generation module 2 includes an exclusive OR gate 20 , an inverter 21 and a flip-flop 22 . The XOR gate 20 performs an XOR operation on the received synchronization signal 101 and the system reset signal 111 to output a signal 201 . The inverter 21 inverts the signal 201 to generate a pre-latch signal 210 . The flip-flop 22 receives the pre-latch signal 210 and the reference clock signal clock_in to obtain a clock control signal 221 synchronized with the reference clock signal clock_in.

The latch unit 3 is composed of a latch 30 and a clock gate 31 . The latch 30 performs a falling-edge active synchronous operation on the clock control signal 221 and the reference clock signal clock_in to output the signal 301 . The clock gate 31 receives the signal 301 output by the latch 30 and the reference clock signal clock_in to control the output of the system clock signal 311 according to the signal 301 . In this embodiment, the clock gate 31 is an AND gate. Since the clock control signal 221 is output to the clock gate 31 after being synchronized by the latch 30 , glitches in the system clock signal 311 output by the clock gate 31 can be prevented.

For those skilled in the art, the above embodiment is only a preferred example for realizing the present invention. Those skilled in the art can have different implementations based on the disclosure scope of the present invention based on the above description. For example, the clock control signal generation module 2 can also be made up of AND gates or other logic components, so that the clock control signal generation module 2 can make the clock control signal 221 effective results. Similarly, the latch unit 3 , which determines whether to output the system clock signal 311 according to the received reference clock signal clock_in and the clock control signal 221 , can also be composed of different logic components to produce the same effect.

In order to clearly disclose the present invention, the following will describe how the reset system of the present invention realizes the synchronous reset operation of the designed chip by controlling the output of the system clock signal in combination with the waveform diagrams of the above-mentioned control signals.

Please refer to FIG. 3 , assuming that the reset source signal rst_in is active at low level, and the reset source signal rst_in changes from an inactive state to an active state during the period T3 of the reference clock signal clock_in, that is, the design chip 500 needs to be reset. The synchronization module 10 then performs a synchronous operation on the reset source signal rst_in according to the reference clock signal clock_in to generate a synchronization signal 101 with a difference of one clock period from the reset source signal rst_in, that is, the synchronization signal 101 is valid during clock periods T3-T5. Subsequently, the triggers D3, D4, and D5 of the delay unit 11 sequentially delay the synchronous signal 101, so that the system reset signal 111 output by the delay unit 11 is delayed by 3 clock cycles relative to the synchronous signal 101, that is, the system The reset signal 111 is valid during clock periods T3-T8. At this time, the flip-flops FF1 - FFn in the design chip 500 can perform a reset operation according to the received system reset signal 111 . The XOR gate 20 performs an XOR operation on the synchronization signal 101 and the system reset signal 111 , and the inverter 21 inverts the signal 201 output by the XOR gate 20 to obtain a pre-latch signal 210 . Obviously, when the synchronization signal 101 and the system reset signal 111 are both active, the pre-latch signal 210 is at a high level; when the synchronization signal 101 changes from an active state to an invalid state while the system reset signal 111 is still active, The pre-latch signal 210 becomes active; when the synchronization signal 101 and the system reset signal 111 are both inactive, the pre-latch signal 210 changes from the active state to the invalid state, that is to say, the pre-latch signal is in the clock cycle T6～ T8 is a valid state. Since the clock control signal 221 is obtained after the pre-latch signal 210 is synchronously processed by the flip-flop 22, the clock control signal 221 becomes an active state/inactive state after a clock cycle delay relative to the pre-latch signal 210, that is, the clock control signal 221 Signal 221 is valid during clock periods T7-T9. Since the latch 30 is based on the reference clock signal clock_in to latch the clock control signal 221 on a falling edge, and the clock gate 31 controls the output of the system clock signal 311 based on the signal 301 output by the latch 30, the system clock The signal 311 is in an inactive state between the falling edge of the clock cycle T7 and the falling edge of the clock cycle T10 , that is, remains in a low level state.

It can be seen from the above description that after the received system reset signal is valid, the flip-flops FF1~FFn in the design chip 500 start to reset, and the state of the flip-flops FF1~FFn after the reset operation will remain unchanged until receiving Valid system clock signal 311 . Generally speaking, the system clock signal 311 has some delay before reaching the flip-flops FF1 - FFn of the design chip 500 , and the system reset signal 111 also has some delay. In this system, before and after the system reset signal 111 becomes invalid, the system clock signal 311 is controlled to be in an invalid state to ensure that each flip-flop FF1-FFn in the design chip 500 changes from valid to invalid when the system reset signal 111 is inactive. There will be no clock edge at this time to ensure the setup and hold time between them. In this way, before the synchronous system clock signal 311 is sent to the design chip 500, the flip-flops FF1-FFn have been reset, so the flip-flops of the design chip 500 can perform normal logic after receiving the normally output system clock signal 311 respectively. operation. On the other hand, as shown in FIG. 3 , within a period of time after the reset source signal rst_in becomes active, the system clock signal 311 will still be output normally, so the reset system of the present invention can be realized by designing the chip 500 through some specific software. reset operation. For example, the time during which the system reset signal remains active can be set by software.

FIG. 4 is a schematic structural diagram of a reset system according to another embodiment of the present invention. It should be noted that the same elements in FIG. 4 and FIG. 2 are marked with the same reference numerals.

As known to those skilled in the art, the reset system of an embodiment of the present invention shown in FIG. 2 can adjust the duration of the system reset signal by changing the number of flip-flops in the delay unit 11 . The reset system shown in FIG. 4 changes the effective time of the system clock signal by adjusting the frequency of the reference clock signal. As shown in FIG. 4 , the reference clock signal clock_in is output to the delay module 1 and the clock control signal generation module 2 after frequency division by the clock frequency division unit 6 , so as to increase the clock period. For example, the clock frequency division unit 6 divides the frequency of the received reference clock signal clock_in by 1/2 to obtain a clock signal 60 , that is, the period of two reference clock signals clock_in is equal to the period of one clock signal 60 . In this way, the synchronization unit 10 performs a synchronization operation on the reset source signal rst_in according to the clock signal 60 and then outputs a synchronization signal 101 . The synchronization signal 101 at this time is delayed by two cycles of the reference clock signal clock_in relative to the reset source signal rst_in. Obviously, the system reset signal 111 output by the delay unit 11 is delayed by six reference clock signal clock_in cycles relative to the synchronous signal 101. Therefore, relative to the reset system shown in FIG. 2 of the present invention, the system reset signal in this embodiment The effective time of 111 is doubled, so that the flip-flops FF1˜FFn in the design chip 500 have more sufficient time for reset operation.

The reset system disclosed by the present invention has the following advantages:

1. To avoid the time delay for the system reset signal to be transmitted to each flip-flop, so that after each flip-flop completes the reset, it receives the system clock signal and enters the normal operation mode. This effect can effectively improve the reliability of the system.

2. The system design does not need to consider the time delay of the system reset signal being transmitted to each flip-flop, which simplifies the limitation of circuit wiring design.

3. Can support reset request generated by software. A reset request by software must be completed while the hardware is still in normal operation. When the reset system of the present invention receives the reset source signal, it continues to output the system clock signal through the delay module, so that the lower-level hardware can still be in normal operation, so that the system can continue to work and complete the reset.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

Claims (14)

1. A reset system, used to complete the reset operation of the integrated circuit chip, is characterized in that, comprising: A delay module, receiving a reset source signal and a reference clock signal to generate a system reset signal and a synchronization signal; A clock control signal generation module, receiving the system reset signal, synchronization signal and reference clock signal to generate a clock control signal, after the synchronization signal received by the clock control signal generation module changes from the valid state to the invalid state, asserting the clock control signal; and A latch unit decides whether to output the system clock signal according to the received reference clock signal and the clock control signal. 2. The reset system according to claim 1, characterized in that, when the synchronization signal received by the clock control signal generation module and the system reset signal are both in an active state, the clock control signal output by the clock control signal generation module is invalid. 3. The reset system according to claim 1, wherein when the synchronization signal received by the clock control signal generating module is in an invalid state and the system reset signal is in an active state, the clock control signal generating module outputs The clock control signal is active. 4. The reset system according to claim 1, wherein when the synchronization signal received by the clock control signal generation module and the system reset signal are both in an invalid state, the clock control signal output by the clock control signal generation module is invalid. 5. The reset system according to any one of claims 1 to 4, wherein the clock control signal generating module comprises: an exclusive OR gate, receiving the synchronization signal and the system reset signal; and An inverter for inverting the signal output by the XOR gate and outputting a pre-latch signal. 6 . The reset system according to claim 5 , wherein the clock control signal generating module further comprises a flip-flop for receiving the pre-latch signal and a reference clock signal to output the clock control signal. 7. The reset system according to claim 1, wherein the delay module comprises: a synchronization unit, which performs a synchronous operation on the reset source signal and the reference clock signal, and outputs the synchronization signal; and A delay unit receives the synchronization signal output by the synchronization unit, and outputs the system reset signal after delaying the synchronization signal. 8. The reset system according to claim 1, wherein the latch unit comprises: a latch whose control terminal receives the reference clock signal and whose input terminal receives the clock control signal; and A clock gate receives the signal output by the latch and a reference clock signal. 9. The reset system according to claim 8, wherein, when the clock control signal received by the latch is in an active state, the system clock signal output by the clock gate is in an invalid state. 10. The reset system according to claim 1, further comprising a clock frequency division unit, which performs frequency division processing on the received reference clock signal and outputs it to the delay module. 11. A reset method, used to complete the reset operation of the integrated circuit chip, is characterized in that, comprising: generating a synchronous signal synchronous with the reference clock signal according to the reset source signal; Delaying the synchronization signal to obtain a system reset signal; generating a clock control signal according to the synchronization signal and the system reset signal to determine whether to output a system clock signal; and Output the system reset signal for reset operation, where: When the synchronization signal changes from the valid state to the invalid state, the clock control signal is made valid so that the output system clock signal is in the invalid state. 12 . The reset method according to claim 11 , wherein when both the synchronization signal and the system reset signal are active, the clock control signal is disabled to output a system clock signal. 13 . 13. The reset method according to claim 11, wherein when the synchronization signal is in an invalid state and the system reset signal is in an active state, the clock control signal is enabled. 14. The reset method according to claim 11, wherein when both the synchronization signal and the system reset signal are in an invalid state, the clock control signal is invalidated to output a system clock signal.

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