CN101018048A - Oscillation circuit - Google Patents

Abstract

The first comparison circuit outputs a first signal indicating that the voltage corresponding to the amount of charge stored in the first capacitor reaches a first standard voltage. The second comparison circuit outputs a second signal indicating that the voltage corresponding to the amount of charge stored in the second capacitor reaches a second standard voltage. The RS flip-flop circuit is in a fixed state by one of the first signal and the second signal, and is in a reset state by the other. When the RS flip-flop circuit is in a fixed state, the first capacitor is in a charging state, and the second capacitor is in a discharging state. When the RS flip-flop circuit is in a recovery state, the first capacitor is in a discharged state, and the second capacitor is in a charged state.

Description

oscillator circuit

technical field

The present invention relates to an oscillating circuit for supplying stable signals to semiconductor integrated circuits and the like.

Background technique

In recent years, semiconductor integrated circuits, due to the refinement of the production process, have led to a decrease in operating voltage, so it is easy to cause malfunction due to noise. Therefore, semiconductor integrated circuits such as personal microcomputers are required to be less susceptible to interference.

On the other hand, as a conventional oscillation circuit, an oscillation circuit using a count flip-flop (toggle flip-flop) capable of obtaining a triangular wave oscillation output is known. (Refer to Patent Publication No. Hei 5-226984)

Here, a triangular wave oscillator circuit configured as shown in Publication No. Hei 5-226984 (Hei 5 = 1993) will be described.

The capacitor 105 is charged by the current generated by the stationary power source 101 when the switch 102 is in the closed state.

The capacitor 105a is charged by the current generated by the stationary power source 101a when the switch 102a is in the closed state.

The switch 102 is closed when the output signal Q of the count flip-flop 23 is at a high level, and is opened when it is at a low level.

为高电平时关闭，在低电平时开启。switch 102a, the output signal of the count flip-flop 23

Closed when high level, open when low level.

变得比基准电压V_R1高时，输出高电平的输出信号CM。comparator 21, when the output voltage Vo of the capacitor 105 becomes higher than the reference voltage _VR1 , and when the output voltage of the capacitor 105a

When it becomes higher than the reference voltage V _R1 , a high-level output signal CM is output.

分别被反转。If the high-level output signal CM is output to the count flip-flop 23, the output signal Q and the output signal

are reversed respectively.

输出电压

以及输出电压Vo的波形，如图专利公开平5-226984号公报的图3所示。(平5＝1993年)With the above configuration, when the switch 22 is in the closed state on the side of the contact point f, the output signal CM, the output signal Q, the output signal

The output voltage

And the waveform of the output voltage Vo is shown in FIG. 3 of Patent Publication No. Hei 5-226984. (flat 5 = 1993)

(The problem to be solved by the invention)

的波形相位，从安定的周期波形相位偏离近半个周期。However, in the conventional oscillation circuit described above, the period of the output signal Q is very likely to be unstable due to noise. For example, when the capacitor 105 is charged, the output voltage Vo fluctuates before and after the standard voltage V _R1 due to interference, thereby causing the output signal CM to rise several times, and the output signal Q of the counting flip-flop 23 is inverted during this period . In the example of FIG. 9 , during the interval from time A to time B, the output signal Q is always at low level without disturbance, but becomes high level in the middle. As a result, the output signal Q and the output signal

The waveform phase of , deviates from the stable periodic waveform phase by nearly half a cycle.

Contents of the invention

The present invention is made in view of the above-mentioned problems. Its purpose is to provide an oscillation circuit that provides a stable periodic signal even when a disturbance occurs.

(for a solution to the problem)

In order to solve the above-mentioned problems, a first oscillation circuit according to an embodiment of the present invention includes:

The current generated by the power supply charges and discharges the first and second capacitors,

comparing the first voltage corresponding to the amount of charge stored in the first capacitor with the first standard voltage, and outputting a first signal indicating that the first voltage reaches the first standard voltage, a first comparison circuit,

comparing a second voltage corresponding to the amount of charge stored in the second capacitor with a second standard voltage, and outputting a second signal indicating that the second voltage has reached the second standard voltage, a second comparator circuit,

an RS flip-flop circuit in which one of the above-mentioned first signal and the above-mentioned second signal is in a fixed state and the other one of them is in a recovery state,

A first charge and discharge control circuit that makes the first capacitor in a charging state when the RS flip-flop circuit is in a fixed state and in a discharging state when the RS flip-flop circuit is in a recovery state,

The second charge-discharge control circuit is characterized in that the second capacitor is in a charging state when the RS flip-flop circuit is in a recovery state, and is in a discharging state when the RS flip-flop circuit is in a fixed state.

According to the first oscillating circuit, even if one of the first voltage and the second voltage fluctuates before and after the standard voltage due to disturbance, the number of inversions of the output of the RS flip-flop circuit becomes the same as when there is no disturbance. Therefore, the RS flip-flop circuit can output a stable periodic signal.

The second oscillation circuit according to the embodiment of the present invention includes:

The current generated by the power supply charges and discharges the first and second capacitors,

comparing the first voltage corresponding to the amount of charge stored in the first capacitor with the first standard voltage, and outputting a first signal indicating that the first voltage reaches the first standard voltage, a first comparison circuit,

comparing a second voltage corresponding to the amount of charge stored in the second capacitor with a second standard voltage, and outputting a second signal indicating that the second voltage has reached the second standard voltage, a second comparator circuit,

a first RS flip-flop circuit that is in a fixed state by the first signal output from the first comparison circuit and in a recovery state by the second signal output by the second comparison circuit in the fixed state,

a second RS flip-flop circuit that is in a fixed state by the second signal output from the second comparator circuit and in a reset state by the first signal output by the first comparator circuit in the fixed state,

an inverting flip-flop circuit that inverts output when the first RS flip-flop circuit transitions from the recovery state to the fixed state, and when the second RS flip-flop circuit transitions from the recovery state to the fixed state,

Selective conversion: corresponding to the output of the above-mentioned inverting flip-flop circuit, the state of charging the first capacitor and discharging the second capacitor, and discharging the first capacitor while discharging the second capacitor It is characterized by the charge and discharge control circuit in the state of capacitor charge.

According to the second oscillation circuit, even if the first voltage fluctuates before and after the standard voltage due to noise, the number of rises of the output of the first RS flip-flop circuit becomes the same as when there is no noise. Similarly, even if the second voltage fluctuates before and after the standard voltage due to noise, the number of rises of the output of the second RS flip-flop circuit becomes the same as in the case of no noise. Therefore, the inverted flip-flop circuit can output a stable periodic signal.

The third oscillation circuit according to the embodiment of the present invention,

is in the second oscillator circuit,

The above fixed state is the state where the output is high level,

The above recovery state is the state where the output is low level,

Also includes:

When the output of the first RS flip-flop circuit rises, the first one-shot circuit that outputs a high-level first pulse signal,

When the output of the above-mentioned second RS flip-flop circuit rises, the second one-shot circuit that outputs a high-level second pulse signal,

an "OR" circuit that outputs the "OR" of the above-mentioned first pulse signal and the above-mentioned second pulse signal, and in addition

The above-mentioned inversion flip-flop circuit is characterized in that it is configured to invert the output on the rising edge or falling edge of the above-mentioned "OR" circuit.

The fourth oscillating circuit according to the embodiment of the present invention includes:

The first capacitor charged by the current generated by the power supply,

The voltage corresponding to the amount of electric charge stored in the first capacitor is outputted in the interval between the charge rises to the first standard voltage and then falls to the second standard voltage lower than the first standard voltage, and outputs the second voltage of the first signal. a comparison circuit, or

The first capacitor is discharged by the current generated by the power supply,

The voltage corresponding to the amount of electric charge stored in the first capacitor is outputted in the interval between the charge falling to the first standard voltage and then rising to the second standard voltage higher than the first standard voltage. a comparator circuit, one of which also includes:

The second capacitor is charged by the current generated by the power supply,

The voltage corresponding to the amount of electric charge stored in the second capacitor is outputted in the interval between the charge rises to the third standard voltage and then drops to the fourth standard voltage lower than the third standard voltage, and the second signal of the second signal is output. Two comparator circuits, or

The second capacitor is discharged by the current generated by the power supply,

A voltage corresponding to the amount of charge stored in the second capacitor is output from the second signal during the interval from when the charge drops to the third standard voltage and then rises to the third standard voltage higher than the third standard voltage. Two comparator circuits, one of which also includes:

an inversion flip-flop circuit that inverts the output whenever the above-mentioned first signal or second signal is output,

The charge-discharge control circuit is characterized by a charge-discharge control circuit that selectively switches between charging the first capacitor and discharging the second capacitor, and discharging the first capacitor while charging the second capacitor.

According to the fourth oscillating circuit, even if a disturbance occurs, as long as the voltage corresponding to the amount of charge stored in the first capacitor reaches the second standard voltage, or the voltage corresponding to the amount of charge stored in the second capacitor does not reach the fourth standard voltage, in the reverse No disturbing effects will appear in the output of the flip-flop circuit. Therefore, the inverted flip-flop circuit can output a signal with a stable cycle.

The fifth oscillating circuit according to the embodiment of the present invention is in any one of the first, second, and fourth oscillating circuits, with

The above-mentioned first and second capacitors are characterized in that they are charged or discharged by current generated by the same power source.

According to the fifth oscillating circuit, since the first and second capacitors are charged or discharged by the same current, an oscillating signal with a repetition ratio (Duty ratio) of 50% can be obtained.

The sixth oscillation circuit according to the embodiment of the present invention,

is in the first oscillator circuit to

The above-mentioned first and second charge and discharge control circuits are configured to connect respective one ends of the above-mentioned first and second capacitors to a power supply during charging, and connect respective one ends of the above-mentioned first and second capacitors to a power supply during discharging. The two ends are separated, which is characteristic.

The seventh oscillation circuit according to the embodiment of the present invention,

is in any one of the second and fourth oscillator circuits, with

The charging and discharging control circuit is characterized in that one end of the first and second capacitors is connected to a power source for charging, and the two ends of the first and second capacitors are separated and discharged.

Description of drawings

FIG. 1 is a block diagram showing the configuration of an oscillation circuit according to the first embodiment.

FIG. 2 is a block diagram showing the configurations of the first charge and discharge control circuit 109 and the charge and discharge control circuit 110 according to the first embodiment.

FIG. 3 is a pulse diagram showing the operation of the oscillation circuit according to the first embodiment.

FIG. 4 is a block diagram showing the configuration of an oscillation circuit according to the second embodiment.

FIG. 5 is a block diagram showing the configuration of the one-shot circuits 204 and 205 according to the second embodiment.

FIG. 6 is a pulse diagram showing the operation of the oscillation circuit according to the second embodiment.

FIG. 7 is a block diagram showing the configuration of an oscillation circuit according to the third embodiment.

FIG. 8 is a pulse diagram showing the operation of the oscillation circuit according to the third embodiment.

Fig. 9 is a block diagram showing the configuration of a conventional oscillation circuit.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, components having the same functions as those in other embodiments are denoted by the same reference numerals and descriptions thereof are omitted.

"Embodiment 1 of the invention"

The oscillation circuit of Embodiment 1, as shown in FIG. 1 , includes: a power supply circuit 101, a first capacitor 102, a second capacitor 103, a standard power supply 104, a comparison circuit 105, an inverting circuit 106, a comparison circuit 107, and an RS flip-flop circuit 108 , the first charge and discharge control circuit 109 , and the second charge and discharge control circuit 110 . The oscillation circuit of this embodiment is provided in a semiconductor integrated circuit.

The standard power supply 104 generates a standard voltage.

The comparison circuit 105 compares the voltage V1 corresponding to the charge stored in the first capacitor 102 with the standard voltage Vst, and outputs a low level when the voltage V1 is high, and outputs a high level when the standard voltage Vst is high.

The comparison circuit 107 compares the voltage V2 corresponding to the charge stored in the second capacitor 103 with the standard voltage Vst, and outputs a low level when the voltage V2 is high, and outputs a high level when the standard voltage Vst is high.

The RS flip-flop circuit 108 is in a fixed state by the high-level output (first signal) of the inverter circuit 106, and is in a reset state by the low-level output (second signal) of the comparison circuit 107. Then, the output signal Q and the inverted output signal QB of the inverted signal of the output signal Q are output.

The first charge and discharge control circuit 109, as shown in FIG. 2, includes a PMOS transistor 109a and an NMOS transistor 109b. The output signal Q of the RS flip-flop circuit 108 is input to these gates. With such a configuration, the first charge and discharge control circuit 109 controls the charge supply from the power supply circuit 101 to the first capacitor 102 . More specifically, the first charge and discharge control circuit 109 makes the first capacitor 102 into a discharge state when the output signal Q is at a high level (when the RS flip-flop circuit 108 is in a fixed state), and when the output signal Q is at a low level ( When the RS flip-flop circuit 108 enters the recovery state), it becomes the charging state.

The second charge and discharge control circuit 110, as shown in FIG. 2, includes a PMOS transistor 110a and an NMOS transistor 110b. The inverted output signal QB of the RS flip-flop circuit 108 is input to their gates. With such a configuration, the second charge and discharge control circuit 110 controls the charge supply from the power supply circuit 101 to the second capacitor 103 . More specifically, the second charge and discharge control circuit 110 makes the second capacitor 103 into a discharge state when the inverted output signal QB is at a high level (when the RS flip-flop circuit 108 is in a recovery state), and the inverted output signal QB is When the level is low (when the RS flip-flop circuit 108 is in a fixed state), it becomes a charging state.

Next, the operation of the oscillator circuit configured as described above will be described with reference to the pulse diagram of FIG. 3 . The pulse diagram of FIG. 3 shows the waveforms of the respective signals when the disturbance voltage V2 exceeds the standard voltage Vst between time B and time C. As shown in FIG.

At time A in FIG. 3 , if a high level signal is input to the S terminal of the RS flip-flop circuit 108, the output signal Q changes from low level to high level, and the inverted output signal QB changes from high level to low level. flat. When the output signal Q becomes a high level, the first charge and discharge control circuit 109 discharges the charge stored in the first capacitor 102 to the ground side. As a result, the voltage V1 of the first capacitor 102 drops from a high level to a low level. On the other hand, when the inverted output signal QB becomes low level, the second charge and discharge control circuit 110 performs an operation of charging the second capacitor 103 . As a result, the voltage V2 of the second capacitor 103 rises corresponding to the stored electric charges.

The voltage V2 of the second capacitor 103 continues to rise due to charging from time A to time B when it exceeds the standard voltage Vst. Between time A and time B, the signal input to the R terminal, that is, the output of the comparison circuit 107 becomes high level. During this period, the output signal Q of the RS flip-flop circuit 108 maintains a high level, and the inverted output signal QB maintains a low level. In addition, the voltage V1 of the first capacitor 102 starts to drop at time A, once it reaches a low level, it remains low until time B.

If the voltage V2 of the second capacitor 103 exceeds the standard voltage Vst at time B, the output of the comparison circuit 107, that is, the comparison result becomes low level, and a low level signal is input to the R terminal of the RS flip-flop circuit 108 . As a result, the output signal Q of the RS flip-flop circuit 108 changes from high level to low level, and the inverted output signal QB changes from low level to high level. When the inverted output signal QB becomes high level, the second charge and discharge control circuit 110 performs an action of releasing the charge stored in the second capacitor 103 to the ground side. As a result, the voltage V2 of the second capacitor 103 drops from a high level to a low level. On the other hand, when the output signal Q becomes low level, the first charge and discharge control circuit 109 performs an operation of charging the first capacitor 102 . As a result, the voltage V1 of the first capacitor 102 rises corresponding to the storage of the charge.

The voltage V1 of the first capacitor 102 continues to rise due to charging from time B to time C when it exceeds the standard voltage Vst. Between time B and time C, the output signal Q of the RS flip-flop circuit 108 maintains a low level, and the inverted output signal QB maintains a high level. In addition, the voltage V2 of the second capacitor 103 starts to drop at time B, and once it reaches a low level, it stays at a low level until time C.

Here, the RS flip-flop circuit 108 does not change the output until a high-level signal is input to the S terminal once a low-level signal is input to the R terminal and the low-level signal is maintained. Therefore, as shown in FIG. 3, between time B and time C, the voltage V2 exceeds the standard voltage Vst due to interference, even if a low-level signal is input to the R terminal of the RS flip-flop circuit 108, the RS flip-flop circuit 108 The output signal Q and the inverted output signal QB do not change.

If the voltage V1 of the first capacitor 102 exceeds the standard voltage Vst at time C, the output of the comparison circuit 105 , that is, the comparison result becomes low level, and a low level signal is input to the S terminal of the RS flip-flop circuit 108 .

As described above, by repeating the operation in the period from time A to time C, the output signal Q of the oscillation signal and the inverted output signal QB are obtained.

As such, the oscillation circuit of this embodiment can provide the output signal Q and the inverted output signal QB of a stable cycle without being affected by noise.

Also, only by using a comparator circuit using a hysteresis to prevent the influence of noise, the range of noise that can be prevented from affecting is also increased.

In addition, the oscillation circuit of this embodiment can be easily incorporated into a semiconductor integrated circuit due to its simple structure, a small number of components and a small circuit area.

"Embodiment 2 of the invention"

The oscillating circuit of Embodiment 2, as shown in FIG. 4 , includes: a power supply 101, a first capacitor 102, a second capacitor 103, a standard power supply 104, a comparison circuit 105, an inverting circuit 106, a comparison circuit 107, and a first charge and discharge control circuit. Circuit 109, second charge and discharge control circuit 110, inverting circuit 201, RS flip-flop circuits 202, 203 (first and second RS flip-flop circuits), one-shot circuits 204, 205 (first and second one-shot circuits ), NAND circuits 206, 207, OR circuit 208 ("OR" circuit), and flip-flop circuit 209.

The one-shot circuits 204 and 205 each output a pulse of a predetermined width when the input signal rises. Specifically, as shown in FIG. 5 , inverter circuits 204 a to 204 c , a NAND circuit 204 d , and an inverter circuit 204 e are respectively included. The inverter circuits 204a to 204c delay the input signal by a sufficient delay amount so that the NAND circuit 204d outputs a pulse having a necessary width. In order to increase the amount of delay, it is also possible to use an inverter with a low driving capability.

Note that the configuration of the one-shot circuits 204 and 205 is not limited to the configuration shown in FIG. 5 . For example, in this embodiment, the number of converters before the NAND circuit 204d is three, but it is not limited to three, and a combination of buffers and inverters may also be used.

In addition, in the first charge and discharge control circuit 109, the inverted output signal QB of the inverted flip-flop circuit 209 is input to the gates of the PMOS transistor 109a and the NMOS transistor 109b. Furthermore, in the second charge and discharge control circuit 110, the output signal Q of the inversion flip-flop circuit 209 is input to the gates of the PMOS transistor 110a and the NMOS transistor 110b.

Next, the operation of the oscillation circuit configured as described above will be described with reference to the pulse diagram of FIG. 6 . The pulse diagram of FIG. 6 shows the waveforms of the respective signals due to the disturbance voltage V2 exceeding the standard voltage Vst between time B and time C.

At time A in FIG. 6, when the signal CK output from the OR circuit 208 reaches a high level, the output signal Q of the inversion flip-flop circuit 209 changes from a low level to a high level, and the inversion of the inversion flip-flop circuit 209 The output signal QB changes from high level to low level. When the output signal Q becomes high level, the second charge and discharge control circuit 110 performs an action of releasing the charge stored in the second capacitor 103 to the ground side. As a result, the voltage V2 of the second capacitor 103 drops from a high level to a low level. On the other hand, when the inverted output signal QB becomes low level, the first charge and discharge control circuit 109 performs an operation of charging the first capacitor 102 . As a result, the voltage V1 of the first capacitor 102 rises corresponding to the stored electric charges.

The voltage V1 of the first capacitor 102 continues to rise due to charging from time A to time B when it exceeds the standard voltage Vst. During this period, the output signal Q1 of the RS flip-flop circuit 202 becomes low level. In addition, the output signal Q2 of the RS flip-flop circuit 203 becomes high level. Moreover, from time A to time B, the output signal Q of the inversion flip-flop circuit 209 maintains a high level, and the inversion output signal QB maintains a low level. Also, the voltage V2 of the second capacitor 103 starts to drop at time A, once it reaches a low level, it remains low until time B.

If the voltage V1 of the first capacitor 102 exceeds the standard voltage Vst at time B, the output of the comparison circuit 105 , that is, the comparison result becomes a low level. Furthermore, the inverter circuit 106 inverts the low-level output of the comparator circuit 105 , and a high-level signal is input to the S1 terminal of the RS flip-flop circuit 202 . Accordingly, the output signal Q1 of the RS flip-flop circuit 202 becomes high level. When the output signal Q1 becomes high level, the one-shot circuit 204 outputs a high level pulse signal. And, from the OR circuit 208 , a high-level pulse signal is input to the trigger input of the inversion flip-flop circuit 209 as the signal CK. Also, at this time, the output signal Q2 of the RS flip-flop circuit 203 is at a high level, so when the one-shot circuit 204 outputs a high-level pulse signal, the output of the NAND circuit 207 is at a low level. Then, when the low-level output of the NAND circuit 207 is input to the R2 terminal of the RS flip-flop circuit 203, the output signal Q2 is inverted to be low-level.

At time B, if a high-level pulse signal is input to the trigger input of the inversion flip-flop circuit 209, the output signal Q of the inversion flip-flop circuit 209 is inverted from a high level to a low level, and the inversion output signal QB changes from Low level is inverted to high level. Since the inverted output signal QB becomes a high level, the first charge and discharge control circuit 109 discharges the charge stored in the first capacitor to the ground side. As a result, the voltage V1 of the first capacitor 102 drops from a high level to a low level. On the other hand, since the output signal Q becomes low level, the second charge and discharge control circuit 110 performs an operation of charging the second capacitor 103 . As a result, the voltage V2 of the second capacitor 103 rises corresponding to the stored electric charges.

The voltage V2 of the second capacitor 103 rises due to charging between time B and time C when it exceeds the standard voltage Vst. From time B to time C, the output signal Q of the inversion flip-flop circuit 209 maintains a low level, and the inversion output signal QB maintains a high level. In addition, the voltage V1 of the first capacitor 102 starts to drop at time B, and once it reaches a low level, it stays at a low level until time C.

Here, once the RS flip-flop circuit 202 maintains the high level due to the input of the high level signal to the BS1 terminal at time, the output does not change until the low level signal is input to the R1 terminal. Therefore, as shown in FIG. 6, between time B and time C, the voltage V1 exceeds the standard voltage Vst due to interference, even if a high-level signal is input to the S1 terminal of the RS flip-flop circuit 202, the output of the RS flip-flop circuit 202 Signal Q1 also does not change. Therefore, in this case, the output signal Q and the inverted output signal QB of the inverted flip-flop circuit 209 also do not change.

If the voltage V2 of the second capacitor 103 exceeds the standard voltage Vst at time C, the output of the comparison circuit 107, that is, the comparison result becomes low level. Furthermore, the inverting circuit 201 inverts the low-level output of the comparator circuit 107 , and inputs a high-level signal to the S2 terminal of the RS flip-flop circuit 203 . Accordingly, the output signal Q2 of the RS flip-flop circuit 203 becomes high level. Since the output signal Q2 becomes high level, the one-shot circuit 205 outputs a high level pulse signal. And, from the OR circuit 208 , a high-level pulse signal is input to the trigger input of the inversion flip-flop circuit 209 as the signal CK. Also, since the output signal Q1 of the RS flip-flop circuit 202 is at a high level at this time, when the one-shot circuit 205 outputs a high-level pulse signal, the output of the NAND circuit 206 becomes a low level. Then, when the low-level output of the NAND circuit 206 is input to the R1 terminal of the RS flip-flop circuit 202, the output signal Q1 is inverted to be low-level.

At time C, if a high-level pulse signal is input to the trigger input of the inversion flip-flop circuit 209 as the signal CK, the output signal Q of the inversion flip-flop circuit 209 is inverted from low level to high level, and the inversion The output signal QB is inverted from high level to low level.

As described above, by repeating the operation from time A to time C, the output signal Q of the oscillation signal and the inverted output signal QB can be obtained.

In this way, the oscillation circuit of this embodiment can provide the output signal Q and the inverted output signal QB of a stable cycle without being affected by noise.

"Embodiment 3 of the invention"

The oscillating circuit of Embodiment 3, as shown in FIG. 7 , includes: a power supply circuit 101, a first capacitor 102, a second capacitor 103, a standard power supply 104, a first charge and discharge control circuit 109, a second charge and discharge control circuit 110, and a comparison Circuits 301 , 302 (Schmitt circuits), NAND circuit 303 , and flip-flop circuit 209 .

The comparison circuit 301 (the first comparison circuit), when the voltage V1 of the first capacitor 102, exceeds the voltage Vsc (Schmitt voltage) of the specified range (Schmitt range) higher than the standard voltage Vst due to charging, to the voltage Vsc (Schmitt voltage) due to charging. When the discharge becomes the standard voltage Vst, a low-level signal is output, and a high-level signal is output at a time other than this period.

Comparing circuit 302 (second comparing circuit), when the voltage V2 of the second capacitor 103, exceeds the voltage Vsc (Schmitt voltage) of the specified range (Schmitt range) higher than the standard voltage Vst due to charging, to the voltage Vsc (Schmitt voltage) due to charging When the discharge becomes the standard voltage Vst, a low-level signal is output, and a high-level signal is output at a time other than this period.

Next, the operation of the oscillation circuit configured as described above will be described with reference to the pulse diagram of FIG. 8 . The pulse diagram of FIG. 8 shows the waveforms of each signal due to the case where the disturbance voltage V1 exceeds the standard voltage Vst between time A and time B. In FIG.

At time A in FIG. 8, when the signal CK output from the NAND circuit 303 reaches a high level, the output signal Q of the inversion flip-flop circuit 209 changes from a low level to a high level, and the inversion of the inversion flip-flop circuit 209 The output signal QB changes from high level to low level. When the output signal Q becomes high level, the second charge and discharge control circuit 110 performs an action of releasing the charge stored in the second capacitor 103 to the ground side. As a result, the voltage V2 of the second capacitor 103 drops from a high level to a low level. On the other hand, when the inverted output signal QB becomes low level, the first charge and discharge control circuit 109 performs an operation of charging the first capacitor 102 . As a result, the voltage V1 of the first capacitor 102 rises corresponding to the stored electric charges.

The voltage V1 of the first capacitor 102 continues to rise due to charging from time A to time B when it exceeds the standard voltage Vst. During this period, the output signal Q of the inversion flip-flop circuit 209 maintains a high level, and the inversion output signal QB maintains a low level. Also, the voltage V2 of the second capacitor 103 starts to drop at time A, once it reaches a low level, it remains low until time B.

At time B, if the voltage V1 of the first capacitor 102 exceeds the voltage Vsc by a predetermined range higher than the standard voltage Vst, the output of the comparison circuit 301, that is, the comparison result becomes a low level. And, the signal CK output from the NAND circuit 303 becomes high level.

When the signal CK that has become a high level is input to the trigger input of the inversion flip-flop circuit 209, the output signal Q of the inversion flip-flop circuit 209 is inverted from a high level to a low level, and the inverted output signal QB is changed from a low level to a low level. Flat inversion is high level. Since the inverted output signal QB becomes a high level, the first charge and discharge control circuit 109 discharges the charge stored in the first capacitor to the ground side. As a result, the voltage V1 of the first capacitor 102 drops from a high level to a low level. On the other hand, since the output signal Q becomes low level, the second charge and discharge control circuit 110 performs an operation of charging the second capacitor 103 . As a result, the voltage V2 of the second capacitor 103 rises corresponding to the stored electric charges.

Here, as shown in FIG. 8, even if the voltage V1 around the time B changes before and after the standard voltage Vst due to noise, when the voltage of the comparison circuit 301 rises, the voltage V1 is higher than the standard voltage Vst by a predetermined width (Vsc- Vst) is compared with the voltage Vsc, so this effect does not appear in the output signal Q. That is, even if the disturbance voltage V1 exceeds the standard voltage Vst, as long as it does not exceed Vsc, a high-level pulse signal is not input to the trigger input of the inversion flip-flop circuit 209 .

The voltage V2 of the second capacitor 103 continues to rise due to charging from time B to time C when the voltage Vsc exceeds the standard voltage Vst and exceeds the predetermined width. From time B to time C, the output signal Q of the inversion flip-flop circuit 209 maintains a low level, and the inversion output signal QB maintains a high level. In addition, the voltage V1 of the first capacitor 102 starts to drop at time B, and once it reaches a low level, it stays at a low level until time C.

If the voltage V2 of the second capacitor 103 exceeds the range Vsc specified by the standard voltage Vst at time C, the output of the comparison circuit 302 , that is, the comparison result becomes a low level. And, the signal CK output from the NAND circuit 303 becomes high level.

When the signal CK that becomes high level is input to the trigger input of the inversion flip-flop circuit 209, the output signal Q of the inversion flip-flop circuit 209 is inverted from low level to high level, and the inverted output signal QB is changed from high level to high level. Flat inversion is low level.

As described above, by repeating the operation from time A to time C, the output signal Q of the oscillation signal and the inverted output signal QB can be obtained.

In this way, even if there is interference in the oscillation circuit of this embodiment, as long as the voltage V1 or voltage V2 due to this interference exceeds the standard voltage Vst by a specified range and does not exceed the voltage Vsc, the output signal Q and the inverted output signal will not be affected. QB. Therefore, the oscillation circuit of this embodiment can provide the output signal Q and the inverted output signal QB of a stable cycle, compared with the conventional oscillation circuit.

"Other Implementation Modes"

Furthermore, in the oscillator circuits of the above-described embodiments, the same power supply circuit 101 charges the first capacitor 102 and the second capacitor 103 . However, the first capacitor 102 and the second capacitor 103 can also be charged by different power sources.

In addition, in the oscillating circuits of the above-mentioned embodiments, the first capacitor 102 and the second capacitor 103 are discharged after the two ends of each are separated. However, it is also possible to discharge with a power supply current while the power supply is connected.

In addition, in the oscillation circuits of the above-described embodiments, the period of the output signal Q is controlled in accordance with the time required for charging the capacitor. However, the period of the output signal Q may be controlled according to the time required for discharging the capacitor. Specifically, the first capacitor 102 and the second capacitor 103 are discharged by the current in the power supply circuit, and the voltage of any one of the first capacitor 102 and the second capacitor 103 is lower than the specified standard voltage and is determined by the comparison circuit 105, If detected by 107, the inverted output signal Q and the inverted output signal QB may also be used. In addition, when controlling the cycle of the output signal Q according to the time required for discharging the capacitor, a flip-flop of a comparison circuit can be used as in the oscillation circuit of the third embodiment. Specifically, the standard voltages of the comparison circuits 301 and 302 may be higher when the voltage of the capacitor falls than when it rises.

In the oscillation circuits of Embodiments 2 and 3, the output of the inversion flip-flop circuit 209 is inverted at the rising edge of the signal input to the trigger input, but may be inverted at the falling edge.

-practicability-

The oscillating circuit according to the present invention has the effect of being able to provide a signal with a stable period even when disturbance occurs, and is useful, for example, in an oscillating circuit for supplying a signal with a stable period to a semiconductor integrated circuit.

Claims (7)

1. An oscillating circuit, characterized in that: include: The first and second capacitors are charged and discharged by the current generated by the power supply, The first comparison circuit compares the first voltage corresponding to the amount of charge stored in the first capacitor with the first standard voltage, and outputs a first signal indicating that the first voltage reaches the first standard voltage, The second comparison circuit compares the second voltage corresponding to the amount of charge stored in the second capacitor with the second standard voltage, and outputs a second signal indicating that the second voltage reaches the second standard voltage, In the RS flip-flop circuit, one of the above-mentioned first signal and the above-mentioned second signal is in a fixed state, and the other one of them is in a recovery state, The first charging and discharging control circuit is configured to make the first capacitor in a charging state when the RS flip-flop circuit is in a fixed state, and in a discharging state when the RS flip-flop circuit is in a recovery state, The second charge and discharge control circuit makes the second capacitor in a charging state when the RS flip-flop circuit is in a recovery state, and in a discharging state when the RS flip-flop circuit is in a fixed state. 2. An oscillating circuit characterized by: include: The first and second capacitors are charged and discharged by the current generated by the power supply, The first comparison circuit compares the first voltage corresponding to the amount of charge stored in the first capacitor with the first standard voltage, and outputs a first signal indicating that the first voltage reaches the first standard voltage, The second comparison circuit compares the second voltage corresponding to the amount of charge stored in the second capacitor with the second standard voltage, and outputs a second signal indicating that the second voltage reaches the second standard voltage, The first RS flip-flop circuit is set in a fixed state by the first signal output from the first comparison circuit, and in a reset state by the second signal output by the second comparison circuit in the fixed state, The second RS flip-flop circuit is in a fixed state by the second signal output from the second comparison circuit, and in the fixed state by the first signal output by the first comparison circuit in a recovery state, Inverting the flip-flop circuit, when the above-mentioned first RS flip-flop circuit changes from the recovery state to the fixed state, and when the above-mentioned second RS flip-flop circuit changes from the recovery state to the fixed state, the output is reversed, The charging and discharging control circuit selectively switches: corresponding to the output of the above-mentioned inverting flip-flop circuit, the state of charging the first capacitor while also discharging the second capacitor, and discharging the first capacitor at the same time, A state in which the above-mentioned second capacitor is also charged. 3. The oscillation circuit according to claim 2, characterized in that: The above fixed state is the state where the output is high level, The above recovery state is the state where the output is low level, Also includes: The first one-shot circuit, when the output of the first RS flip-flop circuit rises, outputs a high-level first pulse signal, The second one-shot circuit, when the output of the second RS flip-flop circuit rises, outputs a high-level second pulse signal, The "or" circuit outputs the "or" of the above-mentioned first pulse signal and the above-mentioned second pulse signal, and in addition The above-mentioned inversion flip-flop circuit is configured to invert the output on the rising edge or falling edge of the above-mentioned "OR" circuit. 4. An oscillating circuit characterized by: Include: The first capacitor, charged by the current generated by the power supply, The first comparator circuit outputs a voltage corresponding to the amount of charge stored in the first capacitor during the interval between the charge rises to the first standard voltage and then falls to a second standard voltage lower than the first standard voltage. first signal, or The first capacitor, discharged by the current generated by the power supply, The first comparator circuit outputs a voltage corresponding to the amount of charge stored in the first capacitor during the interval between when the charge drops to the first standard voltage and then rises to the second standard voltage higher than the first standard voltage. The first signal, at the same time as one of the following, also includes: The second capacitor, charged by the current generated by the power supply, The second comparator circuit outputs a voltage corresponding to the amount of charge stored in the second capacitor during the interval between the charge rises to the third standard voltage and then falls to the fourth standard voltage lower than the third standard voltage. second signal, or The second capacitor, discharged by the current generated by the power supply, The second comparator circuit outputs a voltage corresponding to the amount of charge stored in the second capacitor during the interval between when the charge drops to the third standard voltage and then rises to the third standard voltage higher than the third standard voltage. The second signal, at the same time as one, also includes: an inversion flip-flop circuit that inverts the output whenever the above-mentioned first signal or second signal is output, The charging and discharging control circuit selectively switches between charging the first capacitor and discharging the second capacitor, and discharging the first capacitor while charging the second capacitor. 5. According to any one of the oscillating circuits described in claim 1, 2 or 4, it is characterized in that: The above-mentioned first and second capacitors are charged or discharged by the current generated by the same power source. 6. The oscillation circuit according to claim 1, characterized in that: The above-mentioned first and second charge and discharge control circuits are configured to connect respective one ends of the above-mentioned first and second capacitors to a power supply during charging, and connect respective one ends of the above-mentioned first and second capacitors to a power supply during discharging. Separate the ends. 7. The oscillating circuit according to claim 2 or 4, characterized in that: The charge and discharge control circuit connects one end of the first and second capacitors to a power source for charging, and separates the two ends of the first and second capacitors for discharge.

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