CN101017850A - VDMOS and IGBT power unit using the PSG doping technology and its making process - Google Patents
VDMOS and IGBT power unit using the PSG doping technology and its making process Download PDFInfo
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- CN101017850A CN101017850A CN 200710037559 CN200710037559A CN101017850A CN 101017850 A CN101017850 A CN 101017850A CN 200710037559 CN200710037559 CN 200710037559 CN 200710037559 A CN200710037559 A CN 200710037559A CN 101017850 A CN101017850 A CN 101017850A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000005516 engineering process Methods 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000001259 photo etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 85
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to VDMOS and IGBT power device with PSG doping technology, which comprises: a metal base, an N+ substrate (P+ for IGBT device), an N- extension layer, a P- area, a P+ area, an N+ area with doping source as PSG layer, a thermal-oxidized SiO2 grid, a multicrystal Si grid, a PSG isolation layer for source and grid, and a metal surface layer. This invention decreases photoetching and other procedures to reduce cost and improve work reliability, and has well practicability and economical efficiency.
Description
Technical field
The present invention relates to the production process of semiconductor device technology in the microelectronics technology, particularly a kind of VDMOS, IGBT power device and manufacturing process thereof that adopts the PSG doping techniques.
Background technology
Existing VDMOS, IGBT power device are mainly by metal back layer, N+ substrate layer, N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO
2Grid oxide layer, polycrystalline silicon grid layer, SiO
2Illuvium, phosphorosilicate glass PSG illuvium and metal surface are formed.Fill the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polycrystalline silicon grid layer is filled the post of grid, phosphorosilicate glass PSG layer and LPCVD SiO
2The source gate spacer is filled the post of in layer combination, the source region by the P-district that is positioned at deep layer, in the middle of being positioned at the P+ district and the annular N+ district that is positioned at periphery, P+ district constitute.
Its manufacturing process flow is mainly as follows:
(1) on the base material that constitutes by N+ substrate layer (being the P+ substrate layer in the IGBT power device) and N-epitaxial loayer, generates one deck grid oxide layer earlier and with method growth one deck polycrystalline silicon grid layer of LPCVD deposit in the mode of thermal oxidation;
(2) remove the SiO that covers on the scope of predetermined origin area with photoetching, dry etching method
2Grid oxide layer and polycrystalline silicon grid layer, and after injecting boron on the N-layer that is concavity, exposure down thus, do annealing, knot processing, form darker, the wide P-district of coverage in the source region;
(3) the photoetching predetermined set is the annular region scope in N+ district in described P-district, and does annealing, knot processing after injecting phosphorus, forms the annular N+ district in source region;
(4) photoetching is positioned at all the other middle predetermined P+ area scopes of described annular N+ district, and does annealing, knot processing after injecting boron, forms the P+ district in the middle of being positioned at;
(5) at front, SiO by remaining polysilicon grid layer
2The side of grid oxide layer and polycrystalline silicon grid layer links to each other with the following concavity plane that comprises N+ district, P+ district surface on the integral surface that forms with the method elder generation deposit of LPCVD or PECVD one deck SiO that grows
2, after whole again deposit growth one deck PSG or BPSG, and then to the SiO on the middle position
2Do photoetching with PSG or bpsg layer and burn into forms by SiO
2The source, the gate spacer that constitute with PSG layer or bpsg layer;
(6) at last just, evaporation growing metal layer on the back side, make VDMOS or IGBT power device.
In the flow process of in this way making VDMOS, IGBT power device, adopted repeatedly photoetching and burn into to remove the property processing, operation is more loaded down with trivial details, particularly is being isolated into purpose, growth SiO with what realize grid and source
2In the process of layer and PSG or bpsg layer, except that need are carried out a photoetching and corrosion process, the version that also has this separator, make the N+ district area of the VDMOS that in this way makes, IGBT power device bigger, make the emitter region area of parasitic NPN pipe also bigger, thereby cause the functional reliability of VDMOS, IGBT power device relatively poor.So, the VDMOS, the IGBT power device ubiquity that utilize prior art to produce cause product cost high because of the complexity of production process, because of structural volume and the functional reliability of owing rationally to cause influencing product, thereby all owing desirable aspect economy and the practicality.
Summary of the invention
The objective of the invention is to provide a kind of area in N+ district in the parasitic components of being convenient to dwindle among VDMOS, the IGBT, the novelty that the emitter region area of parasitic NPN pipe is also dwindled thereupon, helps improving functional reliability and reduce cost of goods manufactured adopts VDMOS, IGBT power device and the manufacturing process thereof of PSG doping techniques.
The VDMOS of employing PSG doping techniques of the present invention, IGBT power device are mainly by metal back layer, N+ substrate layer (being the P+ substrate layer in the IGBT power device), N-epitaxial loayer, P-district, P+ district, N+ district, thermal oxidation SiO
2Grid oxide layer, polycrystalline silicon grid layer, source gate spacer and metal surface are formed.Fill the post of by metal surface that source electrode, metal back layer are filled the post of drain electrode, polycrystalline silicon grid layer is filled the post of grid, the source region by the P-district that is positioned at deep layer, be positioned at the P+ district on the middle part, top layer and be positioned at peripheral annular N+ district, P+ district and constitute.It is characterized in that: phosphorosilicate glass PSG layer is filled the post of the source gate spacer with the form of individual layer; The doped source of phosphorosilicate glass PSG floor when generating N+ district in the source region, after predetermined N+ district annular region is carried out photoetching, dry etching, again by PSG floor height temperature is annealed, the knot processing, make phosphorus wherein in silicon, diffuse to form the N+ district.
The present invention adopts the VDMOS, IGBT power device of PSG doping techniques and technological process that manufacturing process is made the VDMOS power device thereof as follows:
(1) elder generation's mode with thermal oxidation on the base material that is made of N+ substrate layer and N-epitaxial loayer generates SiO
2Grid oxide layer, again with the method growing polycrystalline silicon grid layer of deposit;
(2) remove the SiO that is positioned on the predetermined scope zone, source region with photoetching, dry etching method
2Grid oxide layer and polycrystalline silicon grid layer, and do annealing, knot are handled behind injection boron on the N-layer that is concavity exposure down thus, darker, wide P-district in the formation source region;
(3) concavity N-laminar surface photoetching under being that is exposed is predefined for the central area in P+ district, and does annealing, knot processing after injecting boron, form P+ district more shallow in the middle of being positioned at, book;
(4) with LPCVD method deposit growth PSG floor on the integral surface that constitutes that links to each other by the front of remaining polysilicon grid floor and side, P-district and P+ district, and to be created on P-district and P+ district surperficial on the PSG floor do the removal processing of photoetching, dry etching;
(5) deposit is grown on the front of remaining polysilicon grid layer and the side PSG layer and handles through high annealing, knot, phosphorus contained among the PSG is spread in silicon, form the N+ district of the more shallow book of annular as the doped source in source region;
(6) align, back side evaporation generates metal back layer and metal surface, makes the VDMOS power device.
The above is the manufacturing process of VDMOS power device of the present invention, and for the manufacturing process flow of IGBT power device with it roughly the same, its difference is that the N+ substrate layer on the base material is replaced by the P+ substrate layer.
In addition, according to technology of the present invention, the thickness of described polysilicon gate is generally 4000 dusts to 6000 dusts, and the thickness of the PSG of described LPCVD is generally more than 5000 dusts.
Adopt VDMOS, IGBT power device and the manufacturing process thereof of PSG doping techniques based on the present invention of above-mentioned design, owing to utilize the phosphorosilicate glass PSG layer that deposit generates when in VDMOS, IGBT power device manufacture process the source gate spacer being set to fill the post of, replace in the prior art by SiO with the single layer structure form
2The version of layer and PSG layer combination, and utilize this phosphorosilicate glass PSG floor as the doped source during the N+ district in the generation source region, thus saved SiO
2The layer generation and to SiO
2Layer carries out the operation of photoetching treatment, not only helped reducing production costs, simultaneously but also the N+ district area in the device parasitic among VDMOS, the IGBT is reduced, help increasing substantially the functional reliability of VDMOS, IGBT power device, thereby have tangible technical advance, remarkable economical and extremely strong practicality.
Description of drawings
Fig. 1 is the internal structure schematic diagram of inventive embodiments product;
The internal structure schematic diagram of Fig. 2 prior art products related to the present invention;
Fig. 3 is the process flow diagram of the embodiment of the invention;
Fig. 4 is the manufacturing process flow diagram of the embodiment of the invention.
Among the figure:
1. metal back layer 2.N+ substrate layer 3.N-epitaxial loayer 4.P-district
5.P+ district 6.N+ district 7.SiO
2 Grid oxide layer 8. polycrystalline silicon grid layers
9. source gate spacer 10. metal surface 11.PSG layer 12.SiO
2Layer
13. 14. positive 15. sides, source region scope zone
Embodiment
Below in conjunction with accompanying drawing and exemplary embodiments the present invention is further described.
In Fig. 1 and Fig. 2, the VDMOS of employing PSG doping techniques of the present invention, IGBT power device are mainly by metal back layer 1, N+ substrate layer 2 (being the P+ substrate in the IGBT power device), N-epitaxial loayer 3, P-district 4, P+ district 5, N+ district 6, thermal oxidation SiO
2Grid oxide layer 7, polycrystalline silicon grid layer 8, source gate spacer 9 and metal surface 10 are formed.Filled the post of by metal surface 10 that source electrode, metal back layer 1 are filled the post of drain electrode, polycrystalline silicon grid layer 8 is filled the post of, the source region is made of the P-district 4 that is positioned at deep layer, the annular N+ district 6 that is positioned at the P+ district 5 in the middle of the top layer and is positioned at 5 peripheries, P+ district.Wherein: source gate spacer 9 is by phosphorosilicate glass PSG layer 11 and SiO in the prior art
2Layer 12 combines, and source gate spacer 9 is filled the post of with the form of individual layer by phosphorosilicate glass PSG layer 11 in the present invention; In addition, in the present invention, phosphorosilicate glass PSG floor 11 go back double as be when generating N+ district in the source region doped source, by phosphorosilicate glass PSG floor 11 is done annealing, knot is handled, and makes in the silicon of wherein contained phosphorus in predetermined N+ district 6 annular regions to spread, and forms the N+ district 6 of annular more shallow book.
In Fig. 3 and Fig. 4, the present invention adopts the technological process of PSG doping techniques manufacturing VDMOS power device as follows:
(1) elder generation's mode with thermal oxidation on the base material that is made of N+ substrate layer 2 and N-epitaxial loayer 3 generates SiO
2 Grid oxide layer 7, again with the method growing polycrystalline silicon grid layer 8 of deposit;
(2) remove the SiO that is scheduled on the scope zone, source region 13 with photoetching, dry etching method
2 Grid oxide layer 7 and polycrystalline silicon grid layer 8, and do annealing, knot are handled behind injection boron on the N-layer that is concavity exposure down thus, darker, thick P-district 4 in the formation source region;
(3) photoetching is done in the central area in predetermined P+ district 5 on the concavity N-floor under being that is exposed, and do annealing, knot are handled behind the injection boron, form the P+ district 5 that is positioned at the middle more shallow book in source region;
(4), and P-district 4 and P+ district 5 lip-deep PSG floor 11 are done the removal processing of photoetching, dry etching with LPCVD method deposit growth PSG floor 11 on the integral surface that constitutes that links to each other by the front 14 of remaining polysilicon grid floor 8 and side 15, P-district 4 and P+ district 5;
(5) deposit is grown in the front 14 of remaining polysilicon grid floor 8 and the PSG floor 11 on the side 15 doped source when generating the N+ district in the source region, by phosphorosilicate glass PSG layer 11 being done annealing, knot processing, wherein contained phosphorus is spread in silicon, form the N+ district 6 of the more shallow book of annular;
(6) align, back side evaporation generates metal back layer 1 and metal surface 10, makes the VDMOS power device.
More than be the manufacturing process of VDMOS power device among the present invention, for the manufacturing process flow of IGBT power device with it roughly the same, its difference is that the N+ substrate on the base material is replaced by the P+ substrate.
In addition, described PSG layer 11 effect that is arranged between metal surface 10 and the polycrystalline silicon grid layer 8, fills the post of source gate spacer 9; The thickness of described polycrystalline silicon grid layer 8 generally is controlled at 4000 dusts to 6000 dusts, and the thickness of the PSG layer 11 of LPCVD is generally more than 5000 dusts; The N+ district 6 in described source region be by the PSG floor 11 of LPCVD by to the regional photoetching in predetermined N+ district, dry etching after heating anneal diffuses to form the phosphorus in the PSG floor 11 in P-district 4.
Claims (2)
1. VDMOS, IGBT power device that adopts the PSG doping techniques is by metal back layer (1), N+ substrate layer (2) (being the P+ substrate layer in the IGBT power device), N-epitaxial loayer (3), P-district (4), P+ district (5), N+ district (6), thermal oxidation SiO
2Grid oxide layer (7), polycrystalline silicon grid layer (8), source gate spacer (9) and metal surface (10) are formed, and it is characterized in that: source gate spacer (9) is filled the post of by individual layer phosphorosilicate glass PSG layer (11).
2. VDMOS, IGBT power device manufacturing process that adopts the PSG doping techniques, the technological process that it is characterized in that making VDMOS or IGBT power device is as follows:
(1) elder generation's mode with thermal oxidation on the base material that is made of N+ substrate layer (being the P+ substrate layer in the IGBT power device) (2) and N-epitaxial loayer (3) generates SiO
2Grid oxide layer (7), again with the method growing polycrystalline silicon grid layers (8) of deposit;
(2) remove the SiO that is positioned on the predetermined scope zone, source region (13) with photoetching, dry etching method
2Grid oxide layer (7) and polycrystalline silicon grid layer (8), and do annealing, knot are handled behind injection boron on the N-layer that is concavity exposure down thus, the P-district (4) in formation source region;
(3) photoetching is done in the central area of being scheduled to P+ district (5) on the concavity N-floor under being that is exposed, and do annealing, knot processing after injecting boron, formation is positioned at the P+ district (5) in the middle of the source region;
(4) do the removal processing of photoetching, dry etching with the method for LPCVD deposit growth PSG floor (11) on the integral surface that constitutes that links to each other with P+ district (5) by the front (14) of remaining polysilicon grid floor (8) and side (15) thereof, P-district (4), and to being positioned at P-district (4) and P+ district (5) lip-deep PSG floor (11);
(5) deposit is grown in the front (14) of remaining polysilicon grid floor (8) and the PSG floor (11) on side (15) doped source when generating N+ district (6) in the source region, phosphorosilicate glass PSG layer (11) is done annealing, knot processing, wherein contained phosphorus is spread in silicon, form annular N+ district (6);
(6) align, back side evaporation generates metal back layer (1) and metal surface (10), makes VDMOS, (IGBT) power device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100375591A CN100477270C (en) | 2007-02-14 | 2007-02-14 | VDMOS and IGBT power unit using the PSG doping technology and making process thereof |
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|---|---|---|---|
| CNB2007100375591A CN100477270C (en) | 2007-02-14 | 2007-02-14 | VDMOS and IGBT power unit using the PSG doping technology and making process thereof |
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| CN100477270C CN100477270C (en) | 2009-04-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151268A (en) * | 2013-03-21 | 2013-06-12 | 矽力杰半导体技术(杭州)有限公司 | Vertical double-diffused field-effect tube and manufacturing process thereof |
| CN103578981B (en) * | 2012-07-19 | 2016-09-07 | 无锡华润上华半导体有限公司 | Field terminates the preparation method of insulated gate bipolar transistor |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482681B1 (en) * | 2000-05-05 | 2002-11-19 | International Rectifier Corporation | Hydrogen implant for buffer zone of punch-through non epi IGBT |
| EP1531497A1 (en) * | 2003-11-17 | 2005-05-18 | ABB Technology AG | IGBT cathode design with improved safe operating area capability |
| CN100421256C (en) * | 2006-05-24 | 2008-09-24 | 杭州电子科技大学 | SOI LIGBT device unit of integrated ESD diode |
| CN201017889Y (en) * | 2007-02-14 | 2008-02-06 | 上海富华微电子有限公司 | VDMOS, IGBT power device using PSG doping technique |
-
2007
- 2007-02-14 CN CNB2007100375591A patent/CN100477270C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578981B (en) * | 2012-07-19 | 2016-09-07 | 无锡华润上华半导体有限公司 | Field terminates the preparation method of insulated gate bipolar transistor |
| CN103151268A (en) * | 2013-03-21 | 2013-06-12 | 矽力杰半导体技术(杭州)有限公司 | Vertical double-diffused field-effect tube and manufacturing process thereof |
| US9245977B2 (en) | 2013-03-21 | 2016-01-26 | Silergy Semiconductor Technology (Hangzhou) Ltd | Vertical double-diffusion MOS and manufacturing technique for the same |
| CN103151268B (en) * | 2013-03-21 | 2016-02-03 | 矽力杰半导体技术(杭州)有限公司 | A kind of vertical bilateral diffusion field-effect pipe and manufacturing process thereof |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
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| CN100477270C (en) | 2009-04-08 |
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Assignee: JILIN MAGIC SEMICONDUCTOR CO., LTD. Assignor: JILIN SINO-MICROELECTRONICS Co.,Ltd. Contract record no.: 2011220000035 Denomination of invention: VDMOS and IGBT power unit using the PSG doping technology and its making process Granted publication date: 20090408 License type: Exclusive License Open date: 20070815 Record date: 20110824 |