CN101017837A - Solid image pickup device - Google Patents
Solid image pickup device Download PDFInfo
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- CN101017837A CN101017837A CNA2006100644818A CN200610064481A CN101017837A CN 101017837 A CN101017837 A CN 101017837A CN A2006100644818 A CNA2006100644818 A CN A2006100644818A CN 200610064481 A CN200610064481 A CN 200610064481A CN 101017837 A CN101017837 A CN 101017837A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/809—Constructional details of image sensors of hybrid image sensors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/803—Pixels having integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/807—Pixel isolation structures
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Abstract
一种固体摄像装置，包括：半导体衬底，上述半导体衬底由含有P型杂质的衬底本体和在上述衬底本体上设置的第一N型半导体层构成；含有多个光电转换部的摄像区域，上述多个光电转换部由在上述第一N型半导体层的表面部上彼此独立设置的第二N型半导体层构成；以及第一周边电路区域，上述第一周边电路区域由在上述第一N型半导体层上形成的第一P型半导体层构成。此固体摄像装置还包括第二周边电路区域，上述第二周边电路区域由在上述第一N型半导体层上以连接上述衬底本体的方式形成的第二P型半导体层构成。
A solid-state imaging device, comprising: a semiconductor substrate, the semiconductor substrate is composed of a substrate body containing P-type impurities and a first N-type semiconductor layer disposed on the substrate body; an imaging device including a plurality of photoelectric conversion parts region, wherein the plurality of photoelectric conversion portions are formed of second N-type semiconductor layers independently provided on the surface portion of the first N-type semiconductor layer; and a first peripheral circuit region, wherein the first peripheral circuit region is composed of A first P-type semiconductor layer is formed on an N-type semiconductor layer. The solid-state imaging device further includes a second peripheral circuit region, and the second peripheral circuit region is composed of a second P-type semiconductor layer formed on the first N-type semiconductor layer in a manner connected to the substrate body.
Description
The cross reference of related application
The application based on and require the priority of the Japanese patent application No.2005-327601 that submits on November 11st, 2005, quote its full content as a reference at this.
Technical field
The present invention relates to a kind of amplifying-type solid-state imaging device.In more detail, relate to a kind of employing N/P
+The CMOS of substrate (complementary metal oxide semiconductors (CMOS), Complementary Metal OxideSemiconductor) type solid camera head, so-called cmos image sensor.
Background technology
Since past, as solid camera head, the solid camera head of well-known a kind of charge coupled cell type (below, be called CCD (charge coupled device, Charge Coupled Device) imageing sensor).Usually adopt N type substrate to form ccd image sensor.In addition, ccd image sensor is for its driving, 3 power supplys that just need magnitude of voltage to differ from one another.For example, the driven CCD imageing sensor just needs 3 power supplys of 5V (volt), 8V and 15V.Under the situation of this ccd image sensor, its power consumption is about 500mW (milliwatt).
In addition, recently,, a kind of employing P/P has been proposed as solid camera head
+The cmos image sensor of substrate, and becoming commercialized.This cmos image sensor has the operation principle different with ccd image sensor (feature).Particularly, cmos image sensor has the feature of single power supply, low voltage drive and low-power consumption etc.For example, drive cmos image sensor, have 1 3V power supply to get final product.The power consumption of this cmos image sensor is about 50mW.
In recent years, cmos image sensor is the same with the situation of ccd image sensor, is clearly constantly advancing many pixelations (high pixelation).Do not increase pixel (imaging apparatus) quantity if do not change the size of transducer, will make the pixel miniaturization of each this moment certainly.So,, the light-receiving area of the photodiode in each pixel is dwindled along with the miniaturization of pixel.Thus, will reduce the photosensitivity of photodiode.
Under the situation of ccd image sensor,, just can improve the photosensitivity of photodiode by the depletion layer of expansion photodiode.But as mentioned above, the structure of the cmos image sensor voltage lower than ccd image sensor of serving as reasons drives.Thus, compare, just be difficult to expand the depletion layer of photodiode with ccd image sensor.That is, under the situation of cmos image sensor, be difficult to the sensitivity decrease that depletion layer by the expansion photodiode improves the photosensitivity of photodiode and revises the photodiode that precise and tiny refinement causes thus.Therefore, for cmos image sensor, developing a kind of technology that improves the photosensitivity of photodiode with the ccd image sensor diverse ways of using becomes from now on important technology problem (for example, the reference towards further high pixelation
The spy opens the 2001-160620 communique and the spy opens The 2001-223351 communique).In addition, wish to develop a kind of photosensitivity that not only can improve photodiode, but also can suppress the technology of the image quality deterioration of bloom and colour mixture etc.
As a solution of this problem, for example, discussing a kind of employing N/P
+The method of substrate.Adopt N/P
+Substrate be the electronic high-effective that will produce by opto-electronic conversion accumulate in the photodiode.That is N/P,
+Substrate and P/P
+The situation of substrate is identical, and structure is for to become the P of substrate bulk
+On the type substrate, stacked epitaxially grown n type semiconductor layer (N type epitaxial loayer).At this N/P
+In the N type epitaxial loayer of substrate, utilize accelerator, ion injects the N type impurity of P (phosphorus) for example etc., forms photodiode (n type semiconductor layer).So the photodiode that forms with than P/P
+The expansion that the situation of substrate is compared depletion layer becomes and is more prone to.Therefore, do not improve the driving voltage of cmos image sensor, just can improve the photosensitivity of photodiode.Meanwhile, owing to can utilize the shortening in the life-span of charge carrier, so just can suppress the generation of the image quality deterioration of bloom and colour mixture etc.Therefore, by adopting N/P
+Substrate is made cmos image sensor, just can solve above-mentioned problem.
, with employing P/P
+Substrate is made the situation difference of cmos image sensor, is adopting N/P
+Substrate is made under the situation of cmos image sensor, and N/P takes place
+The several peculiar problem that substrate causes.
The firstth, the isolating problem between relevant photodiode.At P/P
+In the substrate, on P type epitaxial loayer, form a plurality of photodiodes (n type semiconductor layer).Thus, just can make between the photodiode element separation reliably by p type semiconductor layer as P type epitaxial loayer.That is, photodiode just can not be electrically connected each other.With respect to this, at N/P
+In the substrate, on N type epitaxial loayer, form a plurality of photodiodes (n type semiconductor layer).Thus, photodiode does not have element separation each other, will produce the problem that photodiode is electrically connected to each other.
The second, be problem about leakage current.At P/P
+Under the situation of substrate,, just can on the section of each chip, present p type semiconductor layer by cut into the scribing operation of a plurality of independent semiconductor chips from a slice Si (silicon) wafer.With respect to this, at N/P
+Under the situation of substrate, utilize the scribing operation, just can on the section of each chip, present as P
+The PN junction at the interface of type substrate bulk and N type epitaxial loayer.When presenting PN junction on the chip section, the surface of its section just becomes the reason that produces leakage current, perhaps will become the current path of leakage current.That is, probably cause leakage current to increase.
The 3rd, be the problem of the relevant circuit that is provided with at the periphery of camera watch region.One of feature of cmos image sensor can be enumerated and various signal processing circuits (peripheral circuit) can be carried out singualtion with imaging apparatus.That is, different with ccd image sensor, because the manufacturing process that the manufacturing process of cmos image sensor approaches logical circuit, so just can on same production line, make.In addition, as mentioned above, owing to cmos image sensor can drive by the single power supply low-voltage, so, just can use the power supply of logical circuit as its driving power.Like this, can carry out in the cmos image sensor of singualtion, use P/P
+Under the situation of substrate, pass through P
+The type substrate bulk just can make P-well (P trap) ground connection that forms peripheral circuit.Thus, the pulse signal that just can make by peripheral circuit, particularly logical circuit and analog circuit generated becomes the good signal of waveform stabilization.That is, using P/P
+Under the situation of substrate, just can make many pixelations of cmos image sensor or high speed.
With respect to this, using N/P
+Under the situation of substrate, just utilize N type epitaxial loayer to isolate P-well and the P that forms peripheral circuit
+The type substrate bulk.Therefore, just can not pass through P
+The type substrate bulk makes P-well ground connection.That is, owing to only can get earthing potential (Vss), so the zero potential of P-well that can not ground connection is just unstable from P-well.Therefore, at peripheral circuit particularly in the analog circuit, the rising edge of pulse/trailing edge produces and postpones etc., will produce thus and can only produce the unsettled non-square pulse of waveform, perhaps the problem of the timing slip that generates of pulse.These are that camera head and the per 1 second shooting coma aberration number of 2M (million) more than the bit is in the high speed video camera more than 30 frames at for example pixel quantity, can become the bad main cause of pixel characteristic that presents vertical stripe and horizontal stripe etc.
Summary of the invention
According to a first aspect of the invention, a kind of solid camera head is provided, this solid camera head comprises (corresponding to claim 1): Semiconductor substrate, and above-mentioned Semiconductor substrate is made of the substrate bulk that contains p type impurity and first n type semiconductor layer that is provided with on above-mentioned substrate bulk; The camera watch region that contains a plurality of photoelectric conversion parts, above-mentioned a plurality of photoelectric conversion parts are made of second n type semiconductor layer that is provided with independently of one another on the surface element of above-mentioned first n type semiconductor layer; First peripheral circuit area, above-mentioned first peripheral circuit area is made of first p type semiconductor layer that forms on above-mentioned first n type semiconductor layer; And second peripheral circuit area, above-mentioned second peripheral circuit area is made of second p type semiconductor layer that forms in the mode that connects above-mentioned substrate bulk on above-mentioned first n type semiconductor layer.
Description of drawings
Fig. 1 is the employing N/P of expression first embodiment of the invention
+The structure chart of an example of the cmos image sensor of substrate.
Fig. 2 is the profile of the structure example of the cmos image sensor shown in the presentation graphs 1.
Fig. 3 is the characteristic accompanying drawing of expression along the part of the III-III line of the cmos image sensor shown in Fig. 2.
Fig. 4 is the plane graph of a part of the camera watch region of the cmos image sensor shown in the presentation graphs 2.
Fig. 5 is the circuit diagram of the primary structure of the cmos image sensor shown in the Fig. 2 that schematically illustrates.
Fig. 6 is the characteristic accompanying drawing of expression along the part of the VI-VI line of the cmos image sensor shown in Fig. 2.
Fig. 7 is the employing N/P that represents second embodiment of the invention
+The profile of the structure example of the cmos image sensor of substrate.
Fig. 8 is the characteristic accompanying drawing of expression along the part of the VIII-VIII line of the cmos image sensor shown in Fig. 7.
Preferred implementation
Various embodiments of the present invention are described with reference to the accompanying drawings.Should be noted that accompanying drawing is schematically, and the dimension scale that goes out shown here is different from actual size.The size of each accompanying drawing has nothing in common with each other, and dimension scale also has nothing in common with each other.Each following embodiment provides a kind of device and a kind of method, be used to implement technical conceive of the present invention, and technical conceive does not limit the structure of material of the present invention, shape, structure or element especially.Do not breaking away within the scope of the presently claimed invention, can carry out various changes and modification technical conceive.
First execution mode
Fig. 1 shows the employing N/P of first embodiment of the invention
+The basic structure of the cmos image sensor of substrate (imageing sensor of scale-up version).Have again, in the present embodiment, illustrate the cmos image sensor of singualtion.
As shown in Figure 1, in the cmos image sensor of singualtion, be provided with camera watch region (or pixel portions) 11.In addition, in this cmos image sensor, be provided with peripheral circuit (or peripheral treatment circuit) 12.As peripheral circuit 12, for example, be equipped with analog/digital converter (ADC) 12a, digital/analog converter (DAC) 12b, timing control circuit 12c, timing generator (TG/SG) 12d, DSP (digital signal processor, Digital Signal Processor) 12e, coding circuit 12f, AGC (automatic gain control, Automatic Gain Control) circuit 12g, CLP (clamp, Clamp) circuit 12h and output circuit 12i.Dispose above-mentioned peripheral circuit 12, so that surround the periphery of above-mentioned camera watch region 11 respectively.In addition, among above-mentioned peripheral circuit 12, only ADC12a is the peripheral circuit of simulation class, and other is the peripheral circuit of logic class.On the Semiconductor substrate that forms by 2 layers of structure (described later), form these camera watch regions 11 and peripheral circuit 12.
Fig. 2 shows the cross-section structure of the cmos image sensor shown in Fig. 1.In the present embodiment, for example show for example along the section of the II-II line of Fig. 1.Under the situation of this aforesaid way, Semiconductor substrate 21 is 2 layers of structure.That is, the part (underclad portion) of these Semiconductor substrate 21 its downsides is for containing the substrate bulk 22 of p type impurity.In addition, the part (top section) of Semiconductor substrate 21 its upsides is for containing first n type semiconductor layer 23 of N type impurity.
For example, in the substrate bulk 22 that forms by Si, contain boron (B) as p type impurity.Therefore, substrate bulk 22 also can be called the P type semiconductor substrate.Boron concentration in the substrate bulk 22 (p type impurity concentration) is set at for example about 2 * 10
18Cm
-3(2E18cm
-3).
On the other hand, form first n type semiconductor layer 23 by on the surface of substrate bulk 22, carrying out epitaxial growth.In the present embodiment, the thickness of representing with solid arrow mark T1 among Fig. 2 was by epitaxial growth method deposit first n type semiconductor layer 23 on the surface of substrate bulk 22 before becoming about 5.0 μ m.Contain phosphorus in first n type semiconductor layer 23 as epitaxially grown layer as N type impurity.Therefore, first n type semiconductor layer is yet with to be called N type epitaxial loayer.Phosphorus concentration in first n type semiconductor layer 23 (N type impurity concentration) for example can be set at about 2 * 10
15Cm
-3
Like this, Semiconductor substrate 21 just becomes 2 layers of structure of stacked N type epitaxial loayer 23 on P type semiconductor substrate 22.In the following description, claim this Semiconductor substrate 21 to be N/P
+Substrate.
Usually, making this N/P
+During substrate 21, the speed of growth of N type epitaxial loayer 23 is set in and is about 1 μ m/ branch, prolongs N type epitaxial loayer 23 outside on P type semiconductor substrate 22.Under the situation of this setting (membrance casting condition), from as N/P
+The deep-seated of type substrate 21 is put P type semiconductor substrate 22 side direction of (deep layer portion) as N/P
+The N type epitaxial loayer 23 of the shallow position (skin section) of type substrate 21 is as the almost not diffusion (moving) of boron of p type impurity.Therefore, at the interface of P type semiconductor substrate 22 and N type epitaxial loayer 23, as described later, the curved profile of boron concentration becomes precipitous.In addition, at the N/P of the state of original making
+In the type substrate 21, its PN junction (24) is equivalent to the interface of P type substrate 22 and N type epitaxial loayer 23.That is, stocking the N/P of state
+In the type substrate 21, as mentioned above, PN junction (24) is positioned at apart from N/P
+The degree of depth place of surperficial about 5.0 μ m of type substrate 21.
When reality is made cmos image sensor, in advance to N/P
+Type substrate 21 is implemented heat treated.Thus, make boron diffusion in the P type semiconductor 22 in N type epitaxial loayer 23.For example, under about 1150 ℃ by carrying out this heat treated in 1.5 hours.The result of this heat treated is oozed out the boron as p type impurity in N type epitaxial loayer 23 from P type semiconductor substrate 22, on P type semiconductor substrate 22, form the P type trap (P-well) 25 as the 3rd p type semiconductor layer.N/P after implementing heat treated
+In the type substrate 21, this PN junction 24 is equivalent to the interface of P type trap 25 and N type epitaxial loayer 23.In addition, solid arrow mark T2 thickness represented, that form the N type epitaxial loayer 23 behind the P type trap 25 is about 2.5～3.5 μ m among Fig. 2.That is the N/P after implementing heat treated,
+In the type substrate 21, PN junction 24 is positioned at apart from N/P
+The degree of depth place of surperficial about 2.5～3.5 μ m of type substrate 21.And near the boron concentration the PN junction 24 of P type trap 25 becomes about 2 * 10
15Cm
-3
Like this, utilize near the boron concentration its PN junction 24, the concentration of the p type impurity of the P type trap 25 that will form on P type semiconductor substrate 22 is set at about 2 * 10
15Cm
-3With respect to this, as mentioned above, will be set at about 2 * 10 as the boron concentration of the p type impurity concentration of P type semiconductor substrate 22
18Cm
-3That is N/P,
+In the type substrate 21, the degree of depth is set at greater than the concentration of the p type impurity of the deep layer portion of 5.0 μ m approximately apart from its surface is higher than as the concentration from 2.5～3.5 μ m to the p type impurity of the shallow position of 5.0 μ m approximately of the degree of depth directly over it.
Usually, in the high zone of the concentration of p type impurity, short as the life-span of the electronics of charge carrier, electronics combines with the hole rapidly again.Therefore, even N/P
+The electronics that generates in the type substrate 21 is from N/P
+The diffusion into the surface of type substrate 21 to than about 5.0 μ m more the below deep layer portion, this electronics also combines with the hole rapidly again.In addition, at distance N/P
+Even the electronics that the shallow position of surperficial about 5.0 μ m of type substrate 21 generates will be diffused into N/P
+The deep layer portion of type substrate 21 also can be to N/P near the interface of the concentration of p type impurity P type jumpy trap 25 and N type epitaxial loayer 23
+The face side of type substrate 21 is returned transition.Particularly, even at distance N/P
+The electronics that the shallow position of surperficial about 5.0 μ m of type substrate 21 generates is to N/P
+The deep layer portion diffusion of type substrate 21 also can be because of near the potential barrier wall that exists PN junction 24 to N/P
+The face side of type substrate 21 is returned.
At this, at the N/P that uses this structure
+In the cmos image sensor that type substrate 21 is made, in each chip, be provided with: camera watch region 11, peripheral circuit simulated domain (the 2nd peripheral circuit area) 13, peripheral circuit logic region (the 1st peripheral circuit area) 14 and chip cut-out portion 15.And, in peripheral circuit 13, form respectively P type trap (second p type semiconductor layer) 13 ', in peripheral circuit logic region 14, form P type trap (first p type semiconductor layer) 14 '.In the case, P type trap 13 ', 14 ' all have from N/P
+The skin section of type substrate 21 (surface element of N type epitaxial loayer 23) arrives the degree of depth of P type semiconductor substrate 22 (or P type traps 25), and is formed continuously.Chip cut-out portion 15 is called scribe line and partly divides.
Then, near 27 ones on the surface of the N of corresponding camera watch region 11 type epitaxial loayer 23, read transistorized grid 26 and as the drain electrode of test section 27 etc. by being processed to form of conventional (having now).Meanwhile, near the surface element of N type epitaxial loayer 23, though diagram not has been processed to form capacitor and grid wiring etc. by routine.
In addition, in the surface element of the N of corresponding camera watch region 11 type epitaxial loayer 23, at its a plurality of positions, the photodiode (Photo Diode) that is provided as photoelectric conversion part independently of one another by the processing of routine (PD) 28.Particularly, on the surface of N type epitaxial loayer 23, pattern forms not shown resist film so that it becomes the figure of regulation.After this, inject phosphorus to the surface element ion of N type epitaxial loayer 23 as N type impurity.At this moment, as the degree of depth of the peak value of the phosphorus concentration (P concentration) of the concentration of N type impurity mainly the size of the energy when injecting the P ion decide.In the present embodiment,, utilize the injection energy of about 300KeV (kilo electron volt) as the injection condition of P ion, with the dosage setting of P ion 1.2 * 10
12Cm
-2Thus, form the photodiode 28 that constitutes by second n type semiconductor layer at a plurality of positions of the surface element of N type epitaxial loayer 23.That is, the peak value with phosphorus concentration is positioned at apart from the such phosphorus concentration curved profile of the degree of depth of surperficial about 0.4 μ m of N type epitaxial loayer 23, at the surface element of N type epitaxial loayer 23 a plurality of photodiodes 28 is set.
In addition, in the surface element of the N of corresponding camera watch region 11 type epitaxial loayer 23, form as a plurality of STI element separation zone, that for example constitute (shallow trench isolation from, hallow Trench Isolation) 29 by oxide-film.Make these STI29 be about 0.3～0.35 μ m apart from the degree of depth on the surface of N type epitaxial loayer 23.
And, in the N of corresponding camera watch region 11 type epitaxial loayer 23, with independent the 4th p type semiconductor layer 30 that constitutes by multilayer around the figure setting of photodiode 28.Near surface from N type epitaxial loayer 23 is provided with the 4th p type semiconductor layer 30 to P type trap 25 sides respectively.Particularly, the downside at each STI29 and test section 27 is provided with the 4th p type semiconductor layer 30 respectively.By more than 23 ion of N type epitaxial loayer being injected for example boron, form the 4th p type semiconductor layer 30 respectively as p type impurity.In the 4th p type semiconductor layer 30, the boron concentration of its periphery of boron concentration ratio of the central portion 30a of each layer is higher.
The situation of this example forms by 5 layers of the 4th p type semiconductor layer 30 that constitutes.Therefore, in order to form these by 5 layers of the 4th p type semiconductor layer 30 that constitutes, the ion that carries out 5 boron injects.The injection energy that these 5 secondary ions inject and the dosage of B ion are set at successively since the 1st time: under about 200KeV about 7 * 10
12Cm
-2, under about 400 KeV about 5 * 10
11Cm
-2, under about 650 KeV about 5 * 10
11Cm
-2, under about 1100KeV about 5 * 10
11Cm
-2, and under about 1700KeV about 5 * 10
11Cm
-2Under this setting (injection condition), in the moment that the ion that finishes 5 times injects, use respectively by 5 layers of the 4th p type semiconductor layer 30 that constitutes seamlessly landfill between the surface element of each STI29 and test section 27 and P type trap 25.That is, finishing the moment that 5 secondary ions inject, the N type epitaxial loayer 23 between the surface element of each STI29 and test section 27 and P type trap 25 carries out substantial P type semiconductor stratification by the 4th p type semiconductor layer 30 that constitutes by 5 layers.Having, be separately positioned in the 4th p type semiconductor layer 30 of downside of test section 27, the 4th p type semiconductor layer 30 under the test section 27, is that the 4th p type semiconductor layer 30 of the superiors also stops layer as so-called puncture and works.
In above-mentioned ion injecting process,, the boron in the P type semiconductor substrate 22 is oozed out from P type semiconductor substrate 22 to N type epitaxial loayer 23 sides by thermal diffusion.Thus, and carry out comparing before ion injects, will be as the PN junction 24 in conjunction with interface of N type epitaxial loayer 23 and P type trap 25 further to N/P
+Type substrate 21 sides rise.Particularly, the thickness at the N type epitaxial loayer 23 that finishes the moment that 5 secondary ions inject is about 2.0 μ m.That is, the PN junction 24 in the moment that finishes the injection of 5 secondary ions is positioned at apart from N/P
+The degree of depth place of surperficial about 2.0 μ m of type substrate 21.Therefore, from N/P
+Substantial P type semiconductor stratification can be carried out by the 4th p type semiconductor layer 30 that constitutes by 5 layers to the N type epitaxial loayer 23 that the thickness of PN junction 24 is about 2.0 μ m in the surface of type substrate 21.
Like this, be provided with respectively and have the degree of depth that arrives P type trap 25 under STI29 and the test section 27, the 4th p type semiconductor layer 30 that constitutes by 5 layers is not set interruptedly, continuously along STI29 and test section 27.Thus, make photodiode 28 and other photodiode 28 element separation aspect electric that is adjacent to each other.That is, with the 4th p type semiconductor layer 30 that is provided with around the mode of photodiode 28 separately respectively just with P type trap 25, as being worked in the barrier layer of electricity isolation between the photodiode 28.
In addition, under the situation of this example, even at N/P with wafer-like
+Type substrate 21 cuts into the chip cut-out portion 15 of a plurality of chips, and the 4th p type semiconductor layer 30 that constitutes by 5 layers is set similarly.The 4th p type semiconductor layer 30 and the 4th p type semiconductor layer 30 that is arranged on the downside of STI29 and test section 27 of this chip cut-out portion 15 form simultaneously.Promptly in the present embodiment, the downside of STI29 and test section 27 be provided with respectively by become the barrier layer by 5 layers of the 4th p type semiconductor layer 30 that constitutes the time, also simultaneously corresponding scribe line is partly divided, N type epitaxial loayer 23 boron ion implantations.Thus, identical with each the 4th p type semiconductor layer 30 of the downside that is arranged on each STI29 and test section 27, in chip cut-out portion 15, interruptedly be not provided with continuously have from the surface element of N type epitaxial loayer 23 arrive P type trap 25 the degree of depth, by 5 layers of the 4th p type semiconductor layer 30 that constitutes.Like this, even at N/P
+In the chip cut-out portion 15 of type substrate 21, from N/P
+Substantial P type semiconductor stratification also can be carried out by the 4th p type semiconductor layer 30 that constitutes by 5 layers to the N type epitaxial loayer 23 of the about 2.0 μ m of the thickness of PN junction 24 in the surface of type substrate 21.
Under the situation of this structure, do not increase operation quantity and carry out simultaneously just can easily forming as the 4th p type semiconductor layer 30 on barrier layer and the 4th p type semiconductor layer 30 of chip cut-out portion 15.
In addition, N/P
+Type substrate 21 in the operation of back, is divided into a plurality of chips along chip cut-out portion 15.In chip section 15, from N/P
+The surface of type substrate 21 to the back side is by the 4th p type semiconductor layer 30, and P type trap 25 and P type semiconductor substrate 22 constitute.Therefore, in chip cut-out portion 15, even cut off N/P
+Type substrate 21 can not present PN junction 24 at this section yet.
And, become S3 (surperficial shield sensor) structure in order to make photodiode 28, at the surface element of photodiode 28 shielding (shield) layer (PD-p layer) 32 is set respectively.Particularly, at first, on the surface of the N type epitaxial loayer 23 except that photodiode 28, pattern forms not shown resist film so that it becomes the figure of regulation.After this, inject boron at the surface element intermediate ion of photodiode 28 as p type impurity.At this moment, the dosage setting that injects energy and B ion is under about 10KeV 1 * 10
13Cm
-2Thus, the surface element (surface level) that covers respectively as the photodiode 28 of n type semiconductor layer by the screen 32 as p type semiconductor layer that is formed by boron shields.That is, form screen 32 by the surface element at photodiode 28, the n type semiconductor layer (28) that just can carry out opto-electronic conversion is just in fact imbedded the skin section of N type epitaxial loayer 23.By like this, use the p type semiconductor layer (32) that forms by boron to shield the surface of n type semiconductor layer (28), form the photodiode 28 of S3 structure.
Under the situation of this structure,, improve concentration once more as the boron of p type impurity at the near surface of photodiode 28.Particularly, the concentration of the boron of the near surface of photodiode 28 becomes about 1 * 10
19Cm
-3
On the other hand, as mentioned above, in the part of corresponding peripheral circuit simulated domain 13 and peripheral circuit logic region 14, form respectively P type trap 13 ', 14.With the mode of adjacency camera watch region 11 form P type trap 13 ', 14 '.Particularly, on the surface of N type epitaxial loayer 23, pattern forms not shown resist film so that it becomes the figure of regulation.After this, inject boron to the surface element ion of N type epitaxial loayer 23 as p type impurity.At this moment, as the degree of depth of the peak value of the boron concentration of the concentration of p type impurity mainly the size of the energy when injecting the B ion decide.
In the present embodiment, as the injection condition of B ion, the dosage setting that injects energy and B ion is under about 800KeV about 1 * 10
13Cm
-2And under about 1500KeV about 5 * 10
11Cm
-2Under this setting (injection condition), at the surface element 2 secondary ions injection boron of N type epitaxial loayer 23.Thus, at the degree of depth place of surperficial about 2.0 μ m of distance N type epitaxial loayer 23, form respectively the P type trap 13 that constitutes by the 1st, the 2nd semiconductor layer with boron concentration curve profile ', 14 '.That is, at N/P
+The skin section of type substrate 21, across P type trap 25, be provided with the P type trap 13 be connected P type semiconductor substrate 22 ', 14 '.P type trap 13 ', 14 ' in boron concentration be set at about 2 * 10
15Cm
-3
Then, in the peripheral circuit simulated domain 13 of the peripheral circuit 12 that is used to form the simulation class, utilize the conventional ADC12a that is processed to form.Though at length do not illustrate in the accompanying drawings for easy, the P of corresponding peripheral circuit simulated domain 13 type trap 13 ' near surface, for example be formed for forming the P type trap 12 of N type MOS transistor respectively
-1And be used to form the N type trap 12 of P type MOS transistor
-2That is, at P type trap 12
-1The middle N type MOS transistor that forms is at N type trap 12
-2The middle P type MOS transistor that forms realizes the assembling of ADC12a.
In addition, in the peripheral circuit simulated domain 14 of the peripheral circuit 12 that is used to form logic class, utilize conventional DAC12b, timing control circuit 12c, TG/SG 12d, DSP12e, coding circuit 12f, agc circuit 12g, CLP circuit 12h and the output circuit 12i of being processed to form.Though at length do not illustrate in the accompanying drawings for easy, the P type trap 14 of the logic region 14 of corresponding peripheral circuit ' near surface, for example be formed for forming the P type trap 12 of N type MOS transistor respectively
-1And be used to form the N type trap 12 of P type MOS transistor
-2That is, at P type trap 12
-1The middle N type MOS transistor that forms is at N type trap 12
-2The middle P type MOS transistor that forms realizes the assembling of DAC12b, timing control circuit 12c, TG/SG 12d, DSP12e, coding circuit 12f, agc circuit 12g, CLP circuit 12h and output circuit 12i.
Finally, after through the operation that is processed to form regulations such as aluminium (Al) wiring of utilizing routine, along the 15 scribing N/P of chip cut-out portion
+Type substrate 21 is cut apart respectively by chip unit.Thus, finish cmos image sensor according to this example.Its result has obtained the aforesaid cmos image sensor that is formed by desirable structure.That is, using N/P
+In the cmos image sensor of type substrate 21, photodiode 28 is fenced up individually by P type trap 25 and the 4th p type semiconductor layer 30, and is electrically isolated from one, and can stop the section at chip PN junction 24 to occur.Meanwhile, can obtain, form the P type trap 13 of the peripheral circuit 12 of simulation class ' and form the cmos image sensor of the P type trap 14 of the peripheral circuit 12 of logic class ' be connected with P type semiconductor substrate 22 by P type trap 25.
Fig. 3 is illustrated in the cmos image sensor of said structure, along N/P
+The figure of the impurity concentration curve profile of the thickness direction of type substrate 21.At this, show peripheral circuit simulated domain 13 that represent with the III-III line among Fig. 2, corresponding (P type trap 12 particularly
-1) part, with respect to the boron concentration of depth direction.
Promptly the part of corresponding peripheral circuit simulated domain 13 is set, so that P type trap 12
-1, P type trap 13 ', the boron concentration separately of P type trap 25 and P type semiconductor substrate 22 is as shown in this figure.Have again, even for corresponding peripheral circuit logic region 14 (P type trap 12 particularly
-1) part, for the boron concentration of depth direction, also almost similarly set.
Fig. 4 is the plane graph of a part of the camera watch region 11 of the above-mentioned cmos image sensor of expression.As indicated in Fig. 4, photodiode 28 its peripheries are surrounded by the 4th p type semiconductor layer 30.Thus, each photodiode 28 is isolated, is insulated with other photodiode 28 electricity of adjacency by being arranged on its each the 4th p type semiconductor layer 30 on every side.
Fig. 5 has schematically illustrated the structure of the pixel in the above-mentioned cmos image sensor.Each dot structure of cmos image sensor is for having: reset transistor 1, read transistor 2, amplifier transistor 3, address transistor 4 and photodiode 28.Reset transistor 1 and reading between the source drain of transistor 2 directly connects.Similarly, directly connect between the source drain of amplifier transistor 3 and address transistor 4.In addition, the grid of amplifier transistor 3 is connected reset transistor 1 and reads on the tie point between the source drain of transistor 2.And photodiode 28 its terminals along the direction side are connected to the source electrode (or drain electrode) of reading transistor 2.
Then, with reference to Fig. 6, illustrate present embodiment cmos image sensor along N/P
+The impurity concentration of the thickness direction of type substrate, electron distributions and electromotive force.Fig. 6 represents respectively along impurity concentration, electron distributions and the electromotive force of the VI-VI line of the cmos image sensor shown in Fig. 2.
At first, the curve chart of the epimere side of key diagram 6.In the curve chart of Fig. 6 epimere side, the impurity concentration in the screen 32 that constitutes by p type semiconductor layer with the Regional Representative of " B " expression among the figure.In addition, the impurity concentration in the photodiode 28 that constitutes by n type semiconductor layer with the Regional Representative of " C " expression among the figure.In addition, the impurity concentration in the Regional Representative N type epitaxial loayer of representing with " D " among the figure 23.In addition, the impurity concentration in the Regional Representative P type trap of representing with " E " among the figure 25.Impurity concentration in Regional Representative's P type semiconductor substrate 22 of representing with " F " among the figure is arranged again.
As indicated in the curve chart of the epimere side of Fig. 6, the surface from the deep layer portion of P type semiconductor substrate 22 to P type trap 25 lowers at leisure as the boron concentration of p type impurity concentration.And, locate at the P type trap 25 of the position that is positioned at the about 2.0 μ m of the degree of depth and the interface (24) of N type epitaxial loayer 23, because the conduction type of impurity is different,, become precipitous curved profile so impurity concentration sharply changes.In addition, the interface of the photodiode 28 that constitutes at N type epitaxial loayer 23 with by n type semiconductor layer is because impurity is identical, so impurity concentration gently changes.And, in photodiode 28,, reach peak value as the phosphorus concentration of N type impurity at the about 0.4 μ m place of the degree of depth.Also have, the interface of the screen 32 that constitutes at photodiode 28 with by p type semiconductor layer, because impurity is different, impurity concentration temporarily lowers.And, in screen 32,, reach peak value as the boron concentration of p type impurity concentration at its near surface.In addition, as indicated in the curve chart of the epimere side of Fig. 6, N/P
+The peak value (greatly) of the N type impurity concentration (phosphorus concentration) in the peak value (greatly) of the distribution of the electronics in the type substrate 21 (charge carrier) and the photodiode 28 is consistent basically.
Then, the curve chart of key diagram 6 hypomere sides.The curve chart of the hypomere side of Fig. 6 shows N/P
+Potential Distribution in the type substrate 21.As indicated in the curve chart of the curve chart of Fig. 6 hypomere side and Fig. 6 epimere side, N/P
+Electromotive force in the type substrate 21 is the peak value (greatly) and the N/P of the position of minimum (minimum) and the N type impurity concentration (phosphorus concentration) in the photodiode 28
+The position of the peak value of the electron distributions in the type substrate 21 (greatly) is consistent basically.
N/P
+Electronic motion in the type substrate 21 (action) is mated with the physical phenomenon usually very much.That is, by the photoelectric action of photodiode 28, even at N/P
+The electronics that produces in the type substrate 21 leaks and is diffused into as N/P from photodiode 28
+P type semiconductor substrate 22 sides of the deep layer portion side of type substrate 21 also can be returned because of the potential barrier wall and transit to N/P
+The skin section side of type substrate 21.And the electronics that lets out from photodiode 28 finally passes through diffusion etc., accumulates in N/P once more
+In the photodiode 28 of the electromotive force step-down in the type substrate 21.Particularly, the electronics that lets out from photodiode 28 gathers N/P once more
+The impurity concentration that electromotive force in the type substrate 21 becomes in the photodiode 28 of minimum (minimum) is the position of peak value.Its result is using N/P
+In the cmos image sensor of the present embodiment of type substrate 21, can improve the photosensitivity of photodiode 28.
As mentioned above, according to this 1st execution mode, can make the P type trap 13 that forms simulation class peripheral circuit 12 ' and form the P type trap 14 of logic class peripheral circuit 12 ', by P type semiconductor substrate 22 ground connection.Therefore, the good signal that becomes waveform stabilization by the pulse signal of logical circuit and analog circuit generation can be made, the problem of the time-shifting of so-called pulse generation can be solved.And, using N/P
+In the cmos image sensor of type substrate 21,, can isolate photodiode 28 by electricity, can stop section PN junction 24 to occur simultaneously at chip by P type trap 25 and the 4th p type semiconductor layer 30.Therefore, just can obtain to suppress that colour mixture, the photosensitivity that electronics produces descends, the cmos image sensor of bloom because of leaking in pixel adjacent (photodiode).Its result is using N/P
+In the cmos image sensor of type substrate, on can being formed in colour mixture sensitization skin bloom characteristic, in the good structure, the high frequency characteristic of peripheral circuit etc. can also be kept, the structure that is fit to many pixelations or high speed more can be constituted.
(the 2nd execution mode)
Fig. 7 represents employing N/P second embodiment of the invention
+The basic structure of the cmos image sensor of substrate (amplification type solid state imaging device).In the present embodiment, be that example describes with the cmos image sensor of singualtion.In addition, the N/P that illustrates respectively at corresponding peripheral circuit simulated domain 13
+The skin section of type substrate 21 form dark P type trap (second p type semiconductor layer) ', at the N/P of corresponding peripheral circuit logic region 14
+The skin section of type substrate 21 forms than P type trap 13 ' shallow P type trap (first p type semiconductor layer) 14 " situation.Have again, give identical symbol, omit its detailed explanation at this to the part identical with Fig. 2.
That is, this 2nd execution mode and above-mentioned the 1st execution mode difference are that in peripheral circuit simulated domain 13 and peripheral circuit logic region 14, only the P type trap 13 ' structure of peripheral circuit simulated domain 13 is for to be connected to P type semiconductor substrate 22 by P type trap 25.
In addition, Fig. 8 illustrate according to the cmos image sensor of present embodiment, along N/P
+The impurity concentration curve profile of the thickness direction of type substrate.At this, show peripheral circuit logic region 14 that represent by the VIII-VIII line among Fig. 7, corresponding (P type trap 12 particularly
-1) part, with respect to the boron concentration of depth direction.So figure is indicated, at N type epitaxial loayer 23 and P type trap 14 " interface, and the interface of N type epitaxial loayer 23 and P type trap 25, it is rapid that change in concentration separately becomes.This be because, " and the N type epitaxial loayer 23 that has films of opposite conductivity each other of P type trap 25 at the P of corresponding peripheral circuit logic region 14 type trap 14.
Under the situation of present embodiment, for example as shown in Figure 7, P type trap 13 ', be formed on continuously corresponding peripheral circuit simulated domain 13 ' the zone, have from N/P
+The skin section of type substrate 21 arrives the degree of depth of P type trap 25 (or P type semiconductor substrates 22).With respect to this, P type trap 14 " is formed on the zone of corresponding peripheral circuit logic region 14, for example has apart from N/P
+The degree of depth about the skin section 1 μ m of type substrate 21.
That is, at the N/P of corresponding peripheral circuit simulated domain 13
+In the skin section of type substrate 21 with the mode of adjacency camera watch region 11 form P type trap 13 '.P type trap 13 ' always is formed into dark position (about 2.0 μ m), contacts with P type trap 25.On the other hand, at the N/P of corresponding peripheral circuit 14
+In the skin section of type substrate 21, form P type trap 14 " in mode with camera watch region 11 adjacency.P type trap 14 " is not formed into dark position, does not contact with P type trap 25.Particularly, on the surface of N type epitaxial loayer 23, pattern forms not shown resist film, becomes the figure of regulation.After this, inject boron to the surface element intermediate ion of N type epitaxial loayer 23 as p type impurity.At this moment, as the mainly size decision of the energy when injecting the B ion of the degree of depth of the peak value of the boron concentration of the concentration of p type impurity.
As the injection condition of B ion, the 1st time the injection energy and the dosage of B ion are set under about 800KeV about 1 * 10 respectively
13Cm
-2, the 2nd time the injection energy and the dosage of B ion are set under 1500KeV about 5 * 10 respectively
11Cm
-2Under this setting (injection condition), when the formation of the resist film that repeats compulsory figure and peeling off, the ion that also carries out 2 times (the 1st times and the 2nd time) in the part of corresponding peripheral circuit simulated domain 13 injects, form dark P type trap 13 '.On the other hand, carrying out 1 (only any 1 time of the 1st time or the 2nd time) ion in the part of corresponding peripheral circuit logic region 14 injects, forms than P type trap 13 ' shallow P type trap 14 ".Thus, at the N/P of corresponding peripheral circuit simulated domain 13
+In the skin section of type substrate 21, form apart from P type trap 13 degree of depth of surperficial about 2.0 μ m of N type epitaxial loayer 23, that constitute by second p type semiconductor layer with boron concentration curve profile '.With respect to this, at the N/P of corresponding peripheral circuit logic region 14
+In the skin section of type substrate 21, form " apart from P type trap 14 degree of depth of surperficial about 1.0 μ m of N type epitaxial loayer 23, that constitute by first p type semiconductor layer with boron concentration curve profile.
Like this, respectively at N/P
+In the skin section of type substrate 21, across P type trap 25, be provided with the P type trap 13 be connected P type semiconductor substrate 22 ', and because of with P type trap 25 between the P type trap 14 that do not link to each other of residual N type epitaxial loayer 23 with P type semiconductor substrate 22 ".P type trap 13 ', 14 " in boron concentration (p type impurity concentration) for example be set at about 2 * 10
15Cm
-3
Then, in the peripheral circuit simulated domain 13 of the peripheral circuit 12 that is used to form the simulation class, utilize the conventional ADC12a that is processed to form.In addition, in the peripheral circuit simulated domain 14 of the peripheral circuit 12 that is used to form logic class, utilize conventional DAC12b, timing control circuit 12c, TG/SG12d, DSP12e, coding circuit 12f, agc circuit 12g, CLP circuit 12h and the output circuit 12i of being processed to form.Though at length do not illustrate in the accompanying drawings for easy, but the P of corresponding peripheral circuit simulated domain 13 type trap 13 ' near surface and the P type trap 14 of the logic region 14 of corresponding peripheral circuit " near surface, for example be formed for forming the P type trap 12 of N type MOS transistor respectively
-1And be used to form the N type trap 12 of P type MOS transistor
-2
Have again, in the surface element of the N of corresponding peripheral circuit logic region 14 type epitaxial loayer 23 (P type trap 14 " near surface), also for example to inject the about 1500KeV of energy and dosage and about 5 * 10
13Cm
-2Ion injects phosphorus.Thus, can improve the concentration (about 2 * 10 of thin originally N type epitaxial loayer 23
15Cm
-3), can keep trap (12
-1, 12
-2) between isolation withstand voltage.But this operation also can be omitted according to design standard.
As mentioned above, the situation of this structure of present embodiment, about the peripheral circuit 12 of simulation class, because P type trap 13 ' be connected at the bottom of the p type semiconductor layer 22, so can obtain stable zero potential.About logic class peripheral circuit 12, P type trap 14 " is not connected P type semiconductor substrate 22.Therefore, can solve noise that the peripheral circuit 12 of reason logic class produces flies in the camera watch region 11 and in the peripheral circuit simulated domain 13 and the problem of the deterioration of picture characteristics such as so-called vertical stripe that causes and horizontal stripe.Have, the situation of the peripheral circuit 12 of logic class as the peripheral circuit 12 of simulation class, can not make deterioration in characteristics owing to the distortion and the delay regularly of a little impulse waveform, so some fluctuations of zero potential do not influence picture characteristics again.
That is, using N/P
+In the cmos image sensor of type substrate 21,, can obtain stable zero potential making the P type trap 13 that forms logic class peripheral circuit 12 ' be connected under the situation of P type semiconductor substrate 22.Therefore, can make the pulse signal that forms by the peripheral circuit 12 of simulating class become stable good waveform, not produce delay regularly.In addition, using N/P
+In the cmos image sensor of type substrate 21, because N/P
+Therefore the charge carrier combination more rapidly that produces in the type substrate 21 can suppress to leak into because of electronics the image quality deterioration of the so-called colour mixture bloom that produces in the pixel adjacent (28).And, using P
+In the cmos image sensor of type substrate 21, P type trap 14 in making peripheral circuit logic region 14 " under the situation of isolating with P type semiconductor substrate 22, can stop the noise that is produced by logic class peripheral circuit 12 to fly in the peripheral circuit simulated domain 13 by P type semiconductor substrate 22 and P type trap 25 and in the camera watch region 11.Thus, can suppress the bad generation of picture characteristics of vertical stripe and horizontal stripe.
Those of ordinary skills understand additional advantage easily and make amendment.Therefore, at concrete detailed and each embodiment that explains that the invention is not restricted in this displaying and description aspect the more wide region of the present invention.Therefore, within the spirit and scope that do not break away from accessory claim and the basic conception of the present invention that equivalents limited thereof, can carry out various modifications.
Claims (16)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005327601A JP4679340B2 (en) | 2005-11-11 | 2005-11-11 | Solid-state imaging device |
| JP2005327601 | 2005-11-11 |
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| Publication Number | Publication Date |
|---|---|
| CN101017837A true CN101017837A (en) | 2007-08-15 |
| CN100524787C CN100524787C (en) | 2009-08-05 |
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|---|---|
| US (1) | US7709870B2 (en) |
| JP (1) | JP4679340B2 (en) |
| KR (1) | KR100860198B1 (en) |
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2005
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-
2006
- 2006-11-09 US US11/558,200 patent/US7709870B2/en active Active
- 2006-11-10 KR KR1020060110826A patent/KR100860198B1/en not_active Expired - Fee Related
- 2006-11-10 CN CNB2006100644818A patent/CN100524787C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840924A (en) * | 2009-03-18 | 2010-09-22 | 株式会社东芝 | Semiconductor device and back-illuminated solid-state imaging device |
| CN104137263A (en) * | 2012-01-23 | 2014-11-05 | 索尼公司 | Solid-state image pickup apparatus, method for manufacturing solid-state image pickup apparatus, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070050837A (en) | 2007-05-16 |
| KR100860198B1 (en) | 2008-09-24 |
| CN100524787C (en) | 2009-08-05 |
| JP4679340B2 (en) | 2011-04-27 |
| JP2007134581A (en) | 2007-05-31 |
| US20070108487A1 (en) | 2007-05-17 |
| US7709870B2 (en) | 2010-05-04 |
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