CN101005071A - Composite field effect transistor structure - Google Patents

Abstract

The structure of complex type field effect transistor (FET) includes FET of N type lateral double diffusion metallic oxide semiconductor (NLDMOS), and N type junction field effect tube (NJFET). The invention also discloses method for manufacturing the complex type FET. The method includes steps: forming common drain area of NLDMOS and NJFET from N+ diffusion layer in N type extension; forming connection electrode from N+ diffusion layer in N type extension to be as common drain electrode of NLDMOS and NJFET. The disclosed structure and method reduces area of chip effectively so as to be able to provide initial voltage of gate electrode of NLDMOS, and to turn off NLDMOS effectively. The invention reduces power consumption greatly.

Description

Composite field effect transistor structure

Technical Field

The present invention relates to semiconductor devices, and more particularly to field effect transistors.

Background

In high voltage integrated circuits, high voltage lateral double diffused metal oxide semiconductor (LDMOS) or high voltage Junction Field Effect Transistor (JFET) is commonly used as a high voltage tolerant device. In order to effectively reduce the on-resistance while improving the withstand voltage of the LDMOS or JFET device, high withstand voltage and low on-resistance of the circuit can be achieved by controlling the electric field. But only one LDMOS or one JFET is in the same circuit. When the circuit needs the high-voltage LDMOS and the high-voltage JFET at the same time, two separate components, namely the high-voltage LDMOS and the high-voltage JFET, are needed to be adopted, and the high-voltage LDMOS and the high-voltage JFET occupy larger chip area.

On the other hand, in a high-voltage integrated circuit, it is sometimes necessary to effectively control the power supply of the high-voltage terminal to the chip. For a circuit using only N-type LDMOS, if a high voltage supply is needed when the circuit is started, the enhancement-type NLDMOS is not turned on because its gate initial voltage is zero, and if the depletion-type NLDMOS is directly turned on, the problem of initial power-up is solved, but it cannot be turned off by the gate (except for the gate plus a negative voltage). Further, the circuit thus constructed is not only complicated in structure but also extremely high in power consumption.

Disclosure of Invention

Aiming at the defects existing in the use of LDMOS and JFET in the high-voltage integrated circuit, the invention provides a composite field effect transistor structure.

According to one aspect of the present invention, a composite fet structure is provided. It includes: lateral double diffused N-type metal oxide semiconductor field effect transistors (NLDMOS) and N-type junction field effect transistors (njets). The N-type laterally diffused metal oxide semiconductor (NLDMOS) and the N-type field effect transistor (NJFET) of the field effect transistor structure share one drain region, a P-well substrate of the N DMOS and a P-type substrate of the whole chip are used as a grid region of the N JFET, P-type upper isolation layers and P-type lower isolation layers (P-type lower isolation layers 104 in the drawing) are used for forming opposite-connection isolation around the whole N DMOS and the N JFET, and the N DMOS and the N JFET are isolated from other elements on the chip where the structure is. An N + diffusion layer (an N + diffusion layer 107 in the drawing) is arranged between the P-well substrate of the N-type laterally diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source of the NJFET. The N-type epitaxy is not only a drain drift region of the NLDMOS, but also a body region of the NJFET.

Wherein, NLDMOS include:

a P-type substrate as a substrate of the entire structure;

n-type epitaxy;

a drain region formed by an N + diffusion layer (N + diffusion layer 112 in the drawing) within the N-type epitaxy, wherein the N + diffusion layer (N + diffusion layer 112 in the drawing) of the N-type epitaxy forms a connection electrode as a drain;

a P well 110 positioned in the N-type epitaxy is used as a substrate of the NLDMOS, and a P + diffusion layer (a P + diffusion layer 108 in the drawing) on the substrate of the NLDMOS forms a connecting electrode as a substrate connecting end;

an N + diffusion layer (an N + diffusion layer 109 in the figure) in the substrate of the NLDMOS is used as a source region of the NLDMOS, and a connecting electrode is formed in the source region through the N + diffusion layer (the N + diffusion layer 109 in the figure) to serve as a source;

the gate polycrystalline silicon crossing the P well between the source region and the drain region of the NLDMOS is used as the gate of the NLDMOS, an active region and a field region are arranged below the gate of the NLDMOS, the thin oxide region of the active region is used as a gate oxide layer, the field region is positioned above the drain region of the NLDMOS, the active region is positioned above the P well and crosses the P well to intersect the source region and the drain region, and the length of the NLDMOS gate is the length of the intersection of the active region and the P well substrate.

Wherein, the NJFET includes:

the drain region of the NLDMOS is used as the drain region of the NJFET, the P-type substrate of the whole chip and a P-well in an N-type epitaxy are used as the gate region of the NJFET, wherein a P + diffusion layer (a P + diffusion layer 108 in the drawing) in the P-well and a P + diffusion layer (a P + diffusion layer 106 in the drawing) in an upper P-type isolation layer form a connecting electrode as a gate, a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing) form a gate-to-gate isolation, the P-type substrate and the gate are connected, a connecting electrode is formed relative to the N + diffusion layer (an N + diffusion layer 107 in the drawing) on the N-type epitaxy on the NLDMOS gate region and close to the source side, and is used as the source of the NJFET, and the N + diffusion layer (an N + diffusion layer 107 in the drawing) of the NJFET is positioned between the P-.

Further, a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may be disposed between the P-type substrate and the N-type epitaxy near the gate of the NLDMOS of the composite fet structure and near the drain electrode, or a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may not be disposed;

furthermore, an N well layer can be arranged at the drain ends of the NLDMOS and the NJFET of the composite field effect transistor structure, or an N well layer can be omitted;

further, in the composite field effect transistor structure, a P-type diffusion is added on the N-type epitaxy used as the drain drift region of the NLDMOS, namely between the drain terminal of the N + diffusion layer (N + diffusion layer 112 in the drawing) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion can be one section or K section (K > 1). After the P-type diffusion is added, the concentration of N-type epitaxy can be improved, the on-resistance of NLDMOS is reduced, and the optimal design meeting the requirements of high withstand voltage and on-resistance is realized.

Further, in the composite field effect transistor structure, an N + diffusion layer (an N + diffusion layer 109 in the drawing) serving as the source region of the NLDMOS may be included in one N-diffusion layer to improve the withstand voltage of the P-well substrate and the source region of the NLDMOS, or there may be no N-diffusion layer around the N + diffusion layer (the N + diffusion layer 109 in the drawing) of the source region of the NLDMOS, so as to be suitable for use when the voltage of the P-well substrate and the source region of the NLDMOS is low or the P-well substrate and the source region of the NLDMOS are turned on to a potential;

further, the composite field effect transistor is of a completely centrosymmetric circular structure. The following description will be made with a field effect transistor structure having an N-well layer, a P-type lower spacer (P-type lower spacer 103 in the drawing), and an N-diffusion layer, at the center of symmetry, the NLDMOS and the drain of the NJFET, and the drain region of which is composed of an N + diffusion layer (N + diffusion layer 112 in the drawing), an N-well layer, and an N-type epitaxy layer. The N well layer is arranged in the N-type epitaxy and is a certain distance away from the P well, the magnitude of the distance determines the withstand voltage of the NLDMOS and the NJFET, and an N + diffusion layer (an N + diffusion layer 112 in the drawing) is arranged in the N well layer and is positioned at the symmetrical center. The P-type lower isolation layer (P-type lower isolation layer 103 in the figure) for the NLDMOS is located between the P-type substrate of the NLDMOS and the N + diffusion layer (N + diffusion layer 112 in the figure) of the drain of the NLDMOS, and also located between the P-type substrate and the N-type epitaxy. In the field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing) which form a pair-pass isolation, the pair-pass isolation passes through a P + diffusion layer (a P + diffusion layer 106 in the drawing), a contact hole is connected with an aluminum bar and is connected to a low potential, and the contact hole is an isolation contact hole. Between the isolation contact and the P-well substrate of the NLDMOS is an N + diffusion layer (N + diffusion layer 107 in the figure) that serves as the source contact of the NJFET. The P-well is formed between the N + diffusion layer (N + diffusion layer 107 in the drawing) of the source of the NJFET and the N + diffusion layer (N + diffusion layer 112 in the drawing) of the drain of the NLDMOS, and serves as a substrate of the NLDMOS and also serves as a gate of the NJFET. The P + diffusion layer (P + diffusion layer 108 in the figure) in the NLDMOS substrate serves as a substrate contact hole of the NLDMOS, the N + diffusion layer (N + diffusion layer 109 in the figure) in the NLDMOS substrate serves as a source of the NLDMOS, and the N + diffusion layer (N + diffusion layer 109 in the figure) of the source of the NLDMOS also serves as a contact hole. The gate polysilicon is arranged above the edge of the source electrode of the NLDMOS and the side close to the drain region and crosses between the substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the gate polysilicon, one section is a thin oxide layer, the other section is a thick oxide layer, the thin oxide layer crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the overlapping size is determined by the lateral diffusion of an N + diffusion layer (an N + diffusion layer 109 in the drawing), and the thick oxide layer is arranged above an N-type epitaxy used as the drain region of the NLDMOS. The gate polysilicon is connected to the aluminum bar through the contact hole, and the gate polysilicon is the gate of the NLDMOS. The N + diffusion layer (the N + diffusion layer 109 in the drawing) of the NLDMOS source region can be included in one N-diffusion layer to improve the withstand voltage of the NLDMOS substrate and the source region.

According to yet another aspect of the present invention, a composite fet structure is provided. It includes: NLDMOS and njets. The NLDMOS and the NJFET of the field effect transistor structure share a drain region, a P-well substrate of the NLDMOS and a P-type substrate of the whole chip are used as a grid region of the NJFET, P-type upper isolation layers and P-type lower isolation layers (P-type lower isolation layers 104 in the attached drawing) are used for forming opposite-connection isolation around the whole NLDMOS and the NJFET, and the NLDMOS and the NJFET are isolated from other elements on the chip where the structure is located. An N + diffusion layer (an N + diffusion layer 107 in the drawing) is arranged between the P-well substrate of the N-type laterally diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source of the NJFET. The N-type epitaxy is not only a drain drift region of the NLDMOS, but also a body region of the NJFET.

Wherein, NLDMOS include:

a P-type substrate as a substrate of the entire structure;

n-type epitaxy;

a drain region formed by an N + diffusion layer (N + diffusion layer 112 in the drawing) within the N-type epitaxy, wherein the N + diffusion layer (N + diffusion layer 112 in the drawing) of the N-type epitaxy forms a connection electrode as a drain;

the P trap in the N-type epitaxy is used as the substrate of the NLDMOS, and a P + diffusion layer (a P + diffusion layer 108 in the drawing) on the substrate of the NLDMOS forms a connecting electrode as a substrate connecting end;

an N + diffusion layer (an N + diffusion layer 109 in the figure) in a P-well substrate of the NLDMOS is used as a source region of the NLDMOS, and a connecting electrode is formed in the source region through the N + diffusion layer (the N + diffusion layer 109 in the figure) to be used as a source;

the gate polysilicon crossing the source region and the drain region of the NLDMOS is used as a gate of the NLDMOS, an active region and a field region are arranged below the gate polysilicon of the NLDMOS, the thin oxide region of the active region is used as a gate oxide layer, the field region is positioned above the drain region of the NLDMOS, the active region is positioned above the P well and crosses the P well to intersect the source region and the drain region, and the length of the NLDMOS gate is the length of the intersection of the active region and the P well substrate.

Wherein, the NJFET includes:

the drain region of the NLDMOS is used as the drain region of the NJFET, the P-type substrate of the whole chip and a P-well in an N-type epitaxy are used as the gate region of the NJFET, a P + diffusion layer (a P + diffusion layer 108 in the drawing) in the P-well and a P + diffusion layer (a P + diffusion layer 106 in the drawing) in an upper P-type isolation are used as electrodes to be connected to form a gate, an upper P-type isolation layer and a lower P-type isolation layer (a lower P-type isolation layer 104 in the drawing) form a gate-to-gate isolation, the P-type substrate and the gate are connected, a connection electrode is formed on an N + diffusion layer (an N + diffusion layer 107 in the drawing) on the N-type epitaxy, which is opposite to the gate region of the NLDMOS and close to the source side, and is used as the source of the NJFET, and the N + diffusion layer (an N + diffusion layer 107 in the drawing) of the NJF.

Further, in the composite field effect transistor structure, a P-type lower isolation layer (a P-type lower isolation layer 103 in the drawing) may be arranged between the P-type substrate and the N-type epitaxy near the gate of the NLDMOS and near the drain electrode, or a P-type lower isolation layer (a P-type lower isolation layer 103 in the drawing) may not be arranged;

furthermore, the drain electrode terminals of the NLDMOS and the NJFET of the composite field effect transistor structure can be provided with an N well layer or not;

furthermore, in the composite field effect transistor structure, a P-type diffusion layer is added on an N-type epitaxy used as an NLDMOS drain drift region, namely between a drain leading-out end of an N + diffusion layer (an N + diffusion layer 112 in the attached drawing) of an NLDMOS drain region and a P-well substrate of the NLDMOS, wherein the P-type diffusion layer can be a section or a K section (K is more than 1), and after the P-type diffusion is added, the concentration of the N-type epitaxy can be improved, the on-resistance of the NLDMOS can be reduced, and the optimized design meeting the requirements of high withstand voltage and on-resistance can be realized;

further, in the composite field effect transistor structure, an N + diffusion layer (an N + diffusion layer 109 in the drawing) serving as the source region of the NLDMOS may be included in one N-diffusion layer to improve the withstand voltage of the P-well substrate and the source region of the NLDMOS, or there may be no N-diffusion layer around the N + diffusion 2 of the source region of the NLDMOS, so as to be suitable for use when the voltage of the P-well substrate and the source region of the NLDMOS is low or the P-well substrate and the source region of the NLDMOS are turned on to a potential;

further, the composite type field effect transistor is in a partial central symmetry circular structure, wherein the NLDMOS is in complete central symmetry, and the NJFET is in partial central symmetry. The following description will be made using a field effect transistor structure having an N-well layer, a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing), and an N-diffusion layer. At the center of symmetry is the drain region of the high voltage NLDMOS and high voltage NJFET, which consists of an N + diffused layer (N + diffused layer 112 in the figure), an N-well layer and an N-type epitaxy. The N + diffusion layer (the N + diffusion layer 112 in the drawing) is arranged at a certain distance from the P well, the size of the distance determines the voltage resistance of the NLDMOS and the NJFET, and the N + diffusion layer (the N + diffusion layer 112 in the drawing) is arranged in the N well layer and is positioned at the symmetrical center. The P-type lower isolation layer (P-type lower isolation layer 103 in the figure) for the NLDMOS is located between the P-type substrate of the NLDMOS and the N + diffusion layer (N + diffusion layer 112 in the figure) of the drain of the NLDMOS, and also located between the P-type substrate and the N-type epitaxy. In the composite field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is an opposite-through isolation formed by a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing), the opposite-through isolation is connected to a low potential through a P + diffusion layer (a P + diffusion layer 106 in the drawing) and is connected to an aluminum strip through a contact hole, and the contact hole is an isolation contact hole. The N + diffusion layer (the N + diffusion layer 107 in the drawing) is used as a source contact hole of an NJFET between an isolation contact hole and a P-well substrate of the NLDMOS; the other arc is an N + diffusion layer (N + diffusion layer 107 in the drawing) which is not used as a source contact hole of an NJFET between the isolation contact hole and the P-well substrate of the NLDMOS. The sizes of the two arcs can be changed according to the convenience and the actual requirement of the layout. The P-well is formed between the N + diffusion layer (N + diffusion layer 107 in the drawing) of the source of the NJFET and the N + diffusion layer (N + diffusion layer 112 in the drawing) of the drain of the NLDMOS, and serves as a substrate of the NLDMOS and also serves as a gate of the NJFET. In the substrate of the NLDMOS, there are a P + diffusion layer (P + diffusion layer 108 in the drawing) for a substrate contact hole of the NLDMOS and an N + diffusion layer (N + diffusion layer 109 in the drawing) for a source of the NLDMOS, and the N + diffusion layer (N + diffusion layer 109 in the drawing) for a source of the NLDMOS is also used for the contact hole. The gate polysilicon is arranged above the edge of the source electrode of the NLDMOS and the side close to the drain region, crosses between the substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the gate polysilicon, one section of the oxide layer is a thin oxide layer, the other section of the oxide layer is a thick oxide layer, the thin oxide layer crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the size of the overlapping is determined by the lateral diffusion of an N + diffusion layer (an N + diffusion layer 109 in the drawing), and the thick oxide layer is arranged above an N-type epitaxy used as the drain region. The gate polysilicon is connected to the aluminum bar through the contact hole, and the gate polysilicon is the gate of the NLDMOS. The N + diffusion layer (the N + diffusion layer 109 in the drawing) of the NLDMOS source region can be included in one N-diffusion layer to improve the withstand voltage of the NLDMOS substrate and the source region.

According to still another aspect of the present invention, there is provided a method of manufacturing a composite type field effect transistor. It comprises the following steps:

taking a P-type substrate of the NLDMOS as a substrate of the whole chip;

forming an N + diffusion layer (an N + diffusion layer 112 in the drawing), an N + diffusion layer (an N + diffusion layer 109 in the drawing), an N + diffusion layer (an N + diffusion layer 107 in the drawing), a P + diffusion layer (a P + diffusion layer 106 in the drawing), and a P + diffusion layer (a P + diffusion layer 108 in the drawing) on an N-type epitaxy of the NLDMOS;

a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing) are generated around the whole NLDMOS and the NJFET to form a pair-pass isolation;

the P well in the N-type epitaxy is used as the substrate of the NLDMOS, and the substrate using the NLDMOS comprises the N + diffusion layer (an N + diffusion layer 109 in the drawing) and the P + diffusion layer (a P + diffusion layer 108 in the drawing); and

forming the N + diffusion layer (the N + diffusion layer 112 in the figure) in the N-type epitaxy into a drain region of the NLDMOS, and forming a connecting electrode by using the N + diffusion layer (the N + diffusion layer 112 in the figure) as a common drain of the NLDMOS and the NJFET; forming a connecting electrode on the P + diffusion layer (P + diffusion layer 108 in the figure) on the substrate of the NLDMOS as a substrate connecting end of the NLDMOS; taking the N + diffusion layer (the N + diffusion layer 109 in the figure) in the substrate of the NLDMOS as a source region of the NLDMOS, and forming a connecting electrode through the N + diffusion layer (the N + diffusion layer 109 in the figure) to be used as a source of the NLDMOS; taking gate polysilicon which crosses a P well between a source region and a drain region of the NLDMOS and intersects with the source region and the drain region of the NLDMOS as a gate of the NLDMOS; and

forming a connection electrode between the P + diffusion layer (P + diffusion layer 108 in the figure) in the P well and the P + diffusion layer (P + diffusion layer 106 in the figure) in the P-type upper isolation to serve as a gate of the NJFET; the N + diffusion layer (N + diffusion layer 107 in the drawing) on the N-type epitaxy which is close to the source side of the NLDMOS with respect to the gate region of the NLDMOS forms a connection electrode as the source of the NJFET.

In addition, in the composite field effect transistor, a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may be added between the P-type substrate and the N-type epitaxy near the gate of the NLDMOS and near the drain, or a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may not be added;

in addition, in the composite field effect transistor, an N well layer can be added at the drain electrode terminal of the NLDMOS and the NJFET, or the N well layer is not added;

in addition, in the composite field effect transistor, a section or K section (K is more than 1) of P-type diffusion layer can be added between the drain leading-out end of the N + diffusion layer (N + diffusion layer 112 in the drawing) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and further, after the P-type diffusion layer is added, the concentration of N-type epitaxy can be improved, the on-resistance of the NLDMOS can be reduced, and the optimal design of a chip can be realized;

in addition, in the composite field effect transistor, an N-diffusion layer may be added between a P-well and an N + diffusion layer (the N + diffusion layer 109 in the drawing), or an N-diffusion layer may not be added, and further, after the N-diffusion layer is added, the withstand voltage of a P-well substrate and a source region of the NLDMOS is increased, while the N-diffusion layer is not added, and the N-diffusion layer is mainly used when the voltage of the P-well substrate and the source region of the NLDMOS is low or the P-well substrate and the source region of the NLDMOS are turned on to a potential;

in addition, the composite field effect transistor can be manufactured into a circular structure with complete central symmetry or a circular structure with partial central symmetry, and further, in the circular structure with partial central symmetry, the NLDMOS structure is completely central symmetry, and the NJFET structure is partially central symmetry.

By using the composite field effect transistor structure, the area of a chip can be effectively reduced when the same voltage is applied to the high-voltage ends of the NLDMOS and the NJFET, the initial voltage of a grid electrode of the NLDMOS can be provided, the NLDMOS can be effectively turned off, and therefore power consumption is greatly reduced.

Drawings

The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,

fig. 1 shows an overall longitudinal sectional structural view of a composite field effect transistor of the present invention;

FIG. 2 is a schematic diagram showing a longitudinal cross-sectional structure of the composite FET of the present invention in full central symmetry;

FIG. 3 is a schematic diagram showing a longitudinal cross-sectional structure of a composite FET of the present invention having a P-type diffusion 539;

fig. 4 is a schematic diagram showing a longitudinal sectional structure of the composite type field effect transistor of the present invention without the N-well layer 111;

fig. 5 shows a schematic longitudinal sectional structure of the composite fet of the present invention without the P-type lower isolation 103;

FIG. 6 is a schematic diagram showing a longitudinal cross-sectional structure of a composite field effect transistor of the present invention having an N-diffusion layer 640;

FIG. 7 is a longitudinal and top view of a composite field effect transistor of the present invention showing central symmetry;

fig. 8 is a longitudinal view and a top view of a composite field effect transistor of the present invention showing partial central symmetry; while

Fig. 9 is a schematic circuit diagram of the NLDMOS and the NJFET corresponding to fig. 1 to 8.

Detailed Description

Various embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

Fig. 2 shows an embodiment of the composite field effect transistor of the present invention.

As shown in fig. 2, the composite type field effect transistor exhibits perfect central symmetry and has a P-type lower isolation layer 103 and an N-well layer 111. The P-type lower isolation layer 103 is located near the gate polysilicon 130 of the NLDMOS and between the P-type substrate 101 and the N-type epitaxy 102 on the side close to the drain electrode, and the N-well layer 111 is located at the drain electrode terminals of the NLDMOS and the NJFET. In the composite field effect transistor structure, the NLDMOS and the NJFET share one drain region, a P-well substrate of the NLDMOS and a P-type substrate 101 of the whole chip are used as a grid region of the NJFET, a P-type upper isolation layer 105 and a P-type lower isolation layer 104 are used for forming an opposite-pass isolation around the whole NLDMOS and the NJFET, and the NLDMOS and the NJFET are separated from other elements on the chip where the structure is located. An N + diffusion layer 107 is arranged between the P-well substrate of the N-type laterally diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source region of the NJFET. The N-type epitaxy 102 is both the drain drift region of the NLDMOS and the body region of the NJFET.

Fig. 3 is added with a P-type diffusion layer 539 on the basis of fig. 2, and the P-type diffusion layer 539 is located between a drain terminal of the N + diffusion layer 112 of the NLDMOS drain region and a P-well substrate of the NLDMOS. After the P-type diffusion layer 539 is added, the basic characteristics of the whole chip are unchanged, the concentration of the N-type epitaxy 102 can be improved, and the on-resistance of the NLDMOS is reduced, so that the optimal design of the chip is realized.

Fig. 4 is a view of fig. 2 with an N-well layer 111 removed. The structure without the N well layer 111 can increase the on-resistance of the NLDMOS and the NJFET, and is suitable for being applied to circuits with low on-resistance requirements.

Fig. 5 is a diagram of fig. 2, in which a P-type lower isolation layer 103 is removed, and the structure without the P-type lower isolation layer 103 can improve the pinch-off characteristic of the NJFET, so that the NJFET has a better constant current characteristic.

Fig. 6 adds an N-diffusion layer 640 to that of fig. 2. The N-diffusion layer 640 is positioned in the P-well substrate 110, and the N + diffusion layer 109 of the NLDMOS source region is contained in the N-diffusion layer 640, so that the withstand voltage value between the substrate and the source terminal of the NLDMOS can be improved, and the N-diffusion layer is suitable for being applied to circuits which need to bear larger withstand voltage at the substrate and the source terminal.

Fig. 7 shows yet another embodiment of the composite field effect transistor structure of the present invention. As shown in fig. 7, the entire structure exhibits a completely centrosymmetric circular structure having an N-well layer 111 and a P-type lower isolation layer 103 therein. Located at the center is the drain of the high voltage NLDMOS and high voltage NJFET, which is composed of N + diffused layer 112, N-well layer 111 and N-type epitaxy 102. The N-well layer 111 is spaced from the P-well 110 within the N-type epitaxy 102 by a distance, the size of the distance determines the breakdown voltage of the NLDMOS and the NJFET, and the N + diffusion layer 112 is located at the center within the N-well layer 111 (in a structure without the N-well layer 111, the N + diffusion layer 112 is located at the center). Looking outward from the center of symmetry, the P-type lower isolation layer 103 for the NLDMOS is located between the substrate of the NLDMOS and the N + diffused layer 112 of the NLDMOS drain, and also between the P-type base 101 and the N-type epitaxy 102. The outermost layer of the whole NLDMOS and the NJFET is an opposite-through isolation layer formed by a P-type upper isolation layer 105 and a P-type lower isolation layer 104, the opposite-through isolation layer is connected to a low potential through a contact hole connecting aluminum strip through a P + diffusion layer 106, and the contact hole is an isolation contact hole. Between the isolation contact hole and the P-well substrate of the NLDMOS is an N + diffusion layer 107 serving as a source contact hole of the NJFET, and between the source N + diffusion layer 107 of the NJFET and the N + diffusion layer 112 of the drain of the NLDMOS is a P-well 110 serving as a substrate of the NLDMOS and also serving as one gate of the NJFET. The P + diffusion layer 108 in the NLDMOS substrate serves as a substrate contact hole of the NLDMOS, the N + diffusion layer 109 in the NLDMOS substrate serves as a source of the NLDMOS, and the N + diffusion layer 109 of the source of the NLDMOS is also used as a contact hole. A grid polysilicon 130 is arranged above the edge of a source electrode of the NLDMOS and the side close to the drain region and crosses between a substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the grid polysilicon 130, one section is a thin oxide layer 129, the other section is a thick oxide layer, the thin oxide layer 129 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the size of the overlapping is determined by the lateral diffusion of an N + diffusion layer 109, and the thick oxide layer is arranged above an N-type epitaxy 102 used as the drain region of the NLDMOS. The gate polysilicon 130 is connected to the aluminum bar through the contact hole, and the gate polysilicon 130 is the gate of the NLDMOS. The N + diffusion layer 109 of the NLDMOS source region can be included in one N-diffusion layer 640 to improve the withstand voltage of the NLDMOS substrate and the source region.

Fig. 8 is yet another embodiment of a composite field effect transistor structure of the present invention. The composite field effect transistor has a circular structure with partial central symmetry, wherein the NLDMOS has complete central symmetry, and the NJFET has partial central symmetry. The composite type field effect transistor has an N-well layer 111, a P-type lower isolation layer 103, and an N-diffusion layer 640. At the center of symmetry is the drain region of the NLDMOS and NJFET, which consists of N + diffused layer 112, N-well layer 111 and N-type epitaxy 102. The N + diffusion layer 112 is spaced from the P-well 110 by a distance, the size of the distance determines the withstand voltage of the NLDMOS and the NJFET, and the N + diffusion layer 112 is located at the symmetrical center in the N-well layer 111. The P-type lower isolation layer 103 for the NLDMOS is located between the P-type substrate 101 of the NLDMOS and the N + diffusion layer 112 of the drain of the NLDMOS, and also located between the P-type substrate 101 and the N-type epitaxy 102. In the composite field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is a P-type upper isolation layer 105 and a P-type lower isolation layer 104 which form a pair of through isolation, the pair of through isolation passes through a P + diffusion layer 106, and is connected with an aluminum strip through a contact hole to be connected with a low potential, and the contact hole is an isolation contact hole. The N + diffusion layer 107 is divided into two sections of arcs in the same pattern, wherein the two sections of arcs are used as source contact holes of an NJFET between an isolation contact hole and a P-well substrate of the NLDMOS; the other arc is an N + diffusion layer 107 without a source contact hole serving as an NJFET between the isolation contact hole and the P-well substrate of the NLDMOS. The sizes of the two arcs can be changed according to the convenience and the actual requirement of the layout. Between the source N + diffused layer 107 and the NLDMOS source N + diffused layer 112 of the NJFET is a P-well 110 that serves as the substrate for the NLDMOS and one gate for the NJFET. In the substrate of the NLDMOS, a P + diffusion layer 108 for a substrate contact hole of the NLDMOS and an N + diffusion layer 109 for a source of the NLDMOS are provided, and the N + diffusion layer 109 for the source of the NLDMOS is also provided for the contact hole. The gate polysilicon 130 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS at the edge of the source of the NLDMOS and above the side close to the drain region, two sections of oxide layers are arranged below the gate polysilicon 130, one section is a thin oxide layer 129, the other section is a thick oxide layer, the thin oxide layer 129 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlap with the source of the NLDMOS, the size of the overlap is determined by the lateral diffusion of the N + diffusion layer 109, and the thick oxide layer is positioned above the N-type epitaxy 102 serving as the drain region of the NLDMOS. The gate polysilicon 130 is connected to the aluminum bar through the contact hole, and the gate polysilicon 130 is the gate of the NLDMOS. The N + diffusion layer 109 of the NLDMOS source region can be included in one N-diffusion layer 640 to improve the withstand voltage of the NLDMOS substrate and the source region.

Fig. 9 shows a schematic circuit structure of the NLDMOS and the NJFET corresponding to fig. 1 to 8. Wherein, NJFET431 and NLDMOS432 correspond to NJFET and NLDMOS in FIG. 1 respectively; the gate 433 of the NJFET431 corresponds to the isolated contact extraction electrode 113 and the P-well extraction electrode 115 in fig. 1-8, the source 434 of the NJFET431 corresponds to the source extraction electrode 114 in fig. 1-8, and the common drain 437 of the NJFET431 and the NLDMOS432 corresponds to the drain extraction 118 in fig. 1-8. The substrate 438 of the NLDMOS432 corresponds to the P-well terminal 115 in fig. 1-8, the gate 435 of the NLDMOS432 corresponds to the gate 130 of the NLDMOS in fig. 1-8, and the source 436 of the NLDMOS432 corresponds to the source 116 of the NLDMOS in fig. 1-8.

Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the field effect transistor type, the functional layer length, and the like in the embodiments of the present invention without departing from the spirit and scope of the present invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.

Claims (32)

1. A field effect transistor structure, comprising: the LDMOS comprises a transverse double-diffused metal oxide field effect transistor (LDMOS) and a Junction Field Effect Transistor (JFET), wherein the LDMOS and the JFET both have respective source regions and gate regions, and share the same drain region.

2. The structure of claim 1, wherein the LDMOS and the JFET are both enhancement mode N-type field effect transistors.

3. The structure of claim 1, wherein the NLDMOS comprises: a P-type substrate (101); an N-type epitaxy (102); and a P well (110) positioned in the N-type epitaxy (102) is used as a substrate of the NLDMOS, and a P + diffusion layer (108) on the NLDMOS substrate forms a connecting electrode as a substrate connecting end.

4. The structure of claim 1, wherein the NLDMOS comprises: a drain region formed by an N + diffusion layer (112) within the N-type epitaxy (102), wherein the N + diffusion layer (112) of the N-type epitaxy (102) forms a connection electrode as a drain of the NLDMOS; an N + diffusion layer (109) in the substrate of the NLDMOS is used as a source region of the NLDMOS, and a connecting electrode is formed through the N + diffusion layer (109) and used as a source electrode; and the gate polysilicon (130) spans the P well (110) between the source region and the drain region of the NLDMOS and intersects with the source region and the drain region of the NLDMOS to serve as the gate of the NLDMOS.

5. The structure of claim 1, wherein the NJFET comprises: taking the drain region of the NLDMOS as the drain region of the NJFET, wherein an N + diffusion layer (112) of an N-type epitaxy (102) forms a connecting electrode as the drain of the NJFET; a P-type substrate (101) and a P well (110) in the N-type epitaxy (102) are used as gate regions of the NJFETs, wherein a P + diffusion layer (108) in the P well (110) and a P + diffusion layer (106) in the P-type upper isolation layer (105) form a connecting electrode which is used as a gate of the NJFETs; and forming a connecting electrode as a source of the NJFET by using an N + diffusion layer (107) on the N-type epitaxy (102) which is opposite to the NLDMOS gate region and close to the source side.

6. The structure of claim 5, wherein the N + diffused layer (107) of the NJFET source is located between the substrate of the NLDMOS and the upper P-type isolation layer (105).

7. The structure of claim 1, characterized in that there is a P-type lower isolation layer (103) between the P-type substrate (101) and the N-type epitaxy (102) near the gate of the NLDMOS and near the side of the drain electrode.

8. The structure of claim 1, further comprising a Nwell layer (111) at the drain terminals of the NLDMOS and the NJFET.

9. The structure of claim 1, characterized in that a P-type diffusion (539) can be added between the drain terminal (118) of the N + diffusion layer (112) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion (539) can be a segment.

10. The structure of claim 1, characterized in that a P-type diffusion (539) can be added between the drain terminal (118) of the N + diffusion layer (112) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion (539) can be K-segment (K > 1).

11. The structure of claim 1, further comprising an N-diffusion layer (640) between said N + diffusion layer (109) serving as said NLDMOS source region and said P-well (110).

12. The structure of claim 1, wherein said composite field effect transistor can exhibit a circular configuration that is completely centrosymmetric or a circular configuration that is partially centrosymmetric.

13. The structure of claim 12, wherein the composite fet exhibits a circular configuration with partial centrosymmetry, the NLDMOS exhibits full centrosymmetry, and the NJFET exhibits partial centrosymmetry.

14. The structure of claim 1, wherein an upper P-type isolation layer (105) and a lower P-type isolation layer (104) are used to form an on-channel isolation around the entire LDMOS and JFET, and the LDMOS and JFET are separated from other elements on a chip on which the structure is located by the on-channel isolation.

15. A method of manufacturing a composite field effect transistor, comprising:

step (a): taking a P-type substrate of the NLDMOS as a substrate of the whole chip;

step (b): taking a P well on an N-type epitaxy as a substrate of the NLDMOS;

step (c): forming an N + diffusion layer (112), an N + diffusion layer (109), an N + diffusion layer (107), a P + diffusion layer (106) and a P + diffusion layer (108) on the N-type epitaxy of the NLDMOS;

step (d): forming a drain (437) common to the NLDMOS and the NJFET on the N-type epitaxy;

a step (e): forming a source (436) and a gate (435) of the NLDMOS on the N-type epitaxy;

step (f): forming a substrate connection (438) of the NLDMOS on the N-type epitaxy;

step (g): forming a source (434) and a gate (433) of the NJFET on the N-type epitaxy.

16. The method of claim 15, wherein the LDMOS and the JFET are both implemented using enhancement mode N-type field effect transistor material.

17. The method of claim 15, wherein in steps (a) and (b), said N + diffusion layer (109) and said P + diffusion layer (108) are contained within a P-well (110) on said N-type epitaxy.

18. The method of claim 15, wherein in steps (c) and (d), the N + diffused layer (112) on the N-type epitaxy forms a drain region common to the NLDMOS and the NJFET, and a connecting electrode is formed using the N + diffused layer (112) as a drain (437) common to the NLDMOS and the NJFET.

19. The method of claim 15, wherein in step (e), the N + diffusion layer (109) in the NLDMOS substrate is used as a source region of the NLDMOS, and a connection electrode is formed through the N + diffusion layer (109) as a source (436) of the NLDMOS.

20. The method of claim 15, wherein step (e) further comprises: and taking gate polysilicon (130) which crosses a P well (110) between a source region and a drain region of the NLDMOS and intersects with the source region and the drain region of the NLDMOS as a gate (435) of the NLDMOS.

21. The method of claim 15, wherein in step (f) the P + diffused layer (108) on the NLDMOS substrate is formed as a connecting electrode as a substrate connection terminal (438) of the NLDMOS.

22. The method of claim 15, wherein in step (g) the N + diffused layer (107) on the N-type epitaxy (102) opposite to the gate of the NLDMOS and near the source side of the NLDMOS forms a connecting electrode as the source (434) of the NJFET.

23. The method of claim 15, wherein step (g) further comprises: and forming a connecting electrode as a grid electrode (433) of the NJFET by the P + diffusion layer (108) in the P trap (110) and the P + diffusion layer (106) in the P-type upper isolation (105).

24. The method of claim 15, wherein a P-type lower isolation layer (103) is further formed between the P-type substrate (101) and the N-type epitaxy (102) near the gate of the NLDMOS and near the side of the drain electrode.

25. The method of claim 15, further comprising forming an N-well layer (111) at the drain terminals of the NLDMOS and the NJFET.

26. The method of claim 15, wherein a P-type diffusion layer (539) is further formed between said N + diffusion layer (112) of said NLDMOS drain region and said P-well substrate of said NLDMOS, and said P-type diffusion (539) is a segment.

27. The method of claim 15, wherein a P-type diffusion layer (539) is further formed between said N + diffusion layer (112) of said NLDMOS drain region and said P-well substrate of said NLDMOS, and said P-type diffusion (539) is K-segment (K > 1).

28. The method of claim 15, further comprising forming an N-diffusion layer (640) within said P-well (110), and wherein said N-diffusion layer (640) comprises said N + diffusion layer (109).

29. The method of claim 15, wherein the composite structure of the NLDMOS and the NJFET can be formed using a full-centrosymmetric circular structure.

30. The method of claim 15, wherein the composite structure of the NLDMOS and the NJFET is formed using a partially centrosymmetric circular structure.

31. The method of claim 30, wherein when the resultant structure exhibits a circular structure with partial central symmetry, the NLDMOS employs full central symmetry and the NJFET employs partial central symmetry.

32. The method of claim 15, wherein an isolation dielectric is used to form insulation between the LDMOS and the JFET electrode and to isolate the NLDMOS and the NJFET from other components on the chip on which the structure is located by a pass-through isolation formed by the P-type upper isolation (105) and the P-type lower isolation (104).

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