CN1009519B - Low frequency digital notch filter - Google Patents

Abstract

The low-frequency digital notch filter (Fig. 1) comprises an all-pass network filter (1) and a T-type filter (3), and the input node (31) is connected with the latter feedback, and is connected with the terminal output node (33), The transfer function of filter (1) is A(Z)=(Z ^-1 +K ₁ )/(1+K ₁ Z ^-1 ); the throughput and tap transfer function of filter (3) is B(Z) =[(K ₃ +K ₂ −K ₄ )Z ⁻¹ −1)/(1−K ₃ Z ⁻¹ ) and C(Z)=K ₂ Z ⁻¹ /(1−K ₃ Z ⁻¹ ), Here Z ^-1 is a unit delay operator, K ₁ ~ K ₄ are multiplier coefficients, and the filter (3) can be realized jointly by three multipliers (19, 21 and 23) and a delay unit (25).

Description

This invention relates to improvements in the design of low frequency digital notch filters and complex filters including such filters.

There are many digital signal processing (DSP) applications where one of the required functional elements is a filter that rejects any low frequency signal and possibly any DC content of that signal. A typical application of such a filter is when the digital signal being processed is a digital representation of an analog signal containing unwanted 50 Hz or 60 Hz signals. These signals will be the result of line coupling into the system from adjacent power equipment; it is often necessary to remove these unwanted signals and any DC components present.

Many different filter structures have been considered to implement such filters, especially in applications where the frequency of the signal to be cleaned is much smaller than the system sampling frequency (about 1%). When considering the suitability of such structures, many aspects of their performance must be considered. For example, in order to ensure simple and effective implementation, it is hoped that the filter has a reasonable and regular structure, and considering the price factor, the complexity should be minimal. Another requirement is that the multiplication components be kept to a minimum, and preferably the word length of the multiplier coefficients is also minimized, along with other performance considerations that lead to the need to increase the signal word length. Loop filter structures tend to amplify any layered noise such that the noise always follows the truncation process following the multiplier stage, usually with additional bits in the signal word length to compensate for this amplification so that the filter noise remains at an acceptable level. The magnitude of the signal at the internal nodes of the filter must also be considered. A filter with a high effective Q-factor will have signals at its internal nodes that are 40dB larger than the input signal at certain frequencies, even though the overall gain is 1. Increasing the signal word length also avoids clipping.

For example, imagine an application where the 50 Hz and 60 Hz signals need to be attenuated by at least 25 dB in a system with a sampling frequency of 8 Hz, and all DC components should be eliminated, while the 200 Hz signal should be attenuated by less than 0.7 dB.

A filter including biquadratic sections will be very regular and easy to implement. However such a filter selected for optimum noise and signal adding length performance includes as many as 14 9-bit multipliers and 6 delay elements. With a noise gain of 0dB at the internal nodes, the noise amplification is about 13dB. As mentioned earlier, the signal word length needs to be increased by an additional 3 bits to compensate for the filter. It should be noted, however, that many alternative structures exist, eg a filter implemented with 11 multipliers and 5 delay elements would have considerable bad signal growth characteristics.

The object of the present invention is to provide a digital filter with a reasonable and general structure, but with a simple structure and equivalent or better performance than the existing filters.

A kind of low-frequency digital notch filter is provided according to the present invention, it comprises:

an input node;

An all-pass network filter connected to the above nodes, including at least one delay unit, at least one coefficient multiplier with a multiplication coefficient of K ₁ , the transfer function A(Z) of the filter is given by the following formula:

A(Z)=(Z ^-1 +K ₁ )/(1+K ₁ Z ^-1 ) where Z ^-1 is a unit delay operator;

A T-shaped filter, whose input is connected to the output of the above-mentioned all-pass network filter, and whose output is connected with the above-mentioned input node in negative feedback, the T-shaped filter includes at least one delay unit and at least three coefficient multipliers, and its multiplication The coefficients are K ₂ , K ₃ and K ₄ , respectively. Its throughput transfer function B(Z) is given by:

B(Z)=[1+(K ₂ ·K ₄ -K ₃ )Z ^-1 ]/(1-K ₃ Z ^-1 ), and its input-to-tap transfer function C(Z) is given by :

C(Z)=K ₂ Z ^-1 /(1-K ₃ Z ^-1 ); and

a terminal output node connected to the output of the above-mentioned T-shaped loop filter and connected to the above-mentioned input node.

The above notch filter can be connected in series with a DC suppression filter according to the application.

The accompanying drawings in this manual include:

Fig. 1 is a circuit diagram of a low-frequency digital notch filter implemented according to the present invention;

Fig. 2, is the circuit diagram of the direct current suppressing filter used in combination with the notch filter shown in Fig. 1;

Figure 3 is a graph illustrating a typical gain frequency response and the frequency response achievable using the combination of filters shown in Figures 1 and 2 above.

Embodiments of the present invention will now be described by way of example with reference to the above-mentioned drawings.

A low-frequency notch filter component of a composite band-stop filter is shown in Figure 1, which mainly includes two sub-filters, namely an all-pass network filter 1 and a T-type filter 3.

The all-pass network filter 1 includes a delay unit 5 and a coefficient multiplier 7 . The transfer function A(Z) of this filter is given by:

A(Z)=(Z ⁻¹ +K ₁ )/(1+K ₁ Z ⁻¹ ), where K ₁ is the coefficient value of the multiplier 7 . Filters can be implemented by standard loop structures - eg, "Digital Signal Processing Systems for Efficient Interpolation and Decimation" by RIA. Valerzuela and AG Conslantinides. The structure described in the article [see IEE Transactions Volume 130 Pt.G No.6 (1983.12) page 232], the shown all-pass network filter 1 includes a branch between the common input delay unit 5 and the multiplier 7 The road nodes 9 and 11 also include an output node 13 connected to the outputs of the delay unit 5 and the multiplier 7 . Between the output of the delay unit 5 and the output of the multiplier 7, and between the output of the multiplier 7 and the delay unit 5, there are cross-connect lines 15 and 17 via branch nodes 11 and 9, respectively.

The T-shaped filter 3 is connected to the output node 13 of the all-pass network filter 1, and the filter includes three multipliers 19, 21 and 23, whose multiplication coefficients are K ₂ , K ₃ and K ₄ respectively. The transfer functions B(Z) and C(Z) of filter 3 are expressed by the following two equations:

B(Z)=[(K ₃ +K ₂ ·K ₄ )Z ^-1 -1]/(1-K ₃ Z ^-1 ) (input to output); and C(Z)=K ₂ Z ^-1 / (1-K ₃ Z ^-1 ) (input to tap).

In the embodiment of this filter 3 as shown in Figure 1, the multiplier 19, the branch node 27, the delay unit 25 and the multiplier 21 are connected in series, and the delay unit 25 is shunted by the multiplier 23 through the branch node 27, The output of the multiplier 21 is connected to an output node 29, which is also connected to the input of the T-filter for subtraction from the input signal.

Adding an input node 31 and an output node 33 completes the low frequency notch filter block. The feedback signal is taken from a point on the signal path between delay element 25 and multiplier 21 of the T-filter and subtracted from the input at input node 31 . The output signal from node 31 is supplied in parallel to the input and output nodes 33 of an all-pass network filter 33 and summed at node 33 with the output signal of the T-filter 3 .

The low frequency notch filter block shown in FIG. 1 also includes a fifth multiplier 35 connected at the output of output node 33 . The multiplication coefficient K ₅ =1/2 of this multiplier.

The DC rejection filter components of the composite filter are shown in Figure 2. This filter section is connected in series with the above-mentioned low frequency notch filter section. It basically comprises an all-pass network filter 1 and an output node 37, the input signal of which part is supplied to the network filter 1 and the output node 37 in parallel. At node 37 the input signal is subtracted from the output signal of the network filter 1, which may have the same structure as the corresponding filter previously described with reference to FIG. But here the multiplication coefficient of the multiplier 7 is K ₆ . In the DC suppression filter shown in FIG. 2 , the output node 37 is connected to the seventh multiplier 39 . The multiplication coefficient K ₇ of the multiplier 39 is 1/2. This DC rejection filter selection has better performance than its biquad component counterpart and is very similar in form to a notch filter, making it possible to implement it more efficiently.

A typical performance illustration is shown in Figure 3. The band stop frequency is 50 Hz, and a horizontal response is obtained for frequencies above 200 Hz. Suitable values for the coefficients K ₁ to K ₇ are given in Table 1 below

Table 1

coefficient value

K ₁ - (1-3/16)

K ₂ 1/16

K ₃ 1-1/128

K ₄ 1/4

K ₅ 1/2

K ₆ - (1-1/32)

K ₇ 1/2

It can be seen from Figure 3 that the required performance can be easily obtained when using the coefficient values in Table 1. Figure 3 illustrates DC rejection, with a low frequency bandstop of 50 Hz and a nearly flat response at frequencies above 200 Hz.

The table below gives the performance of the combination of the 2 components shown in Figure 1 and Figure 2.

Table 2

Structure: Reasonable and regular, using a simple all-pass network as a filter

basic components of the .

Composition: 7 multipliers, 3 delay units.

Multiplier: 7 bits, but the multiplication coefficient of 4 of the 7 multipliers is only

Only powers of base 2, but can be implemented very simply.

Noise amplification: about 10dB.

Maximum noise gain for internal nodes: 3dB

Signal word length: 3 additional bits are required to compensate the filter

It can be seen that the above structure provides many improvements over the more general structure at the expense of a less regular structure. For a given signal word length, it manages to obtain performance similar to that of previously studied biquadratic partial filters, but only uses half the number of storage units and half the number of multipliers, and in many cases the multiplication coefficients are simple, For example 1/2 etc.

Coefficients K ₁ -K ₇ can be varied to meet other application requirements, in particular changing the frequency of the notch filter relative to the sampling frequency. One of the advantages of the above structure is that many multiplications can be easily implemented, even using cascades of divide-by-2, even when the coefficients are changed to meet different requirements. Therefore, referring to Figures 1 and 2, the coefficients _K5 and _K7 are always chosen to be equal to 1/2. K 5 and K 4 can usually be arranged if both K ₂ and K ₄ are not powers of 1/2, and the coefficient K ₃ has _the following relationship K ₃ =1-( ₂ ·K ₂ K ₄ ) with the coefficients K 2 and K ₄ One of K ₇ has a value of 1/2.

Claims (8)

1, a kind of low-frequency digital notch filter, comprising: an input node, an all-pass network filter, and an output node, it is characterized in that, described all-pass network filter comprises: A first filter stage with an input and an output, the input is connected to the above-mentioned input node, the first filter stage contains at least one first delay unit and at least one first coefficient multiplier whose multiplication coefficient is K ₁ , the first The delay unit and the first coefficient multiplier are connected to each other such that the transfer function A(Z) of the first filter stage is A(Z)=(Z ^-1 +K ₁ )/(1+K ₁ Z ^-1 ); A second filter stage with input and output, the input of the second filter stage is connected to the output of the first filter stage, the second filter stage contains a second delay unit and three multiplication coefficients are K ₂ , K ₃ and a second coefficient multiplier of K ₄ , the second delay unit and the second coefficient multiplier are connected to each other such that the transfer function B(Z) of the second filter stage is B(Z)=[(K ₃ +K ₂ ·K ₄ )Z ^-1 -1]/(1-K ₃ Z ^-1 ); a filter output node connected to the output of the second filter stage; and A feedforward line connected between said input node and output node is used to sum the filter input and the output of the second filter stage to provide a notch characteristic at the desired frequency. 2. The notch filter as claimed in claim 1, characterized in that there is a branch node at the output of the second delay unit, so that the transfer function C (Z ) is given by: C(Z)＝K ₂ Z ^-1 /(1-K ₃ Z ^-1 ); And, a feedback line is connected between the branch node and the input node. 3. The notch filter according to claim 1, wherein said T-shaped filter comprises three multipliers and a delay unit, wherein two multipliers are respectively connected on each side of the delay unit , and the other one is shunted across the delay unit through a branch node, and also includes an output node, so that the output signal of the multiplier subtracts the signal introduced by the common input. 4. The notch filter according to claim 1, characterized in that the value of the coefficient K ₃ related to the coefficients K ₂ and K ₄ is: K ₃ =1-(2K ₂ K ₄ ), and the coefficient K ₂ and _K4 are both powers of 1/2. 5. The notch filter according to claim 1, further comprising a fifth multiplier connected to the output node with a multiplication coefficient of _K5 , which is a multiplier divided by 2. 6. A compound filter composed of the notch filter according to claim 1, characterized in that it is composed of a DC suppression filter connected in series with it. 7. The composite filter according to claim 6, wherein said DC suppression filter comprises: a public input; an all-pass network filter stage of the same structure as said first filter stage; and A node that connects the common input and the output of the aforementioned all-pass network filter such that the input signal is subtracted from the output signal of the filter. 8. A composite filter as claimed in claim 6, characterized in that a seventh multiplier, which is a divide-by-two multiplier, is connected at the output of said DC rejection filter.

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