CN1008589B - Digital luminance processing systems - Google Patents

Abstract

The digital brightness treatment circuit comprises first cosine filter, second low pass filter and the 3rd filter (it is little that it will compare low cut to the decay of the high frequency) coupled in series of it and parallel connection.The 3rd filter comprises the variable proportion device.The output of second filter is connected to an input of synthesizer, and the output of the 3rd filter is connected to second input of synthesizer.Synthesizer is output as the output channel of treatment circuit.

Description

Digital luminance processing systems

The invention relates to and handle the video luminance signal component, particularly about setting up the device of the luminance component amplitude-frequency response of wishing, such as in digital television receiver.In order to improve the acutance and the resolution detail of image, wish to improve the transient response of luminance channel by the high frequency response that improves luminance channel.

Improve the steepness of amplitude transition in the vision signal, can be in the subjective response that improves video signal processing system; And preshoot of the generation of the moment before transition, and, also can improve response in the later upper punch of moment generation of transition.People also know, utilizing a kind of device that each terminal (being commonly referred to tap) in delay line or similar device is gone up the time delayed signal that produces combines in a predefined manner, can form desirable amplitude-frequency and (or) phase-frequency characteristic, and do not introduce phase nonlinear or phase distortion basically.This device is sometimes referred to as " transversal equalizer " or " transversal filter ", has carried out general narration in the number of patent application № of USPO 2,263,376 (A.D. Bu Lumeiyin people's such as (A.D.Blumlein)) file.

In television system or handle composite signal (for example to provide the prearranged signal transmission characteristic, the signal of the selected frequency of enhancing) in the similar system, hope comprises peaking circuit in luminance channel, this peaking circuit can be adaptive to rapidly the control of luminance signal component HFS in the vision signal (for example, enhancing or peaking relatively).For example, wish for the amplitude of the higher part luminance signal of some frequency, to carry out controllable enhancing according to the quality that receives TV signal.

Fig. 1 represents a transfer function, when being used for luminance signal, can making and reappear image and obtain very desirable improvement subjective.The present invention directly relates to relevant device, can be used for this transfer function of luminance channel in the analog video digitizer signal processing system usually.For digital television receiver, in order to provide cost low television receiver, this device must be realized with minimum parts.

In order to implement even a kind of simple numerical processing capacity all needs a large amount of devices.For example:, just need the transistor more than 200 for two 8 signal plus.Be readily appreciated that, in that to be easy to management and cost aspect the number of devices low, realize the necessary processing capacity of digital hardware in the television system, each functional part must be designed to suitable with the ideal response characteristic simple structure.According to this restrictive requirement, thereby developed the peaking circuit that only needs a multiplier circuit in a preferred embodiment.

The digital brightness treatment circuit that device according to the present invention is realized by a finite impulse response (FIR) (FIR) filter is formed, and this filter comprises the first cosine FIR filter, the second and the 3rd FIR filter coupled in series of it and parallel connection.The 2nd FIR filter produces low pass filter response.The 3rd FIR filter for the decay of HFS less than decay for low frequency part.The 3rd FIR filter comprises the variable proportion device, and an input channel of its output channel and synthesizer links.The output channel of the 2nd FIR filter is connected to second input channel of synthesizer, and the output channel of synthesizer is exactly the output channel of treatment circuit.

Can be according to device of the present invention with being peaking circuit in the digital video information processor.Can be added to proportionality coefficient in the variable proportion device by change, regulate the high frequency response of peaking circuit.Realize whole filter weight elements with displacement sampling separately, make needed filter hardware minimize.

Accompanying drawing is:

Fig. 1 is the amplitude-frequency response of the peaking of video luminance signal component in the television receiver, and this receiver reappears image subjective the enhancing;

Fig. 2 is the part block diagram that contains the digital television receiver of digital peaking circuit;

Fig. 3 and Fig. 6 are the logic diagram of the FIR filter circuit of general simulation drawing 1 transmission response curve;

Fig. 4 is the block diagram of variable proportion circuit, and this circuit can be used for the circuit of Fig. 3 and Fig. 6; And

Fig. 5 is the relative amplitude-frequency characteristic of the transfer function that presented of Fig. 3 circuit, wherein the COEFFICIENT K of variable proportion circuit equal, less than and greater than 1.

Fig. 7 is the block diagram of the coring circuit of simplification.

In the accompanying drawings, fine rule represent simulation or one-bit digital (such as: the path of signal clock), thick line represent that multistation digital signal is (such as the signal path binary signal of pulse code modulation).

For the transition of vertical line in subjective enhancing displayed image, in television receiver, used the brightness peaking circuit.Represent steeper jump signal, generally comprise high frequency component signal.With respect to low frequency component, the amplitude response of the signal high fdrequency component that highlights can strengthen transition selectively.Yet the peaking that must be noted that the higher-frequency that guarantees luminance signal does not cause the ring of these high fdrequency components.Therefore, whole peaking response must be roll-offed down gradually in that frequency spectrum is high-end, also will guarantee to have in the frequency range of audio signal component the decay of high value.In addition, it would be desirable that the peaking response has linear phase characteristic.It has been found that in the past that when producing the linear phase component the represented general frequency response curve of Fig. 1 produces desirable peaking characteristic.

Fig. 2 is the part block diagram of digital television receiver, represents main signal processing circuit, comprising the brightness peaking circuit.In Fig. 2, receive broadcast television signal, and be added to traditional tuner and intermediate frequency (IF) circuit 12 by antenna 10.Baseband analog composite video signal from circuit 12 is added to the input of analog-digital converter (ADC) 14, and this transducer 14 to be taking a sample to signal such as the speed of four times of color subcarriers, and produces Analog signals'digital and represent.Control ADC14 by the sampled signal that clock generator 16 produces, this clock generator 16 can be the phase-locked loop circuit for colour burst reference component sensitivity in the digitized composite video signal.Comb filter 18 is delivered in sampling output from ADC14, and this filter is isolated the brightness and the chromatic component of composite video signal selectively.Chromatic component is delivered to chroma processing circuitry 20, and this circuit comprises: gain control function, the decoding circuit of filter circuit and color mixture signal is suitably adjusted carrier chrominance signal for use in colour matrix translation circuit 26 here.

Luminance component from comb filter 18 is added to brightness processed circuit 22, and this circuit comprises: brilliance control and vertical definition enhancement function etc.From brightness processed circuit 22 adjusted luminance signals, be added to brightness peaking circuit 24, highlight the selectively amplitude characteristic of signal higher-frequency component of this circuit.Luminance signal from brightness peaking circuit 24 peaking is added to colour matrix translation circuit 26, and there with the carrier chrominance signal appropriate combination of handling, the colour signal of red in order to produce (R), green (G) and blue (B) is used to drive picture tube.

Fig. 3 is a peaking circuit, comprises delay-level, adder and multiplier unit 47.The pattern of multiplier unit 47 is: it comes the added signal of scale with a constant coefficients.The pattern that multiplier 47 is preferably such, promptly its proportionality coefficient K is variable on electricity, is controlled by the control signal that is added to its control input end 50, make the peaking function can be adaptive to add the state of brightness signal.Ideal situation is that proportionality coefficient K is a linear change, so that the adaptive range of a broad is provided.

Brightness sampling among Fig. 3 is sent to input channel 30, and the sampling of peaking is provided by the output channel 49 of adder 48.Luminance sampling signal is coupled to the input channel of delay element 31, and this passage is input to adder circuit 51 serially with it.The brightness sampling also is added to second input channel of adder circuit 51 simultaneously.Constituted a FIR filter by delay element 31 and adder circuit 51, the transfer function that adder 51 outputs are presented is a cosine response with respect to the input sampling that is added to passage 30.When representing with conversion symbol " Z ", transfer function is described by equation (1):

S51/SIN＝1+Z ^-1（1）

Wherein, S51 and SIN are respectively the value of sample of signal in the output channel of adder 51 and the input channel 30.

Sampling output from adder 51 is added to second filter (it comprises circuit element 32,33,34,35,38,41 and 42); And be added to the 3rd filter (it comprises circuit element 33,35,36,37,39,40,43,44,45,46 and 47). Circuit element 33,35,42,43 and 45 is delay elements, and this delay element is with a sampling period inhibit signal sampling; And be for example with the latch of sampling rate clock synchronization.Circuit element 34,36 and 39 is for taking advantage of 2 devices.Suppose that sampling is the binary code of n digit pulse coded modulation (PCM), then taking advantage of 2 devices can be wired circuit, this circuit changes or moves the significance bit in everybody locational each sampling, promptly is moved to the left a position (when the leftmost bit of PCM sign indicating number is highest significant position). Circuit element 32,37,38 and 40 is binary adders; And circuit element 44 and 46 is the binary subtracters that are designed to be suitable for signal format (for example, 2 complement).Circuit element 41 is ratio circuits, and this circuit removes sampling with 4.For binary system PCM sampling, circuit element 41 can be a wired circuit, the significance bit of this each sampling position of circuit change, and two positions promptly move right.

Second filter provides the general lowpass response with fixed gain coefficient in interested frequency range.The 3rd filter provides high frequency response or band-pass response with variable gain factor in interested frequency range, promptly the 3rd filter is greater than decay to the higher-frequency luminance signal component to the decay than the low-frequency brightness signal component.Carrying out linear, additive from the output signal of second filter and the 3rd filter, to produce the luminance signal of peaking, wherein second filter provides than the low-frequency brightness component, and the 3rd filter provides the higher-frequency luminance component.Because the 3rd filter has variable gain coefficient, so the amplitude of luminance signal higher-frequency component can be determined ratio with respect to low frequency component, to produce optimal complex response.

In the illustrated circuit of Fig. 3, the upper signal path is second filter, and the bottom signal path is the 3rd filter.The upper signal path at first is described, the sampled signal from adder 51 is added to the input channel of adder circuit 32 and the input channel of delay element 33.Output sampling from delay element 33 is added to the input channel of delay element 35 and takes advantage of 2 circuit 34.The sampling of the weighting that comes involution 2 circuit 34 is added to second input channel of adder 32, the output of this adder is connected to first input channel of adder 38.Second input channel that is added to adder 38 from the output sampling of delay element 35.Output sampling from adder 38 is removed with 4 in element 41.Sampling from element 41 is added to delay element 42, and this element postpones a sampling period to sampling synthetic and weighting.When representing with conversion symbol " Z ", the transfer function that element provided between the output channel of adder 51 and delay element 42 is described by equation (2):

S42/S51＝1/4（1+2Z ^-1+Z ^-2）Z ^-1（2）

This is generally lowpass response corresponding to the transfer function of second filter.Whole transfer function is described by following formula between the output channel of input channel 30 and delay element 42:

S42/SIN＝1/4（Z ^-1+3Z ^-2+3Z ^-3+Z ^-4） （3）

Sampling from adder 51 output channels is added to takes advantage of 2 devices 36, this takes advantage of the output channel of 2 devices to be connected to first input channel of adder 37.Sampling from delay element 33 is connected to second input channel of adder 37, and the output of this adder 37 is connected to first input channel of adder 40.Sampling from delay element 35 be multiply by 2 in element 39, deliver to second input channel of adder 40 subsequently.The transfer function that element provided between adder 51 and adder 40 output channels is provided by following formula:

S40/S51＝2+Z ^-1+2Z ^-2（4）

This is generally lowpass response.

Sampling from adder 40 is added to delay element 43, and delivers to subtraction circuit 44 as minuend.Output sampling from delay element 43 is delivered to subtraction circuit 44 as subtrahend.The transfer function that element provided between adder 40 and subtraction circuit 44 output channels is provided by following formula:

S44/S40＝1-Z ^-1（5）

Sampling from subtraction circuit 44 is added to the input channel of delay element 45, and delivers to subtraction circuit 46 as subtrahend.The output sampling that has postponed from delay element 45 is delivered to subtraction circuit 46 as minuend.The transfer function that circuit element provided between the output channel of the output of subtraction circuit 44 and subtraction circuit 46 is provided by following formula:

S46/S44＝Z ^-1-1 （6）

The input channel that is added to variable gain multiplier 47 from the output sampling of subtraction circuit 46, this multiplier 47 multiply by variable coefficient K to sampling.Composite transfer function between the output channel of input channel 30 and multiplier 47 is provided by following formula:

S47/SIN=-2K+KZ ^-1+ KZ ^-2+ KZ ^-3+ KZ ^-4-2KZ ^-5(7) this is generally band-pass response.

Synthetic in adder 48 the sampling from delay element 42 and variable gain multiplier 47, this adder provides from the output of peaking circuit in output channel 49 and takes a sample.The transfer function T(Z of peaking circuit) provide by following formula:

T（Z）＝-2K+（K+ 1/4 ）Z ^-1+（K+ 3/4 ）Z ^-2+（K+ 3/4 ）Z ^-3+（K+ 1/4 ）Z ^-4-2KZ ^-5（8）

The transfer function of peaking circuit is done bright in general by Fig. 5.It should be noted that response generally is smooth near direct current, rise then, is peak value between the 2.2-2.5 megahertz, roll-offs then, passes through zero near 4.05 megahertzes.This response curve has approximately at approximate 4.2 megahertz places-minimum value of 40dB.Response curve rises once more then, and is peak value near 5.7 megahertzes.And this back peak value is that we are undesirable.Yet, can suppose that pre-filtering before analog-to-digital conversion will eliminate the whole signal components in the frequency spectrum in this section substantially.

Solid-line curve among Fig. 5 represents that COEFFICIENT K is 1 response curve.Fig. 5 dotted line and dotted line are represented respectively greater than 1 or less than 1 response curve.COEFFICIENT K is 0 o'clock, and the high frequency luminance component will significantly be decayed with respect to DC response.So suitably select COEFFICIENT K, luminance signal can be by peaking or depeaking.(annotate: the response curve that Fig. 5 is illustrated, suppose sampling rate 4 times for color subcarrier in (U.S.) National Television System Committee (NTSC) composite colour television signal.〕

Fig. 4 is the logic diagram of variable multiplier unit circuit, and this multiplier is realized the function of element 47 among Fig. 3.This circuit is programmable displacement-addition type weighting circuit, can sampling be weighted usage factor, and this coefficient is the summation of twice power or is the summation of twice power inverse.Illustrated circuit only comprises 4 shift units and 3 adders, so that produce 16 grades of linear responses for 4 control signals.Its function of illustrated circuit is to multiply by COEFFICIENT K, and K equals 4 binary control signal C ₁C ₂C ₃C ₄Corresponding 10 system numerical value 1/8th.For example, suppose C ₁C ₂C ₃C ₄Be 0101, this equals 5 of 10 systems, and then COEFFICIENT K is 5/8.

The signal of being taken advantage of is delivered to input channel 80.Sampled signal is delivered to shift unit 60-63, and this shift unit is 0,1,2 and 3 the significance bit position that moves right, the position of added PCM sampling, and this corresponds respectively to ratio is 1,1/2,1/4 and 1/8.The symbol bit line connects as 2 complement, and this line requires to vacate more significance bit in the PCM signal that has been shifted, duplicates sign bit on this position.Being shifted or determining that the sampling of ratio is added to respectively by control line C ₁, C ₂, C ₃And C ₄The gate circuit 64-67 of control.When being logical zero on the control line, the sampling of corresponding gate circuit output 0 value.When being logical one on the control line, corresponding gate circuit is by the proportional sampling of its input.Ratio output sampling or the addition in adder tree mesh network (it comprises adder circuit 68,69 and 70) of 0 value, take a sample so that in output channel 71, produce with the input of proportionality coefficient K weighting from gate circuit 64-67.

Get back to C ₁C ₂C ₃C ₄Equal 0101 and input be sampled as the example of 10 hex value 16,10 hex value of being delivered to gate circuit 64-67 by shift unit 60-63 are respectively 16,8,4 and 2.Gate circuit 64 and 66 response logic " 0 " control signal, the output valve that generation equals 0; And gate circuit 65 and 67 response logic " 1 " control signal, will produce output valve 8 and 2 respectively, itself and be 10 hex value 10.The binary value of control signal 0101 equals 5 of 10 systems, so COEFFICIENT K is 5/8.16 5/8ths equal 10, this is the output valve that adder tree produces at output 71.

Circuit in can expander graphs 4 to be producing bigger multiplication factor, and its method can be with comprising the additional shift device parallel with shift unit 60-63, and corresponding gate circuit and adder; Perhaps make shift unit able to programme, and do not adopt hardware.

According to the technology that realizes that sort circuit adopted, must adopt pipelining to come the difference of adaptive circuit on delaying time, for example, during two adder circuit coupled in series in Fig. 3 and Fig. 4.The people who is familiar with prior art will admit these conditions, come design circuit according to these conditions.

The peaking circuit of Fig. 6 between two transfer functions, changing.One of them transfer function is similar to the transfer function of Fig. 3 device.Second transfer function generally is to be zero broadband response at 7.2 megahertzes (for the sampling rate of NTSC).Moreover, comprise adaptive coring circuit in the Circuits System of Fig. 6.Among Fig. 6, be marked with Fig. 3 in each element of each element duplicate numbers, carry out identical functions.

Element 82 and 81 is formed self adaptation coring circuit, can suppose that for large-signal this circuit can the unit's of providing transfer function, does not promptly exert an influence for signal.Suppose to be exactly this situation, transfer function and Fig. 3 circuit between input channel 30 and output channel 49 (when the contact of switch 83 is connected to terminal A, A ' time) in full accord.In this circuit, the efficiency of element in switch 83 left sides is higher slightly than circuit corresponding among Fig. 3, and can show that it can carry out identical functions.

Consider two situations that contact is connected with terminal B of switch 83 below.Can show the transfer function F between input channel 30 and output channel 49 in this case at an easy rate _B, describe by following formula:

-F _B＝-KZ ^-1+（K+1）Z ^-2+（K+1）Z ^-3-KZ ^-4（9）

This is generally the frequency response of cosine shape, is being null value near 7.2 megahertz places.For example, when the horizontal definition that requires to reappear maximum possible when videotex data (for example), foregoing circuit is worked in this manner.Switch 83 can be manual operation switch or electronic switching device, for example, and to signal spectrum content devices sensitive at that time.Function F _BIt also is the function of peaking.

The peaking function can be by the enhancing signal frequency spectrum the higher-frequency component, and the higher-frequency component that has strengthened returned and realize than the method for low frequency component addition.Yet in vision signal, the higher-frequency component is with respect to be subjected to typical significantly decay than low frequency component.This decay is because the bandwidth of video signal of broadcasting is not enough.Consequently the higher-frequency component has relatively poor signal to noise ratio, is subjected to the influence from the analog-digital conversion process quantizing noise especially easily.When a little less than the received signal, the signal to noise ratio of higher-frequency component will obviously reduce, and the peaking circuit power cut-off, the noise that has strengthened be turned back in the input signal go.This unfavorable result can be by preventing the signal coring that has strengthened coring is to carry out before the signal that has strengthened is turned back to other frequency component.

Coring is a kind of signal processing operations, in this operation low level signal change is removed from signal, to improve whole signal to noise ratio.Fixedly coring (removing being no more than the fixedly low level signal change of threshold level) generally is not suitable for television receiver, because spectators are to coming across the noise (being the bright spot in the dark background) in the dark scape, noise (being the dim spot in the bright background) in the bright scape is easier to be discovered out than appearing at.So,, provide high relatively coring threshold preferably for low brightness signal level or darker scape; And, provide low relatively coring threshold for brighter scape.

Referring again to Fig. 6, element 82 is the coring circuit, and Fig. 7 illustrates an example of coring circuit.Element 81 is the memory element to the programming of coring circuit 82 output certain threshold level.Luminance signal from multiplier 47 is added to the signal input channel of coring element 83, there it and threshold value from memory element 81 is compared.If signal value is greater than threshold value, just that signal passes to adder 48.If signal value is less than threshold value, coring element 83 just outputs to adder 48 to a predetermined value (for example, zero).The signal of access thresholds memory element 81 is a low-frequency brightness, generally the average image brightness of its representative.Through delay element 78 and with the joining adder 79 of adder 77 circuit output channels, can obtain low-frequency brightness.Filter transfer function S79/S30(is provided by the element that connects between the output channel of signal input channel 30 and adder 79), provide by following formula:

S79/S30＝（1+Z ^-1）（1+Z ^-2） ²（10）

This filter function is a lowpass response, and this filter was to reach purpose of design near 1.2 megahertzes in its 3dB o'clock, and additional minimum hardware is principle.

From the sample of signal of adder 79 divided by coefficient 64, for example before the address input channel of they being delivered to memory element 81,6 effective bit positions move to right.This signal is carried out division arithmetic two reasons, and at first, threshold value does not need to have very high resolving power, promptly for the luminance signal of 7 positions of putting in marks, has 32 different threshold values just enough.Secondly, if the input on passage 30 is sampled as 8 bit wides, just and by being increased to 11 bit wides after adder 51,77 and 79.Position for specified coring threshold lower-order is insignificant, and does not therefore include the control information of usefulness.Division can be carried out before delay element 78 and adder 79, with the needed hardware number of further minimizing.Another kind of scheme is, the division separated into two parts is carried out, and a part is before delay element 78, and another part is after adder 79.For example, can before element 78, carry out 4 gts, after element 79, carry out two gts thereupon.So just, make the size of adder 79 be reduced to 6 device, can save hardware significantly from 10 device.Last this example has proposed saving good compromise between hardware and the rounding error, and this rounding error causes owing to remove to do division (and truncation) with displacement mode.

Fig. 7 has represented that can be used as a coring circuit of implementing element 82 among Fig. 6.This circuit comprises digital comparator 130, being added on 130 from the input signal of multiplier 47 with from the threshold value of memory 81.If when surpassing threshold value from the sample size of multiplier 47, the control signal (GS) of comparator 130 output logic high level then, otherwise comparator 130 is sent logic low at the GS output.Control signal GS is added to each first input end parallel and gate array 122-128 respectively.Each second input that is added to AND circuit 122-128 from each of multiplier 47 samples of signal respectively.When control signal GS is high level, input signal is passed to coring circuit output channel 200 unchangeably with door 122-128.Otherwise, when control signal GS is low level, provide logic low to output channel 200 with door 122-128.Notice that comparator 130 can be the window comparator, and though input signal greater than added threshold value still less than the threshold value of bearing, 130 all provide the output signal of logic high; Otherwise, the output that produces logic low.

Claims (10)

1, a kind of treatment circuit that is used for the fast acquisition of digital video luminance signal comprises a digital video brightness signal source, it is characterized in that:

Have one and the joining input channel in described video brightness signal source (30), and one first finite impulse response (FIR) (FIR) filter (31,51) with an output channel, a FIR filter presents the cosine transfer function;

Has a joining input channel of the output channel with a described FIR filter, and have one the 2nd FIR filter (32,33,34,35,38,41,42) of an output channel, the 2nd FIR filter presents general low pass frequency response;

Have one and the joining input channel of a described FIR filter output channel, and has an output channel, also comprise one the 3rd FIR filter (33,35,36,37,39,40,43,44,45,46,47) in response to a variable proportion circuit 47 of gain control signal (50), described the 3rd FIR filter presents a frequency response, and this frequency response will be compared to relative low-frequency spectra littler of luminance signal for the decay of the relative high frequency frequency spectrum of luminance signal; And

With described second and the joining synthesizer of output channel (48) of the 3rd FIR filter, be used to synthesize the sample of signal of the filtering that is provided, described synthetic filtering sampling (49) is corresponding to the digital video luminance signal of having handled.

2, according to the circuit in the claim 1, it is characterized in that:

A described FIR filter (31,35) presents transfer function f ₁=1+Z ^-1, wherein the meaning of Z is exactly traditional Z conversion;

Described the 2nd FIR filter (32,33,34,35,38,41,42) presents transfer function f ₂=1/4(Z ^-1+ 2Z ^-2+ Z ^-3); And

Described the 3rd FIR filter (33,35,36,37,39,40,43,44,45,46,47) presents transfer function f ₃=K(-2+3Z ^-1-2Z ^-2+ 3Z ^-3-2Z ^-4), wherein, K is a constant.

3, according to the circuit in the claim 2, it is characterized in that: a described FIR filter (31,51) comprises having one and the joining input channel in described luminance signal source (30), and the delay element (31) with an output channel; This filter also comprises having the adder circuit (51) that first and second input channels are connected to the input and output passage of described delay element respectively, and described adder circuit has an output channel corresponding to an above-mentioned FIR filter output channel.

4, according to the circuit in the claim 2, it is characterized in that: the 2nd FIR filter (32,33,34,35,38,41,42) comprising:

Have first (33) and the delay element of second (35) coupled in series of output channel separately, first delay element has an input channel that is connected to a FIR filter output channel;

Be connected to first weighting device (34) of first delay element output channel, be used for the sample of signal from described first delay element is weighted;

Be connected to the input channel of first delay element, the output channel of second delay element and the device of described first weighting device (32,38) are used for the synthetic sample of signal that obtains there;

Be connected to second weighting device (41) of the device that is used for the composite signal sampling, be used for synthetic sample of signal is weighted; And

Have one and the joining input channel of second weighting device, and have one the 3rd delay element (42) corresponding to the output channel of the 2nd FIR filter output channel.

5, according to the circuit in the claim 2, it is characterized in that: the 3rd FIR filter (33,35,36,37,39,40,43,44,45,46,47) comprising:

Have first (33) and the delay element of second (35) coupled in series of output channel separately, described first delay element has an input channel that is connected to a described FIR filter output channel;

Be connected to first (36) and second (39) weighting circuit of first delay element input channel and second delay element output channel respectively, be used for the sample of signal that is added to respectively here is weighted;

Be connected to first, the device (37,40) of second weighting circuit and first delay element output channel, be used for synthetic sample of signal from described weighting circuit and described first delay element;

First (44) and second (46) subtraction circuit;

Have an output channel, and have to be connected to and be used for one the 3rd delay element (43) of an input channel of described device of composite signal sampling;

The input and output passage of described the 3rd delay element is connected to the minuend of described first subtraction circuit and each device of subtrahend input channel respectively;

Have an input channel that is connected to described first subtraction circuit, and have one the 4th delay element (45) of an output channel;

The input and output passage of described the 4th delay element is connected to the subtrahend of described second subtraction circuit and each device of minuend input channel respectively; And

Described variable proportion circuit comprises having an input channel that is connected to second subtraction circuit, and has the multiplier circuit (47) corresponding to an output channel of described third digit treatment circuit output channel.

6,, it is characterized in that multiplier circuit (47) comprising according to the circuit in the claim 5:

Have the data input channel separately that is connected to described multiplier input channel (80), and have control input end (C separately ₁-C ₄) a plurality of control weighting circuits (60,64,61,65,62,66,63,67); Described each control weighting circuit when being added to that the signal of control end is first kind of logic state separately, provides the reproducing signals of weighting of sample of signal on output channel separately, this sample of signal is added to described input channel; When being added to that the signal of control end is second kind of logic state separately, the sampling of output null value; And described each control weighting circuit comes weighting input sampling with the value that reduces by turn; And

Device (68,69,70) synthesizes the output sampling from described whole control weighting circuits, duplicates with the ratio that produces sampling, and this sampling is added on the described multiplier circuit.

7,, it is characterized in that each circuit in described a plurality of control weighting circuit comprises according to the circuit in the claim 6:

N+1 input with door (64-67), described several sample of signal inputs of being input as, and n+1 imported the control end (C that is coupled to separately ₁-C ₄); And

Shift unit (60-63) is used for changing the significance bit position of sampling, described shift unit be connected in and several sample of signal inputs and multiplier input channel (80) of door between.

8, according to the circuit in the claim 1, it is characterized in that: described synthesizer (48) is connected to the device that described the 3rd FIR filter (33,35,36,37,39,40,43,44,45,46,47) gets on comprises:

A coring circuit with a threshold value input channel, described coring circuit have a signalling channel that is connected between described the 3rd FIR filter and the described synthesizer;

Numerical control device (81) with input channel that is connected to described the 3rd FIR filter output channel is used for sending digital threshold and it is added to the threshold value input channel of described coring circuit; And

Has an input channel that is connected to a described FIR filter (31,51) output channel, and have one the 4th FIR filter (78,79,80) of an output channel that is connected to described numerical control device, described the 4th FIR filter presents a low pass frequency response.

9, the circuit in according to Claim 8 is characterized in that: the transfer function f of described the 4th FIR filter ₄Provide by following formula:

f ₄＝W（1+Z ^-2） ²

Wherein, W is a proportionality coefficient.

10, the circuit in according to Claim 8 is characterized in that:

Described numerical control device (81) comprises having a data output channel that is connected to described threshold value input channel, and the storage device with an address input channel, the programming of described storage device so that threshold value corresponding to adding address signal is provided; And

The output channel of described the 4th FIR filter is connected to described address input channel.

11, the circuit in according to Claim 8 is characterized in that:

Described coring circuit has an input channel that is connected to described the 3rd FIR filter (33,35,36,37,39,40,43,44,45,46,47), and be connected to a described output channel that is used for composite signal sampler (48), described coring circuit comprises comparison means (130), be used for sample of signal and described threshold signal from described the 3rd FIR filter are compared, described coring circuit (122-128) produces described sample of signal as the output sampling, with the response first time of result relatively; And produce a predetermined digital signal as output signal, with the response second time of result relatively.

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