CN100594600C - Complementary metal-oxide-semiconductor transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides a complementary metal oxide semiconductor transistor and a manufacturing method thereof, wherein a deep pocket doping region is arranged in a semiconductor substrate to avoid the occurrence of a latch-up phenomenon. In addition, because the manufacture of the deep pocket doping area is integrated in the lightly doped drain process or the source/drain doping area process, the latch-up prevention capability can be effectively improved without increasing the cost of an additional mask.

Description

Complementary metal-oxide-semiconductor transistor and manufacturing method thereof

technical field

The present invention relates to a complementary metal oxide semiconductor transistor and a manufacturing method thereof, in particular to a complementary metal oxide semiconductor transistor with excellent latch-up robustness and a manufacturing method thereof.

Background technique

A Complementary Metal Oxide Semiconductor (CMOS) transistor is a semiconductor basic element composed of an N-type Metal Oxide Semiconductor (NMOS) transistor and a P-type Metal Oxide Semiconductor (PMOS) transistor.

Please refer to FIG. 1 , which is a schematic structural diagram of a conventional CMOS transistor. As shown in FIG. 1, the existing complementary metal oxide semiconductor transistor includes a P-type semiconductor substrate 10, and the semiconductor substrate 10 in the bottom view direction can distinguish the P-type metal oxide semiconductor element region 20 from the N-type metal oxide semiconductor The element region 40 is isolated by the isolation structure 12 . In the P-type metal oxide semiconductor element region 20, an N-type well 22 is located in the semiconductor substrate 10, a gate insulating layer 24 is located on the surface of the semiconductor substrate 10, a gate electrode 26 is located on the surface of the gate insulating layer 24, and two gaps are formed. The partition walls 28 are located on both sides of the gate electrode 26 , and the two P-type source/drain doped regions 30 are respectively located in the semiconductor substrate 10 on both sides of the two partition walls 28 . In addition, one lightly doped drain 32 is respectively provided in the semiconductor substrate 10 below the partition wall 28 on both sides of the gate electrode 26, and a pocket type ( halo or pocket) doped region 34.

On the other hand, in the NMOS element region 40, a P-type well 42 is located in the semiconductor substrate 10, a gate insulating layer 44 is located on the surface of the semiconductor substrate 10, and a gate electrode 46 is located on the surface of the gate insulating layer 44. , two spacers 48 are located on both sides of the gate electrode 46 , and two N-type source/drain doped regions 50 are respectively located in the semiconductor substrate 10 on both sides of the two spacers 48 . In addition, lightly doped drains 52 are respectively disposed in the semiconductor substrate 10 below the partition walls 48 on both sides of the gate electrode 46 .

At present, complementary metal-oxide-semiconductor transistors have been widely used as the main basic electronic components in integrated circuits. The isolation is more important, otherwise it is prone to lock-up. In addition, for some integrated circuits with high current or high voltage, such as analogue ICs or power management circuits (PMICs), CMOS transistors are more prone to latch-up.

Please continue to refer to FIG. 2 and FIG. 3 , and refer to FIG. 1 together. FIG. 2 is a schematic diagram of a pnpn diode, and FIG. 3 is a graph showing the relationship between current and voltage of the pnpn diode in FIG. 2 . As shown in FIG. 1 , CMOS transistors are connected in an inverter manner to test the latch-up phenomenon. In the P-type metal oxide semiconductor device region 20, the P-type source/drain 30, the N-type well 22 and the P-type semiconductor substrate 10 will form a vertical pnp bipolar transistor, while the N-type metal In the oxide semiconductor device region 40 , the N-type source/drain 50 and the P-type well 42 and the N-type well 22 of the P-type MOS device region 20 form a lateral npn bipolar transistor. Since the base of the vertical pnp bipolar transistor is connected to the collector of the horizontal npn bipolar transistor, the collector of the vertical pnp bipolar transistor is also connected to the horizontal npn bipolar transistor. The bases of the transistors are connected. In this case, the base of any bipolar transistor is driven by the collector of the other bipolar transistor, so that the vertical pnp bipolar transistor and the horizontal npn Bipolar transistors form a positive feedback loop.

The above-mentioned positive feedback loop can be regarded as a parasitic pnpn diode, as shown in FIG. 2 , and the operating curve of the current (I) and voltage (V) of the pnpn diode is shown in FIG. 3 . The triggering currcnt of the pnpn diode is I _H , and when the current is greater than the triggering current (I>I _H ), the pnpn diode will be in an operating state, causing the CMOS transistor to lock up. Once the latch-up phenomenon occurs, the complementary metal oxide semiconductor transistor will temporarily or even permanently lose its function, which will affect the normal operation of the complementary metal oxide semiconductor transistor. Therefore, in the design and production process of the complementary metal oxide semiconductor transistor , How to avoid the occurrence of latch-up phenomenon has become an important topic in research and development.

Contents of the invention

An object of the present invention is to provide a method for fabricating a complementary metal-oxide-semiconductor transistor to improve the latch-up prevention capability of the complementary metal-oxide-semiconductor transistor.

Another object of the present invention is to provide a CMOS transistor with excellent latch-up prevention capability.

To achieve the above object, an embodiment of the present invention provides a method for fabricating a CMOS transistor. First, a semiconductor substrate is provided, which includes a first conductivity type metal oxide semiconductor element region and a second conductivity type metal oxide semiconductor element region, and the semiconductor substrate includes a second conductivity type metal oxide semiconductor element region. The doped well of the conductivity type includes the doped well of the first conductivity type in the metal oxide semiconductor element region of the second conductivity type. Then a plurality of isolation structures are formed on the surface of the semiconductor substrate, and a gate structure is formed in the first conductive type metal oxide semiconductor element region. After that, a first mask pattern is formed on the surface of the semiconductor substrate, wherein the first mask pattern exposes the gate structure of the first conductivity type metal oxide semiconductor element region and the semiconductor substrate on both sides of the gate structure . Subsequently, using the first mask pattern as a mask, two lightly doped Miscellaneous drain. Using the first mask pattern again as a mask, two deep pocket-type wells are formed in the doped wells of the second conductivity type on both sides of the gate structure of the first conductivity type metal oxide semiconductor element region by ion implantation. Doped regions, wherein the two deep pocket doped regions are of the second conductivity type. Afterwards, the first mask pattern is removed, and a gap is formed on the sidewalls of the gate structure of the first conductivity type metal oxide semiconductor device region and the gate structure of the second conductivity type metal oxide semiconductor device region next door. Then, a second mask pattern is formed on the surface of the semiconductor substrate, wherein the second mask pattern exposes the gate structure of the first conductivity type metal oxide semiconductor device region and both sides of the partition wall of the gate structure of the semiconductor substrate. Next, using the second mask pattern as a mask, two source electrodes/ Drain doped region. The second mask pattern is subsequently removed.

The method for manufacturing complementary metal-oxide-semiconductor transistors of the present invention uses the lightly doped drain mask pattern as a mask to create a deep pocket-type doped region, which can not only improve the lock-up prevention ability, but also prevent Add additional mask cost.

In order for those skilled in the art to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the accompanying drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

Description of drawings

FIG. 1 is a schematic structural diagram of an existing CMOS transistor.

Figure 2 is a schematic diagram of a pnpn diode.

FIG. 3 is a graph of current versus voltage for the pnpn diode of FIG. 2 .

FIG. 4 is a flowchart of a method for fabricating a CMOS transistor according to the first preferred embodiment of the present invention.

5 to 11 are schematic diagrams of a method for fabricating a complementary metal-oxide-semiconductor transistor according to a first embodiment of the present invention.

FIG. 12 is a flowchart of a method for fabricating a CMOS transistor according to a second preferred embodiment of the present invention.

13 to 19 are schematic diagrams of a method for fabricating a complementary metal-oxide-semiconductor transistor according to a second embodiment of the present invention.

[Description of main component symbols]

10 Semiconductor substrate 12 Isolation structure

20P type metal oxide semiconductor element area 22N type well

24 gate insulating layer 26 gate electrode

28 partition walls 30 source/drain doped regions

32 lightly doped drain 34 pocket doped region

40N type metal oxide semiconductor element area 42P type well

44 gate insulating layer 46 gate electrode

48 partition wall 50 source/drain doped region

52 lightly doped drain 70 semiconductor substrate

72P type metal oxide semiconductor element area 74N type metal oxide semiconductor element area

76N-type doped well 78P-type doped well

80 isolation structure 82 gate insulating layer

84 gate insulating layer 86 gate electrode

88 gate electrode 89 mask pattern

90 Lightly doped drain 92 Partition wall

93 mask pattern 94 source/drain doped region

96 N-type doped region 98 first mask pattern

100 lightly doped drain 102 pocket doped region

104 deep pocket doped region 106 source/drain doped region

108P-type doped region 118 second mask pattern

120 semiconductor substrate 122P type metal oxide semiconductor element area

124N type metal oxide semiconductor element region 126N type doped well

128P doped well 130 isolation structure

132 Gate insulating layer                         134 Gate insulating layer

136 grid electrodes

139 mask pattern 140 two lightly doped drains

142 partition wall 143 mask pattern

144 source/drain doped region 146 N-type doped region

148 first mask pattern 150 lightly doped drain

152 Pocket Doping Region 154 Deep Pocket Doping Region

156 source/drain doped region 158P type doped region

160 second mask pattern

Detailed ways

Please refer to FIG. 4 . FIG. 4 is a flowchart of a method for fabricating a CMOS transistor according to a first preferred embodiment of the present invention. As shown in FIG. 4 , the main process steps of manufacturing a complementary metal-oxide-semiconductor transistor in this embodiment include:

Step 60: providing a semiconductor substrate;

Step 61: forming a doped well;

Step 62: forming an isolation structure;

Step 63: making a gate structure;

Step 64: making a lightly doped drain, a pocket-type doped region, and a deep-pocket doped region;

Step 65: making partition walls; and

Step 66: Make Source/Drain.

Please continue to refer to FIG. 5 to FIG. 11 . FIG. 5 to FIG. 11 are schematic diagrams of a method for fabricating a CMOS transistor according to a first embodiment of the present invention. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type, but it is not limited thereto. In other embodiments, the first conductivity type can also be N-type, and the second conductivity type It is P type. As shown in Figure 5, a P-type semiconductor substrate 70 is first provided, and the semiconductor substrate 70 in the bottom view direction includes a P-type metal oxide semiconductor element region 72 for making a P-type metal oxide semiconductor transistor, and an N-type metal oxide semiconductor element region 72. The material semiconductor element region 74 is used for making N-type metal oxide semiconductor transistors. Next, an N-type doped well 76 is formed in the semiconductor substrate 70 in the P-type MOS device region 72 , and a P-type doped well 78 is formed in the semiconductor substrate 70 in the N-type MOS device region 74 . Subsequently, a plurality of isolation structures 80 such as field oxide layers or shallow trench isolation structures are formed on the surface of the semiconductor substrate 70 .

As shown in FIG. 6, a dielectric layer such as a silicon oxide layer and a conductive layer such as a polysilicon layer are sequentially formed on the surface of the semiconductor substrate 70, and are respectively formed on the P-type metal oxide semiconductor device region 72 by using photolithography and etching techniques. A gate insulating layer 82 and a gate electrode 86 are formed on the semiconductor substrate 70 , and a gate insulating layer 84 and a gate electrode 88 are formed on the semiconductor substrate 70 in the NMOS device region 74 .

As shown in FIG. 7, the surface of the P-type metal oxide semiconductor device region 72 and the surface of a part of the N-type metal oxide semiconductor device region 74 are shielded by a mask pattern 89, and the N-type metal oxide semiconductor device region is implanted by ion implantation. Two lightly doped drains 90 are formed in the semiconductor substrate 70 on both sides of the gate electrode 88 in the element region 74 , and then the mask pattern 89 is removed.

As shown in FIG. 8, a first mask pattern 98, such as a photoresist pattern, is then formed on the surface of the semiconductor substrate 70. The first mask pattern 98 covers the N-type metal oxide semiconductor element region 74 and part of the P-type metal oxide. The semiconductor device region 72 exposes the gate electrode 86 of the PMOS device region 72 and the semiconductor substrate 70 on both sides of the gate electrode 86 . Subsequently, using the first mask pattern 98 as a mask, two slightly P-type (P- ) lightly doped drain 100, and two slightly N-type (N-) pocket-type doped regions 102. Using the same first mask pattern as 98 as a mask, two heavily N-type (N+ ) deep pocket type (deep halo) doped region 104.

The lightly doped drain 100 , the pocket doped region 102 and the deep pocket doped region 104 use the same first mask pattern 98 as a mask, and are respectively formed in the N-type doped well 76 by using different ion implantation processes. , followed by one or several annealing processes to drive in dopants. It is worth noting that the sequence of the ion implantation process for forming the lightly doped drain 100 , the pocket-type doped region 102 and the deep-pocket-type doped region 104 is not limited by the above description of this embodiment and can be adapted to the situation. The deep pocket-type doped region 104 is formed by high-energy and high-dose ion implantation process, so that it is located under the pocket-type doped region 102 and the lightly doped drain 100 and corresponds to the pocket-type doped region 102 and the lightly doped drain 100. The drain 100 is doped. In this embodiment, the ion implantation energy of the high-energy high-dose ion implantation process is about 150-180 keV, and the ion implantation concentration is about 1013-1014 atoms/cm3, but it is not limited thereto. The presence of the deep pocket type doped region 104 can increase the base width (base width) of the vertical pnp bipolar transistor located in the P-type metal oxide semiconductor element region 72, and reduce its β gain (beta gain), so The occurrence of locking phenomenon can be avoided.

As shown in FIG. 9, the first mask pattern 98 is subsequently removed, and the two side walls of the gate electrode 86 of the P-type metal oxide semiconductor device region 72 and the gate electrode 88 of the N-type metal oxide semiconductor device region 74 are removed. Partition walls 92 are formed. Then use the mask pattern 93 to shield the surface of part of the P-type metal oxide semiconductor device region 72 and the surface of part of the N-type metal oxide semiconductor device region 74, and perform an ion implantation process between the N-type metal oxide semiconductor device region 74. Two source/drain doped regions 94 are formed in the semiconductor substrate 70 on both sides of the partition wall 92, and at the same time, they are formed in the semiconductor substrate 70 of the P-type metal oxide semiconductor element region 72 to be electrically connected to the N-type doped well 76. The connected N-type doped region 96. The mask pattern 93 is subsequently removed.

As shown in FIG. 10, a second mask pattern 118 is then formed on the surface of the semiconductor substrate 70. The second mask pattern 118 shields part of the surface of the P-type metal oxide semiconductor device region 72 and part of the N-type metal oxide semiconductor device. region 74, and use the second mask pattern 118 as a mask to form two source/drain doped electrodes in the semiconductor substrate 70 on both sides of the partition wall 92 of the P-type metal oxide semiconductor element region 78 by ion implantation process. The impurity region 106 and the P-type doped region 108 for electrically connecting with the P-type doped well 78 are formed in the semiconductor substrate 70 of the N-type metal oxide semiconductor device region 74 . As shown in FIG. 11 , the second mask pattern 118 is finally removed, that is, a CMOS transistor with a deep pocket doped region 104 is fabricated.

From the above, it can be known that the deep pocket doped region 104, the pocket doped region 102 and the lightly doped drain 100 of this embodiment are produced by the ion implantation process respectively through the same first mask pattern 98, so there is no need to separately Adding an additional mask can achieve the effect of avoiding the latch-up phenomenon.

Please refer to FIG. 12 . FIG. 12 is a flowchart of a method for fabricating a CMOS transistor according to a second preferred embodiment of the present invention. As shown in FIG. 12 , the main process steps of manufacturing a complementary metal-oxide-semiconductor transistor in this embodiment include:

Step 110: providing a semiconductor substrate;

Step 111: forming a doped well;

Step 112: forming an isolation structure;

Step 113: making a gate structure;

Step 114: making a lightly doped drain and a pocket doped region;

Step 115: making partition walls; and

Step 116: Fabricate source/drain and deep pocket doped regions.

Please continue to refer to FIG. 13 to FIG. 19 . FIG. 13 to FIG. 19 are schematic diagrams of a method for fabricating a CMOS transistor according to a second embodiment of the present invention. In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type, but the method and application of the present invention are not limited thereto. In other embodiments, the first conductivity type can also be N-type , while the second conductivity type is P-type. As shown in FIG. 13 , firstly, a P-type semiconductor substrate 120 is provided. The semiconductor substrate 120 viewed from the bottom direction includes a P-type metal oxide semiconductor element region 122 for making a P-type metal oxide semiconductor transistor, and an N-type metal oxide semiconductor element region 122. The oxide semiconductor device region 124 is used to fabricate N-type metal oxide semiconductor transistors. Next, an N-type doped well 126 is formed in the semiconductor substrate 120 of the P-type MOS device region 122 , and a P-type doped well 128 is formed in the semiconductor substrate 120 of the N-type MOS device region 124 . Subsequently, a plurality of isolation structures 130 such as field oxide layers or shallow trench isolation structures are formed on the surface of the semiconductor substrate 120 .

As shown in FIG. 14 , a dielectric layer such as a silicon oxide layer and a conductive layer such as a polysilicon layer are sequentially formed on the surface of the semiconductor substrate 120, and are respectively formed on the P-type metal oxide semiconductor device region 122 by using photolithography and etching techniques. A gate insulating layer 132 and a gate electrode 136 are formed on the semiconductor substrate 120 , and a gate insulating layer 134 and a gate electrode 138 are formed on the semiconductor substrate 120 in the NMOS device region 124 .

As shown in FIG. 15, the surface of the N-type metal oxide semiconductor device region 124 and a part of the surface of the P-type metal oxide semiconductor device region 122 are shielded by a mask pattern 139, and the N-type metal oxide semiconductor device region 122 is covered by an ion implantation process. Two lightly doped drains 140 are formed in the semiconductor substrate 120 on both sides of the gate electrode 138 in the device region 124 , and then the mask pattern 139 is removed.

As shown in FIG. 16, a first mask pattern 148, such as a photoresist pattern, is then formed on the surface of the semiconductor substrate 120. The first mask pattern 148 covers the N-type metal oxide semiconductor element region 124 and part of the P-type metal oxide. The semiconductor device region 122 exposes the gate structure of the PMOS device region 122 and the semiconductor substrate 120 on both sides of the gate structure. Subsequently, using the first mask pattern 148 as a mask, two slightly P-type (P- ) lightly doped drain 150, and two slightly N-type (N-) pocket-type doped regions 152.

As shown in FIG. 17, the first mask pattern 148 is subsequently removed, and then the two side walls of the gate electrode 136 of the P-type metal oxide semiconductor device region 122 and the gate electrode 138 of the N-type metal oxide semiconductor device region 124 are removed. Partition walls 142 are formed. Next, mask patterns 143 are used to shield part of the surface of the P-type metal oxide semiconductor device region 122 and part of the surface of the N-type metal oxide semiconductor device region 124, and ion implantation is performed between the N-type metal oxide semiconductor device region 124. Two source/drain doped regions 144 are formed in the semiconductor substrate 120 on both sides of the partition wall 142, and are formed in the semiconductor substrate 120 of the P-type metal oxide semiconductor element region 122 at the same time to be electrically connected to the N-type doped well 126. The connected N-type doped region 146. The mask pattern 143 is subsequently removed.

As shown in FIG. 18, a second mask pattern 160 is then formed on the surface of the semiconductor substrate 120, and the second mask pattern 160 shields part of the surface of the P-type metal oxide semiconductor device region 122 and part of the N-type metal oxide semiconductor device. region 124, and use the second mask pattern 160 as a mask to form two source/drain doped electrodes in the semiconductor substrate 120 on both sides of the partition wall 142 of the P-type metal oxide semiconductor element region 128 by ion implantation process. impurity region 156 , and form a P-type doped region 158 in the semiconductor substrate 120 of the N-type metal oxide semiconductor device region 124 for electrically connecting with the P-type doped well 128 . At the same time, the second mask pattern 160 is used as a mask again, and two heavily N-type (N+ ) deep pocket type (deep halo) doped region 154.

The deep pocket doped region 154 and the source/drain doped region 156 in the N-type doped well 126 use the same second mask pattern 160 as a mask, and are respectively formed in the N-type doped well 126 using different ion implantation processes. Doped well 126. It is worth noting that the sequence of the ion implantation process for forming the source/drain doped region 156 and the deep pocket doped region 154 is not limited by the above description of this embodiment and can be changed according to the situation. The deep pocket-type doped region 154 is formed by high-energy and high-dose ion implantation process, so that it is located below the source/drain doped region 156 and corresponds to the source/drain doped region 156 . In this embodiment, the ion implantation energy of the high energy and high dose ion implantation process is about 150 to 180 keV, and the ion implantation concentration is about 10 ¹³ to 10 ¹⁴ atoms/cm ³ , but it is not limited thereto. The presence of the deep pocket type doped region 154 can increase the base width of the vertical pnp bipolar transistor located in the PMOS element region 122, and reduce its β gain (beta gain), so the lock-up phenomenon can be avoided occur.

Finally, as shown in FIG. 19 , the second mask pattern 160 is finally removed, that is, a CMOS transistor with a deep pocket doped region 154 is fabricated.

From the above, it can be seen that the deep pocket doped region 154 and the source/drain doped region 156 of this embodiment are produced by the ion implantation process respectively through the same second mask pattern 160, so there is no need to add an additional mask The effect of avoiding the locking phenomenon can be achieved.

In summary, the complementary metal oxide semiconductor transistor of the present invention increases the base width of the vertical pnp bipolar transistor by setting the deep pocket doped region, thereby reducing its β gain, thus avoiding the occurrence of latch-up phenomenon, Moreover, the fabrication of the deep pocket doped region is integrated in the lightly doped drain process or the source/drain doped region process, so that the latch-up prevention capability can be effectively improved without adding additional mask costs.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims shall fall within the scope of the present invention.

Claims (16)

1. method of making CMOS transistor includes:

The semiconductor-based end, be provided, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;

Form a plurality of isolation structures in the surface at this semiconductor-based end;

Form grid structure in this first conductivity type metal oxide semiconductor device district;

Form first mask pattern in the surface at this semiconductor-based end, this first mask pattern exposes this grid structure in this first conductivity type metal oxide semiconductor device district and the semiconductor-based end of these grid structure both sides;

Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two lightly doped drains;

Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two dark pouch-type doped regions, wherein these two dark pouch-type doped regions are second conductivity type;

Remove this first mask pattern, and form spaced walls in the sidewall of this grid structure in this grid structure in this first conductivity type metal oxide semiconductor device district and this second conductivity type metal oxide semiconductor device district;

Form second mask pattern in the surface at this semiconductor-based end, this second mask pattern exposes this semiconductor-based end of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and this grid structure;

Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two source electrode; And

Remove this second mask pattern.

2. method as claimed in claim 1, other includes in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and to form before these two the dark pouch-type doped regions, utilizes this first mask pattern to form two pouch-type doped regions with second conductivity type earlier in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.

3. method as claimed in claim 1, wherein this first conductivity type is the P type, and this second conductivity type is the N type.

4. method as claimed in claim 1, wherein the ion implantation energy of these two dark pouch-type doped regions is between 150 to 180kev.

5. method as claimed in claim 1, wherein the ion implantation concentration of these two dark pouch-type doped regions is between 10 ¹³To 10 ¹⁴Atom/cm ³Between.

6. CMOS transistor includes:

The semiconductor-based end, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;

A plurality of isolation structures are arranged in this semiconductor-based end;

Grid structure be positioned at the surface at this semiconductor-based end in this first conductivity type metal oxide semiconductor device district, and spaced walls is positioned at the both sides of this gate electrode;

Two source electrode are arranged in this second conductivity type dopant well of this spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district;

Two lightly doped drains, be arranged in this first conductivity type metal oxide semiconductor device district these grid structure both sides this second conductivity type dopant well and respectively to should spaced walls; And

Two dark pouch-type doped regions, be arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district, wherein these two dark pouch-type doped regions are second conductivity type, and respectively this dark pouch-type doped region is positioned at the below of this source electrode of this gate electrode both sides and this lightly doped drain and to should source electrode and this lightly doped drain.

7. CMOS transistor as claimed in claim 6, other comprises two pouch-type doped regions with second conductivity type, is arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.

8. CMOS transistor as claimed in claim 6, wherein this first conductivity type is the P type, and this second conductivity type is the N type.

9. method of making CMOS transistor includes:

The semiconductor-based end, be provided, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;

Form a plurality of isolation structures in the surface at this semiconductor-based end;

Form grid structure in this first conductivity type metal oxide semiconductor device district;

Form first mask pattern in the surface at this semiconductor-based end, this first mask pattern exposes this grid structure in this first conductivity type metal oxide semiconductor device district and the semiconductor-based end of these grid structure both sides;

Utilize this first mask pattern as mask, flow into by ion in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district and form two lightly doped drains;

Remove this first mask pattern, and form spaced walls in the sidewall of this grid structure in this grid structure in this first conductivity type metal oxide semiconductor device district and this second conductivity type metal oxide semiconductor device district;

Form second mask pattern in the surface at this semiconductor-based end, this second mask pattern exposes this semiconductor-based end of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and this grid structure;

Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and form two source electrode;

Utilize this second mask pattern as mask, flow into by ion in this second conductivity type dopant well of these spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district and form two dark pouch-type doped regions, wherein these two dark pouch-type doped regions are second conductivity type; And

Remove this second mask pattern.

10. method as claimed in claim 9, other included before removing this first mask pattern, utilized this first mask pattern to form two pouch-type doped regions with second conductivity type earlier in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.

11. method as claimed in claim 9, wherein this first conductivity type is the P type, and this second conductivity type is the N type.

12. method as claimed in claim 9, wherein the ion implantation energy of these two dark pouch-type doped regions is between 150 to 180kev.

13. method as claimed in claim 9, wherein the ion implantation concentration of these two dark pouch-type doped regions is between 10 ¹³To 10 ¹⁴Atom/cm ³Between.

14. a CMOS transistor includes:

The semiconductor-based end, include the first conductivity type metal oxide semiconductor device district and the second conductivity type metal oxide semiconductor device district, this semiconductor-based end, include the second conductivity type dopant well in this first conductivity type metal oxide semiconductor device district, and include the first conductivity type dopant well in this second conductivity type metal oxide semiconductor device district;

A plurality of isolation structures are arranged in this semiconductor-based end;

Grid structure is positioned at the surface at this semiconductor-based end in this first conductivity type metal oxide semiconductor device district and the both sides that spaced walls is positioned at this gate electrode;

Two source electrode are arranged in this second conductivity type dopant well of spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district;

Two lightly doped drains, be arranged in this first conductivity type metal oxide semiconductor device district these grid structure both sides this second conductivity type dopant well and respectively to should two spaced walls; And

Two dark pouch-type doped regions, be arranged in this second conductivity type dopant well of this spaced walls both sides of this grid structure in this first conductivity type metal oxide semiconductor device district, wherein these two dark pouch-type doped regions are second conductivity type, and respectively this dark pouch-type doped region be positioned at these gate electrode both sides this source electrode the below and to should source electrode.

15. CMOS transistor as claim 14, other comprises two pouch-type doped regions with second conductivity type, is arranged in this second conductivity type dopant well of these grid structure both sides in this first conductivity type metal oxide semiconductor device district.

16. as the CMOS transistor of claim 14, wherein this first conductivity type is the P type, and this second conductivity type is the N type.

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