CN100594491C - Reconfigurable Digital Signal Processor - Google Patents

Abstract

The invention discloses a reconfigurable digital signal processor (DSP). The internal hardware resources of the device can be restructured according to different application requirements, so that various forms of filtering operations can be realized. The invention combines the advantages of the traditional application-specific integrated circuit (ASIC) and the general digital signal processor. It has the computing capability of ultra-large-scale special-purpose devices, and can adapt to different digital signal real-time processing occasions such as fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), FIR pulse group processing, correlation processing, etc., and is easy to use and low in price. .

Description

Reconfigurable Digital Signal Processor

Technical field

The invention discloses a reconfigurable digital signal processor (DSP) for real-time processing of digital signals such as fast Fourier transform (FFT), fast Fourier inverse transform (IFFT), FIR pulse group processing and correlation processing.

Background technique

Since the 1960s, with the rapid development of computing technology and information technology, digital signal processing has developed rapidly as an independent subject and has been widely used in many fields. With the rapid development of large-scale integrated circuit technology and semiconductor technology and the continuous improvement of various real-time processing requirements, the digital signal processing capability has also increased rapidly at an exponential rate, and it has played an increasingly important role in scientific research, military and civilian fields. Important role, digital signal processing devices have become an important condition to support the rapid development of these fields. In the real-time processing of digital signals, filtering operations such as fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), FIR pulse group processing, and correlation processing are most widely used. Currently, there are mainly three hardware implementation methods based on general-purpose digital signal processors, field-programmable gate arrays (FPGA)/large-scale programmable logic devices (CPLDs) and application-specific integrated circuits (ASICs). On the one hand, the three devices have their own limitations. The advantage of the general-purpose digital signal processor lies in the flexibility and universality of programming, but its computing power is limited. Large-capacity FPGA/CPLD has many internal hardware resources, but firmware logic needs to be developed separately for specific applications, the labor cost is high, and large-capacity FPGA/CPLD is expensive. The traditional application-specific integrated circuit architecture and hard-wire connection are fixed, and the function is relatively single, and its application range is greatly limited. On the other hand, the technical requirements of digital signal processing are constantly improving. With the continuous expansion of broadband applications, the continuous increase of the number of array processing, and the continuous increase in the amount of calculations involved in cooperative and non-cooperative number target processing, the requirements for signal processing The speed is constantly increasing. For example, the operation speed of complex 1024-point FFT is required to be above 100MHz, and in some cases it is required to be above 500MHz. It is increasingly difficult for the above three devices to meet the requirements of real-time processing of digital signals in terms of function, price, adaptability, and ease of use.

Contents of the invention

The technical problem to be solved by the present invention is to provide a reconfigurable digital signal processor applied to real-time processing of digital signals, which has the computing capability of dedicated large-scale integrated circuits, and can adapt to fast Fourier transform (FFT), fast Fourier inverse Transformation (IFFT), FIR pulse group processing, correlation processing and other digital signal real-time processing occasions, at the same time, it is easy to use and low in price.

The technical scheme that the present invention takes is:

The internal hardware architecture and hardware connection of the reconfigurable digital signal processor can be restructured by configuring the control word, so as to realize various types of fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT), FIR pulse group and related processing, etc. form of filtering operations.

The main structure includes input unit, output unit, data exchange unit and 4 basic units. The basic unit contains 160 real floating-point multiplication accumulators, and they are evenly distributed in the 4 basic units.

The organizational form of the hardware can be reorganized by configuring the control word: through the configuration of the control word and control signal, the organizational form of the 160 real-number floating-point multiplication accumulators and data exchange units can be changed, so that they can choose different working modes to adapt to Three different calculation tasks: FFT/IFFT, FIR pulse group processing, correlation calculation.

The hardware scheduling scheme adopts a two-level scheduling method combining centralized and distributed: that is, the control word is decoded first by the global module, and then decoded by each basic unit.

The overall architecture adopts a two-level control architecture. The global control module is used to coordinate the four basic units, and each basic unit has its own local control logic inside. The data exchange unit between the four basic units is responsible for sending the data in each basic unit to the other three basic units according to different control requirements.

The input unit receives the control word, performs one-level decoding on the control word, and distributes the control word to each unit. The control word and coefficient entry 1 multiplex the same port. The control word receiving module receives the control word, and then sends it to the first-level decoding module for decoding. On the one hand, it generates a global control signal for generating on-chip timing and providing synchronization for coefficients and data. , and on the other hand transmit to other units in the chip respectively through the control word allocation module. The coefficient synchronization module synchronizes coefficient entry 1 and coefficient entry 2. The data synchronization module synchronizes data entry 1 and data entry 2.

The data exchange unit is a group of multi-input and multi-output switch combination, which exchanges data between the four basic units.

The output unit sorts the operation results of each basic unit and outputs them in different formats. The output result sorting module of the basic unit arranges the output of the basic unit according to the channel order during FFT/IFFT and FIR pulse group processing; when working in the correlation processing operation mode, it adjusts the frame-by-frame output data from each basic unit to be consistent with the input A continuous stream of data at the same data rate. The modulo module completes the conversion from the output format of the real part/imaginary part to the output format of the modulus value/phase angle. The logarithm module converts the input modulo value to a logarithmic representation. The floating-point/fixed-point conversion module can convert the output of the real part/imaginary part module or the modulo module from a floating-point format to a fixed-point format. The exponent normalization module unifies the exponents of the operation results in floating-point format to a fixed value by correspondingly shifting the mantissa. There are two sets of the above four format conversion modules, one for each output port, to ensure that the two output ports can be independently output in any format.

In the basic unit, the data memory includes eight 512×40 dual-port RAMs, which are used for input buffering of operation data, temporary storage of intermediate results of operation, and output buffer of operation results. The data buffer can add data to each complex multiply-accumulator and complex multiply-accumulator sub-array simultaneously. The coefficient memory includes 10 dual-port RAMs of 256×32, which are used to store correlation processing and FIR filter coefficients and weighting coefficients during FFT operations. The coefficients of the FFT iterative operation are a fixed table implemented with dedicated logic. Each complex multiplication accumulator corresponds to four real floating-point multiplication accumulators, and each complex multiplication accumulator sub-array includes 16 real floating-point multiplication accumulators, equivalent to four complex multiplication accumulators. The two complex multiplication accumulator sub-arrays and the complex multiplication accumulator are combined in different ways to complete different operations. The structure of the real floating-point multiplication accumulator is divided into five parts: fixed-point multiplication part, truncation part, index adjustment part, fixed-point addition part, and index judgment part.

The corresponding organizational forms in the three filtering operations are:

When doing FFT/IFFT operations, complex multiplication and accumulation sub-array A and complex multiplication and accumulation sub-array B are respectively used as nodes of an iterative operation of the radix-8 algorithm, and the four complex multiplication accumulators in the sub-array are used to complete the first-level radix-8 iterative operation . The complex multiplication accumulator A and the complex multiplication accumulator B in front of the sub-array are used as a windowing operator to perform windowing processing on the data. The data after windowing enters the complex multiplication and accumulation sub-array for the first-level radix-8 iterative operation. The output of each level of iterative operation is first imported into the data cache, and then sent to another corresponding complex multiplication and accumulation sub-array through the data exchange unit for the next level of iterative operation.

When doing FIR pulse group processing, the 2 complex multiplication accumulator modules inside the basic unit and the multiplication accumulators in the 2 complex multiplication accumulator sub-array modules are used in parallel, and each complex multiplication accumulator corresponds to a channel of the FIR pulse group . The conjugate operation corresponds to 2 channels.

When performing correlation operations, the complex multiplication accumulator and the complex multiplication accumulator sub-array are used in series, which is equivalent to connecting 10 complex multiplication accumulators in series. At this time, the multiplication accumulator inside the basic unit is constructed in a cascaded form.

The hardware scheduling scheme adopted is:

The scheduling of hardware resources through control words and control signals adopts a two-level scheduling mode combining global control and local control in the basic unit. Control words and control signals first enter the global control module for first-level decoding and control word distribution. In this module, the control word is received first, and then some global control signals are generated according to the control word. These global controls include: coordinating the actions of the four basic units, determining the output format of the operation results, and setting the on-chip master clock. The second function of the global control module is to transmit control information to the local control modules of each basic unit. The transmitted information includes: working mode, subtype of working mode, number of operation points, number of channels, number of processing channels.

After receiving the information transmitted by the global control module, the local control module in each basic unit performs two-level decoding on the information and converts it into the details of the hardware scheduling control signal.

The present invention has significant technical progress and positive effects:

The invention combines the advantages of the traditional special integrated circuit and the general digital signal processor.

High-speed processing capability: The present invention adopts a reconfigurable special-purpose digital signal processor scheme, and the chip contains a large amount of hardware resources, and there are as many as 160 floating-point multiplication accumulators, which is far superior to traditional ASICs in terms of processing capability. Since the internal algorithms of the device are all implemented by hardware, it has high-speed computing performance unmatched by general-purpose digital signal processor chips. The internal operation format of the device is floating point. The maximum number of points for fast Fourier transform (FFT) operation on a single chip is 4096 points. The time to complete 4096 points of FFT operation is 25.6us, and the time to complete FFT+IFFT with the same number of points is 51.2us; FIR pulse group processing The maximum number of channels is 128, the maximum filter length of less than 80 channels is 256, and the maximum filter length of more than 80 channels is 128; the maximum operation length of a single-chip single-channel correlation processing operation is 4000, and a maximum of 16 channels can be processed in parallel. The corresponding relationship with each group of coefficients is very flexible.

Reconfigurable function: Different from ASIC chips in the traditional sense, the internal resources of the device can be restructured according to different application requirements, so that various forms such as FFT, IFFT, FIR pulse group and related processing can be realized filtering operation. The use flexibility of the device is enhanced, and the application range of the device is expanded.

Convenient usage: the present invention combines the flexibility of general-purpose digital signal processors to a certain extent, and uses a unique 64-bit function control word to configure the device to meet different application requirements. It is very easy to use, without cumbersome programming and debugging, and does not need logic design and timing analysis like FPGA. It only needs to send 64-bit control words, and the operation data can be input according to the standard timing. As long as the control word is changed, the internal resource structure of the device is reorganized, and the device works in another mode.

Description of drawings

Figure 1 Hardware Architecture Block Diagram 1

Figure 2 Basic unit structure block diagram

Figure 3 Real number multiplication accumulator structure block diagram

Fig.4 Block diagram of basic unit configuration of FFT operation

Figure 5 The basic unit configuration structure block diagram of FIR pulse group operation

Figure 6 The basic unit configuration structure block diagram of the correlation operation

Figure 7 Two-level scheduling framework for hardware resources

Figure 8 Hardware Architecture Block Diagram II

Figure 9 Input unit implementation block diagram

Figure 10 output unit implementation block diagram

Figure 11 32-bit control word input sequence diagram

Figure 12 16-bit control word input sequence diagram

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

The main body of the present invention is 160 multiplication accumulators, which are evenly distributed in 4 basic units. Through the configuration of control words and control signals, the 160 multiplier accumulators, memory, data exchange unit and other hardware resources can work in different organizational forms, and these organizational forms determine the different working modes of the device. In addition, the present invention adopts a two-level scheduling method for hardware resource scheduling, and adopts a method of combining centralized control and distributed control in control.

The specific implementation of the present invention is divided into three levels, the first level is the device hardware architecture; the second level is the hardware organization mode; the third level is the hardware resource scheduling method. The three levels are described below.

1. The main structure of the hardware

The hardware architecture of the present invention is shown in Fig. 1 and Fig. 8 .

The present invention adopts a fully synchronous design, that is, the whole chip has only one clock domain. From the perspective of functional division and balance of logical word resources, the top-level design of the entire device is divided into 7 parts, that is, 4 basic units as the main body, plus 3 parts of input unit, output unit, and data exchange.

The device adopts a two-level control architecture. The global control module is used to coordinate the four basic units, and each basic unit has its own local control logic inside. These four basic units are the main body of the device, and complete the main functions such as data cache, operation, and address generation. The data exchange unit between the four basic units is responsible for sending the data in each basic unit to the other three basic units according to different control requirements. In order to meet different applications, several special function modules are integrated inside the device, including: modulo circuit, logarithm circuit, exponent normalization circuit, floating-point-fixed-point conversion circuit, etc. These dedicated functional modules can output the operation results of the basic unit in different ways, and the two output ports are completely independent and do not affect each other. In addition, a phase-locked loop for frequency multiplication is also integrated inside the device, so that the internal operation clock can be directly input from the outside, or a low-speed clock can be input from the outside first, and then the frequency multiplied by the internal phase-locked loop can be used as the operation clock.

The specific implementation of the input unit is shown in Figure 9. Except for the test input pins used for design for test, all functional input pins enter the input cell first. The input unit is responsible for the following tasks: receiving control words, performing first-level decoding on control words, distributing control words to each unit, synchronizing input coefficients, synchronizing input data, and generating global timing signals required on-chip, etc. The following is a brief description of each module in the input unit. The control word and coefficient entry 1 multiplex the same port (coeff_in[31:0]), so the input control word must be received first, which is the task of the control word receiving module. The inside of the control word receiving module is mainly a group of registers, and the 64-bit control word is divided into two or four times into this group of registers according to the enable signal input outside the chip. After receiving the control word, the first-level decoding module decodes part of the control word into global control signals, which are used to generate on-chip timing, provide synchronization for coefficients and data, and so on. The task of the control word allocation module is to decode the 64-bit control word and transmit it to other units in the chip respectively. Because coefficient entry 1 is also responsible for inputting control words, but coefficient entry 2 is not responsible for this task, so coefficient entry 1 and coefficient entry 2 have different delays, so a synchronization module must be used to synchronize coefficient entry 1 and coefficient entry 2. Similarly, data entry 1 and data entry 2 have different functions, so the data of these two data entries must be synchronized according to the working mode and data type.

The specific implementation of the output unit is shown in Figure 10. The main function of this unit is to sort the operation results of each basic unit and output them in different formats. The filtering operation is completed in the basic unit, and each of the four basic units outputs its results, so the output results of the four basic units must be sorted to ensure that the final output results are output in order. The function of the "basic unit output result sorting" module is: when the device is working in FFT/IFFT and FIR pulse group processing, this module will arrange the output of the basic unit in order of channels; Every 10 points is output in a frame format, and there is an interval between two data frames. At this time, this module adjusts the output data format of the basic unit, and adjusts the data output by frame from each basic unit to be consistent with the input A continuous stream of data at the same data rate. The modulus module mainly completes the conversion from the output format of the real part/imaginary part to the output format of the modulus value/phase angle. The logarithm module can convert the input modulo value into a logarithmic representation. The floating-point/fixed-point conversion module can convert the output of the real part/imaginary part module or the modulo module from a floating-point format to a fixed-point format. The function of the exponent normalization module is similar to the floating-point/fixed-point conversion module. It unifies the exponent of the operation result in floating-point format to a fixed value by shifting the mantissa accordingly. There are two sets of the above four format conversion modules, one for each output port of the chip, which ensures that the two output ports can be independently output in any format.

The data exchange unit is actually a group of multi-input, multi-output switch combination. It receives 8 sets of inputs from 4 basic units, and then switches any set of inputs to any set of outputs through the selector switch. In this way, data can be freely transmitted between the four basic units, and when implementing a specific algorithm, it provides a data path guarantee for the cooperation between the four basic units.

The four basic units are the main part of the present invention, and complete most of the functions such as data cache, operation, and address generation. Its structure is shown in Figure 2. The 4 basic units have a unified architecture. The "data memory" includes eight 512×40 dual-port RAMs, which are used for the data input cache of the operation mode, the temporary storage of the intermediate results of the FFT operation, and the output cache of the FFT operation results. It can be seen from the figure that the "data cache" can add data to each "complex multiplication accumulator" and "complex multiplication accumulator sub-array" at the same time. The "coefficient memory" includes 10 256×32 dual-port RAMs, which are used to store correlation processing operations, filter coefficients of FIR filtering operations, and weighting coefficients of FFT operations. "FFT iterative operation coefficient" uses a fixed table implemented with dedicated logic to provide iterative operation coefficients for FFT/IFFT operations. Each "complex multiplication accumulator" in the figure corresponds to 4 real-number floating-point multiplication accumulators, and each "complex multiplication-accumulator sub-array" includes 16 real-number floating-point multiplication accumulators, which is equivalent to 4 "complex multiplication accumulators". Multiply Accumulator". Two "complex multiplication accumulator sub-arrays" and "complex multiplication accumulators" can be combined in different ways to complete different operations.

When doing FFT/IFFT operations, the "complex multiplication accumulator" is used as a weighted multiplier to weight the input data that requires multi-level operations, and then send it to the "complex multiplication and accumulation sub-array" for radix-8 iterative operations. That is to say, when doing FFT/IFFT operations, the "complex multiplication accumulator A" and "complex multiplication accumulator sub-array A" in the basic unit form a radix-8 operation core, and the "complex multiplication accumulator B" and "complex The multiplication accumulator sub-array B" forms another radix-8 operation core, so that the entire chip has 8 such operation cores, and the FFT/IFFT operation is decomposed into these 8 operation cores for parallel processing during operation.

When doing FIR pulse group processing, the two "complex multiplication accumulator" modules inside the basic unit and the multiplication accumulators in the two "complex multiplication accumulator sub-array" modules are used in parallel, and each complex multiplication accumulator corresponds to the FIR pulse A channel of the group. If the conjugate operation is used, each complex multiplication accumulator corresponds to 2 channels, and if it is multiplexed again, it can correspond to the operation of more channels.

When doing correlation operations, the "complex multiplication accumulator" and "complex multiplication accumulator sub-array" are used in series, which is equivalent to connecting 10 complex multiplication accumulators in series; when doing FIR filtering operations, the "complex multiplication accumulator" and "complex multiplication Accumulator sub-array" is used in parallel, corresponding to 10 channels of filtering operation; when doing FFT operation, "complex multiplication accumulator" is used as a weighted multiplier, after weighting the data, it is sent to "complex multiplication accumulator sub-array" for iteration operation.

The present invention adopts the floating point data format to carry out the complex number operation, and the complex number operation is composed of four real number operations, so the real number floating point multiplication accumulator is the core operation part of the device. The structural block diagram of the real floating-point multiplication accumulator is shown in Figure 3, which is divided into five parts: fixed-point multiplication part, truncation part, index adjustment part, fixed-point addition part, and index judgment part.

The data to be calculated by the device has a total of 20 bits, and the format is 4-bit unsigned exponent + 16-bit signed mantissa. The dynamic range that can be represented is -2 ¹⁵ × 2 ¹⁵ ~2 ¹⁵ × 2 ¹⁵ -1. The coefficient is a 16-bit signed fixed-point number, and the dynamic range that can be expressed is -2 ¹⁵ ~2 ¹⁵ -1. For the intermediate data of the operation, the accuracy factor of the operation and the area and speed factors of the hardware implementation are considered in compromise, and the 24-bit floating-point data format is adopted, that is, 4-bit unsigned exponent + 20-bit signed mantissa. The operation process of the multiplication accumulator has the following five steps.

①. The fixed-point multiplication part is used for fixed-point multiplication of the 16-bit signed mantissa of the data and the 16-bit signed coefficient.

②. The truncation part is used to preserve the precision of the fixed-point multiplication result to the greatest extent. The 20-bit mantissa of the 24-bit intermediate operation data to be reserved and the 4-bit exponent corresponding to the mantissa are determined according to the number of redundant sign bits of the 32-bit multiplication result after the fixed-point multiplication. If the 32-bit fixed-point multiplication result has k redundant sign bits, and only 20 bits can be reserved, then obviously, in order to obtain the maximum precision, it is best to truncate the k-bit redundant signs (shift left by k bits) And at the same time subtract k from the exponent. In this way, the mantissa becomes a sign bit followed by 19 data bits. This is equivalent to performing the following operations on a 32-bit fixed-point multiplication result a ₃₁ a ₃₀ a ₂₉ ... a ₂ a ₁ a ₀ × 2 ^e at the same time:

Remove redundant sign bit and truncate: a ₃₁ a ₃₀ a ₂₉ …a ₂ a ₁ a ₀ □a _31-k a _30-k a _29-k …a _{31 -18-k} a _31-19-k

The index is subtracted from the original basis by k: e□e-k

For the case of e>k>12, that is, after the left shift exceeds 12 bits, 0 should be added to the lower bits. At the same time, it should be noted that the index after subtracting k cannot be made less than 0. In this way, when truncation, the number of redundant sign bits and the size of the exponent must be considered comprehensively. If the original exponent is smaller than the number of redundant sign bits, that is, e<k, then only the redundant number of e bits can be truncated. The cosign bit, while decrementing the exponent to 0:

Remove redundant sign bit and truncate: a ₃₁ a ₃₀ a ₂₉ …a ₂ a ₁ a ₀ □a _31-e a _30-e a _29-e ……a _{31 -18-e} a _31-19-e

The index is subtracted from the original basis by k: e 0

③. For the addition of floating-point numbers, the mantissas of the addend and the summand must have the same exponents before they can be added. The index adjustment part just plays the role of adjusting the exponent of the addend or the summand to make them equal. Assuming that A1=a1×2 ^e1 and A2=a2×2 ^e2 are added together, and e1<e2, then the exponent e1 of A1 should be adjusted to the same value as e2, and the mantissa of A1 should be set as e2-e1 Sign bit extended and shifted right e2-e1 bits.

④. After the exponent adjustment, the addend and the augend exponents have been unified, and the adjusted mantissas of the two can be fixed-point added after the sign bit is extended to obtain a 21-bit fixed-point addition result.

⑤. Because the smaller exponent is always adjusted to a larger exponent in the process of ③exponent adjustment, it is necessary to remove redundant sign bits from the 21-bit fixed-point sum after the fixed-point addition, and judge the exponent after the addition at the same time Value, this is the role of index judgment.

Second, the organization of hardware resources

The present invention is a reconfigurable special-purpose digital signal processor. The so-called "reconfigurable" means that hardware resources can be organized by configuring different control words, so that the hardware resources can work in different modes. The present invention can be configured into three types of working modes: FFT/IFFT, FIR pulse group processing, and correlation processing operations. Each of these three types of working modes can adjust its key parameters through the control word to meet different processing requirements. The organization modes of the hardware resources under the three types of working modes are respectively described below in conjunction with the accompanying drawings.

1. FFT/IFFT

The basic formula of the discrete Fourier transform (DFT) is:

k＝0，1，…，N-1

k=0, 1, ..., N-1

Where w(i) is the DFT weighting factor, x(i) is the input data, and e ^□j2<ki/N is the rotation factor. N is the number of points for DFT operation. If N is a composite number, the DFT operation of one long-point number can be transformed into the DFT operation of two short-point numbers (N ₁ , N ₂ ). If N ₁ and N ₂ can continue to be decomposed, then this kind of decomposition can go on forever, and the calculation amount will be further reduced.

According to different decomposition methods, FFT has base 2, base 4, base 8, mixed base and other algorithms. The FFT/IFFT of the present invention adopts radix-8 operation, and this working mode can be subdivided into three types: FFT, IFFT, and FFT+IFFT, and its processing points can be 256 points, 512 points, 1024 points, 2048 points, and 4096 points etc., and when the number of points is less than or equal to 2048, it can also perform FFT or IFFT processing on two channels of data at the same time. Regardless of the number of FFT/IFFT processing points, in this mode of operation, the four basic units (basic_unit) of the device will be configured as shown in Figure 4. At this time, the "complex multiplication and accumulation sub-array A" and "complex multiplication and accumulation sub-array B" shown in Figure 2 are respectively used as nodes of an iterative operation of the radix-8 algorithm, and the four complex multiplication and accumulators in the sub-array are used to complete the first-level Base-8 iterative operation. The "complex multiplication accumulator A" and "complex multiplication accumulator B" in front of the sub-array are used as windowing operators to perform windowing processing on the data. The data after windowing enters the "complex multiplication and accumulation sub-array" for a first-level radix-8 iterative operation. The output of each level of iterative operation is first imported into the data cache, and then sent to the corresponding other "complex multiplication and accumulation sub-array" through the data exchange unit in Figure 1 for the next level of iterative operation. The following describes the hardware organization in FFT/IFFT mode for a single basic unit.

When the GA3816 device performs FFT transformation, if the number of operation points is greater than 256, the device will work in a time-division multiplex mode. The larger the number of processing points, the more times of multiplexing. The data memory is configured as a data cache in a ping-pong structure. The total data storage capacity in the device is 32×256×40bits, and the data cache allocated to each basic unit is 2×4×256×40bits. Each basic unit data buffer allocates half of the address space, that is, 4×256×40 bits, as a data input buffer. In this way, four basic units of a single device can complete a maximum of 4096 FFT operations.

When performing FFT operation, in order to suppress the side lobe, it is necessary to perform window processing on the input data. Inside the GA3816 device, there is a 40×256×32bit dual-port RAM as a coefficient memory, which is allocated to each basic unit with 10×256×32bits. In each basic unit, 8×256×32bits are used as a window function buffer, and this buffer is also divided into two groups, each group has an addressing depth of 1024, which are sent to each "complex multiplication accumulator sub-array" respectively. The windowing operator provides a window function.

Because the twiddle factor of the FFT/IFFT operation has regularity, the present invention stores the twiddle factor of the radix-8 FFT operation in a fixed table. The maximum number of FFT/IFFT points that can be completed by a single chip of the present invention is 4096, and there are eight 512*32bit twiddle factor coefficient tables inside the chip, which are evenly distributed in four basic units (basic_unit). If the number of operation points is less than 4096, the twiddle factors are extracted from this table. In addition, we also designed a coefficient table of 4×8×32bits, which is used to store the coefficients in base-8 operation.

When the number of FFT points is less than or equal to 2048, the present invention designs a second hardware resource organization method for FFT/IFFT: two channels simultaneously perform FFT operations. In the dual-input data mode, the two basic units basic_uint0 and basic_unit2 form a group to complete the first operation; the two basic units basic_uint1 and basic_unit3 form another group to complete the other operation. Although the hardware resources are divided into two groups, the principle of the radix-8 operation of the two groups of hardware remains unchanged. Two channels of data are input from the data input 1 and data input 2 ports at the same time, and the two sets of results obtained by the operation are simultaneously output from the output port 1 and the output port 2 in parallel. This mode can be used to perform FFT/IFFT on two sets of independent data at the same time or two-dimensional FFT/IFFT on one set of data.

2. FIR pulse group processing

The basic function of FIR pulse group processing is a matrix operation, and its basic formula is: Y=H*X

Where: X=(X ₀ , X ₁ ,...,X _N□1 ) ^T , Y=(Y ₀ , Y ₁ ,...,Y _M□1 ) ^T (N≥ M)

The matrix operation of the above formula can be regarded as a multiplication and accumulation operation in realization. If the operation of one row of the H matrix (hereinafter also referred to as "coefficient matrix") and one column of X matrix (hereinafter also referred to as "data") is observed separately and the operation data is complex, the basic operation form is multiplication and accumulation, and the expression is :

It can be seen that the FIR pulse group processing actually has i groups of multiplication and accumulation operations, and each group includes j times of multiplication and j-1 times of accumulation.

In addition to the basic form of FIR pulse group processing, the present invention proposes several extended forms of FIR pulse group processing: sliding FIR pulse group processing, FIR pulse group processing in parallel with two sets of data, and two-channel addition form of FIR pulse group processing wait. Regardless of the basic form or the extended form, in the working mode of FIR pulse group processing, the hardware resources in the four basic units (basic_unit) will be configured as the organizational form shown in FIG. 5 .

In the organizational form shown in Figure 5, the four complex multiplication accumulators in the "complex multiplication and accumulation sub-array A" together with the "complex multiplication and accumulation accumulator A" form a "parallel multiplication and accumulation array 1"; "complex multiplication and accumulation sub-array B" The 4 complex multiplication accumulators together with the "complex multiplication accumulator B" form a "parallel multiplication accumulation array 2". In the "parallel multiplication and accumulation array", one complex multiplication accumulator is used for FIR pulse group to process one channel (two channels in the conjugate case) operation, such a "parallel multiplication and accumulation array" can process five channels in parallel (conjugated 10 channels in case of conjugation), so 1 basic unit can process 10 channels in parallel (20 channels in conjugate case). Therefore, when the input data rate is equal to the chip operation clock, the four basic units can complete 80 channels of FIR pulse group processing in parallel at most. If the "parallel multiplication and accumulation array" is multiplexed, a maximum of 128 channels of FIR pulse group processing can be completed.

The coefficients processed by the FIR pulse group are stored in the coefficient memory shown in FIG. 2 . Each basic unit has 10 256×32bits dual-port RAM storage coefficients, and each multiplication unit is equipped with a dual-port RAM, which fixedly provides coefficients to a certain complex multiplication accumulator in the "parallel multiplication accumulation array". Such a multiplication The accumulator, together with the dual-port RAM supplying it with coefficients, constitutes a channel of FIR burst processing.

There are 8 dual-port RAMs of 512*40bits in each basic unit (basic_unit) as data memory. When the FIR pulse group is processed, the 8 dual-port RAMs are all used for data cache. In each basic unit, the data buffer receives the same data from the data input port. And add to each multiplication accumulator data input terminal and the coefficients of different channels for multiplication and accumulation operation.

The second hardware resource organization form of FIR pulse group processing is FIR pulse group processing of two sets of parallel data. In this form of organization, the first basic unit (basic_uint0) and the third basic unit (basic_uint2) are divided into one group, and the second basic unit (basic_uint1) and the fourth basic unit (basic_uint3) are divided into another Group. The "parallel multiplication and accumulation array" in the first group of basic units is used to process the data input from the "data input 1" port, and the "parallel multiplication and accumulation array" in the second group is used to process the data input from the "data input 2" port. data processing. The data memory and coefficient memory in the first group of basic units are used to store the first group of data and coefficients; the data memory and coefficient memory in the second group of basic units are used to store the second group of data and coefficients. In this way, a single-chip device can perform FIR pulse group processing on two sets of different data in parallel.

The mode of parallel operation of two groups of data is introduced above. In that mode, the hardware resources of the entire chip are divided into two groups, and each group processes a group of data independently. Similarly, when the number of channels is less than or equal to 40 and the filter length is greater than or equal to 80, in order to improve the calculation speed, the data to be processed can be divided into two segments according to 1/2 of the filter length. One section enters from the data input port 2, and then uses two groups of hardware resources in the chip to multiply and accumulate their respective coefficients at the same time, and then add the results of the respective multiplication and accumulation to obtain a complete processing result. This is the third hardware resource organization mode in the FIR pulse group processing working mode.

3. Related processing operations

其中N为滤波器运算长度。x_i为输入信号，h_i为滤波器对应的系数。The correlation processing operation refers to continuously intercepting N data from a continuously sampled data sequence in a sliding manner for filtering operation. Its operation characteristic is that there are N-1 pieces of data in the adjacent two groups of filtering operations that are the same. Its mathematical expression is:

Among them, N is the operation length of the filter. x _i is the input signal, and h _i is the coefficient corresponding to the filter.

The configuration of hardware resources in the basic unit in the relevant processing operation mode is shown in FIG. 6 . At this time, the multiplication accumulator inside the basic unit is constructed in a cascaded form. Each basic unit contains 10 floating-point complex multipliers. The output of the first complex multiplication accumulator is used as the input of the second complex multiplication accumulator, and is added to the second multiplication and accumulation result, and the addition result is used as the output of the second complex multiplication accumulator, which is input to the third In the complex multiplication accumulator, as an addend of the third addition operation...and so on, 10 complex multiplication accumulators are used in cascade. In this way, each basic unit (basic_unit) can be organized into a cascaded operation structure of 10 complex multiply-accumulators. By multiplexing the "concatenated multiply-accumulate array" for different times, 10*N points (N=1 , 2, 3...100) correlation calculation of filter length. In the same way, the cascading method is also adopted between the four basic units. The previous basic unit obtains the partial multiplication accumulation sum of related operations and sends it to the next basic unit as the first in the next basic unit "cascade multiplication accumulation array". Addends of complex multiply accumulators. In this way, the four basic units are successively accumulated and accumulated, and the final correlation operation result is generated in the fourth basic unit (basic_unit3).

Each basic unit of the device has data memory of the same capacity: 8 dual-port RAMs of 512×40bits. In the correlation operation mode, the data memory in each basic unit is uniformly addressed as a data cache. At data input, the data cache of each basic unit stores the same data. During operation, the data cache provides the same data to 10 cascaded complex multiplication accumulators in the same basic unit at the same clock beat.

The coefficients of correlation operations are temporarily stored in 10 dual-port RAMs of 256×32 bits in each basic unit. In the basic unit, each 32-bit dual-port RAM corresponds to a complex multiplication accumulator in the cascaded multiplication accumulation array, and provides coefficients to that complex multiplication accumulator fixedly. The characteristic of the storage of the coefficient sequence in the 10 dual-port RAMs is that the coefficients are sequentially stored in the 1st to the 10th dual-port RAMs in the order of h _n , h _n+1 ... h _n+9 . That is to say, for the same dual-port RAM, the serial numbers of the coefficients stored in the address n and address n+1 differ by 10. This is to accommodate the 10 complex multiply-accumulators in the cascaded multiply-accumulate array. Because on the pipeline of the cascaded multiply-accumulate array, 10 multiply-accumulate operations need to be performed in the same clock cycle, which requires the coefficient cache to provide 10 consecutive coefficients in the same clock cycle, so the coefficients are stored with this feature.

3. Scheduling method of hardware resources

The present invention adopts a two-level scheduling framework for the scheduling of hardware resources, and adopts a combination of centralized control and distributed control in the control method. Fig. 7 is a frame diagram of two-level scheduling of devices. Control words and control signals first enter the "global control" module for first-level decoding and control word distribution. In this module, the control word is received first, and then some global control signals are generated according to the control word. These global controls include: coordinating the actions of the four basic units, determining the output format of the operation results, and setting the on-chip master clock. The second function of the "global control" module is to transmit control information to the "local control" modules of each basic unit. Control signals and control words first enter the "global control" module, in this module, the control words related to various parameters of operation control are decoded and transmitted to each basic unit. The transmitted information includes: working mode, subtype of working mode, number of computing points, number of channels, number of processing channels, and so on.

After receiving the information transmitted by the global control module, the local control module in each basic unit (basic_unit) will perform two-level decoding on the information, and convert it into the details of the hardware scheduling control signal. For example, the opening and closing of some selection switches is determined according to the working mode and its type; how to store the coefficients and how to generate the coefficient memory address is determined according to the number of processing channels; the multiplexing times of the multiplication and accumulation array are determined according to the number of operation points, and then a certain register is determined Whether to update and update time and so on. The scheduling of hardware resources is divided into two levels, mainly for the sake of orderliness and simplicity in control. From an implementation point of view, it is clearer and more explicit.

Inside the basic unit, the method of arithmetic operation is used to decode the key parameters. Regardless of FFT/IFFT, FIR pulse group or related processing operations, the storage/retrieval addresses of data and coefficients, the multiplexing times of multiplication and accumulation arrays, etc. are all regular. On the basis of these laws, arithmetic operations can be used to The control word is decoded to obtain all control information and timing signals. For example, in the FIR pulse group operation, if the filter order is 40 and the number of points is also 40, then the dedicated decoding multiplier will calculate the coefficients that require a total of 40×40=1600 points. Then, when generating the coefficient write address, the write address of 0~1599 will be generated sequentially, and the coefficient will be written into the corresponding cache. Another reason for using the arithmetic operation decoding method is the compromise between the complexity of scheduling and the use of resources: first, the 8×8 fixed-point multiplier does not take up too many resources; second, if all the work of the processor The states are listed, and if decoding is implemented by look-up table, not only will there be a cumbersome and huge workload, but the resources occupied by the storage unit and look-up logic will also be considerable.

The control word adopted by the present invention for hardware resource scheduling has a total of 64 bits. Under the working modes of FFT/IFFT, FIR pulse group, and correlation operation, the description of the control word is shown in Table 1, Table 2, and Table 3 respectively.

control word name meaning and value chip_id(3:0) Concatenated number If not used, it can always be set to 0000. chip_num(3:0) The number of consecutive pieces If not used, it can always be set to 0000. chan_num(7:0) number of channels If not used, it can always be set to 00000000. work_model(4:0) Operating mode FFT: the value is 10000; IFFT: the value is 10010; FFT+IFFT: the value is 10011; dual-input data FFT: the value is 10100; dual-input data IFFT: the value is 10110. coeff_num(4:0) Number of coefficient groups If not used, it can always be set to 00000.

coeff_chan(4:0) coefficient channel If not used, it can be set to 00000. conj Conjugate selection If not used, it can be set to '0'. length(7:0) filter length The lower four bits length (3:0) represent the data length of the FFT/IFFT operation (that is, the number of points of a set of weighting coefficients). With the base 2, the positive integer value corresponding to length(3:0) is used as the exponent, and the obtained power is the length of the operation. Currently, the length codes that can be processed are: "1000"-256 points; "1001"-512 points; "1010"-1024 points; "1011"-2048 points; "1100"-4096 points. The value obtained by adding 1 to the positive integer value corresponding to length(6:4) represents the number of operation stages required for the large-point FFT/IFFT operation to be split into small-point radix-eight operations, and its value is related to the operation length. The operation of 256 points to 512 points requires three levels, and the corresponding code is "010"; the operation of 1024 points to 4096 points requires four levels, and the corresponding code is "011". The highest bit length (7) is temporarily unused and set to '0'. sel_coeff_ram(4:0) coefficient base During FFT/IFFT operation, the coefficient group can be replaced during the operation. The integer value corresponding to sel_coeff_ram(4:0) indicates a certain set of coefficients in the coefficient memory to be used. The optional value of the number of coefficient groups is related to the number of operation points. 4096 points have 2 groups of coefficients that can be changed, 2048 points have 4 groups, 1024 points have 8 groups, 512 points have 16 groups, and 256 points have 32 groups of coefficients that can be changed. That is, the value range of sel_coeff_ram is between "00000" and "11111". sel_data whether weighted In the FIR pulse group operation mode, select whether to weight the input data. The FFT mode is always set to '0'. sel_coeff_pp coefficient ping pong Whether the coefficients are ping-pong written when data is entered in two ways. No ping-pong, set to '0'; ping-pong, set to '1'. result1_mod(1:0) Output port 1 output mode There are 4 ways to output the result of the final result output port 1. This control word takes 00: output I/Q data; takes 01: outputs modulus value and phase angle; takes 10: outputs logarithm and phase angle; takes 11: outputs related cascade data. sel_AGC1(1:0) Output port 1 gain control The final result output port 1 can be output according to the format of the input data, and I/Q are 20-bit floating-point output respectively; it can also use the value of the control word GAC1 (3:0) as a standard to take a normalized floating-point value; I/Q can be converted into 20-bit fixed-point output. When sel_AGC1(1:0) is set to 00 or 11, floating-point output; when set to 01, the index is normalized to output; when set to 10, fixed-point output. AGC1(3:0) Normalized level of output port 1 When sel_AGC1=01 and 10, a reference index value needs to be determined, and AGC1(3:0) is the reference index value, which is used as the reference when the index is normalized or fixed-point output. result2_mod(1:0) Output port 2 output mode Similar to result1_mod(1:0). Take 00: output I/Q data; take 01: output modulus and phase angle; take 10: output logarithm and phase angle; take 11: output related cascade data. sel_AGC2(1:0) Output port 1 gain control Similar to sel_AGC1(1:0). Take 00, 11: floating-point output; take 01: index-normalized output; take 10: fixed-point output. AGC2(3:0) Normalized level of output port 1 Similar to AGC1(3:0). When sel_AGC2=01, 10, the output floating-point index takes the value of AGC2 as the reference, and performs index normalization or floating-point conversion to fixed-point processing.

Table 1

control word name meaning and value chip_id(3:0) Concatenated number Constantly set to 0000 in FIR mode. chip_num(3:0) The number of consecutive pieces Constantly set to 0000 in FIR mode. chan_num(7:0) number of channels The number of channels for FIR pulse group calculation. Determined according to the needs of use. For example, 50 channels are operated in parallel, then chan_num+1=50. work_model(4:0) Operating mode The value is 01000 in the FIR pulse group operation mode; the value is 00010 in the sliding FIR pulse group operation mode; the value is 00100 in the FIR pulse group mode of parallel operation of two sets of data;

The value of the FIR pulse group mode in which two channels are added is 00001; the FIR pulse group realizes the DFT mode, and the value is the same as the ordinary FIR pulse group operation mode, which is 01000, and the control word sel_data must be set to '1'. coeff_num(4:0) Number of coefficient groups Constantly set to 00000 in FIR pulse group mode. coeff_chan(4:0) coefficient channel Constantly set to 00000 in FIR pulse group mode. conj conjugate selection Whether the coefficient is conjugate in FIR pulse group mode. If the filter bank uses the coefficients of the channel conjugate, it is equivalent to doubling the operation speed. Set to '0', not conjugated; set to '1', conjugated. length(7:0) filter length The filter operation length in FIR pulse group mode, filter length N=length+1. sel_coeff_ram(4:0) Coefficient base address In the FIR pulse group mode, the coefficient of the operation process is changed to the base address. The upper 2 bits are always set to 00, and the lower 3 bits indicate which area of the coefficient memory to use the coefficient. sel_data Whether weighted In the FIR pulse group operation mode, select whether to weight the input data. '0', no weighting; '1' weighting. This control word is '1' if and only when the chip works in FIR pulse group to realize DFT operation. sel_coeff_pp coefficient ping pong In the FIR pulse group mode, it is fixed as '0' here. result1_mod(1:0) Output port 1 output mode There are 4 ways to output the result of the final result output port 1. This control word takes 00: output I/Q data; takes 01: outputs modulus value and phase angle; takes 10: outputs logarithm and phase angle; takes 11: outputs related cascade data. sel_AGC1(1:0) Output port 1 gain control The final result output port 1 can be output according to the format of the input data, and I/Q are 20-bit floating-point output respectively; it can also use the value of the control word GAC1 (3:0) as a standard to take a normalized floating-point value; I/Q can be converted into 20-bit fixed-point output. When sel_AGC1(1:0) is set to 00 or 11, floating-point output; when set to 01, the index is normalized to output; when set to 10, fixed-point output. AGC1(3:0) Normalized level of output port 1 When sel_AGC1=01, 10, it is necessary to determine a benchmark index value, and AGC1(3:0) is the benchmark index value, which is used as the benchmark when the index is normalized or fixed-point output. result2_mod(1:0) Output port 2 output mode Similar to result1_mod(1:0). Take 00: output I/Q data; take 01: output modulus and phase angle; take 10: output logarithm and phase angle; take 11: output related cascade data. sel_AGC2(1:0) Output port 1 gain control Similar to sel_AGC1(1:0). Take 00, 11: floating-point output; take 01: index-normalized output; take 10: fixed-point output. AGC2(3:0) Normalized level of output port 1 Similar to AGC1(3:0). When sel_AGC2=01, 10, the output floating-point index takes the value of AGC2 as the reference, and performs index normalization or floating-point conversion to fixed-point processing.

Table 2

control word name meaning and value chip_id(3:0) Concatenated number When multiple slices are used in cascading, the position of this slice on the cascading chain. For example: this chip is the third chip on the cascade chain, then chip_id+1=3. If used in a single chip, the chip_id is always 0000. Chip_num(3:0) Number of contiguous pieces When multi-chip cascading is used, it indicates how many devices there are in the cascading chain. For example: if there are 3 devices connected in cascade, then chip_num+1=3. If single chip is used, chip_num is always 0000. Chan_num(7:0) number of channels The value is between 00000000 and 00001111, which is determined according to the application requirements. For example, if 7 channels need to be operated in parallel, then chan_num+1=7.

Work_model(4:0) Operating mode The value in the relevant operation mode is 11000 coeff_num(4:0) Number of coefficient groups Indicates how many sets of coefficients are required for multi-channel operation. The value cannot exceed the current number of channels chan_num(7:0). For example, there are 3 sets of coefficients, then coeff_num+1=3. Coeff_chan (4:0) coefficient channel Correspondence between each group of coefficients and each channel. It is used together with the number of coefficient groups coeff_num and the number of channels chan_num. The relationship between the three is: coeff_chan+1=[(chan_num+1)/(coeff_num+1)]+1 that is, (coeff_chan+1) is (chan_num+1) divided by (coeff_num+1) and added 1. For example: chan_num+1=7, coeff_num+1=3, then coeff_num+1=3. The meaning expressed by Coeff_chan+1 is: the number of channels corresponding to each set of coefficients. For the above example, there are 7 channels, 3 sets of coefficients, adding 1 to the coefficient channel is 3, indicating that the 1st, 2nd, and 3rd channels match with the 1st set of coefficients, and the 4th, 5th, and 6th channels match with the 2nd set of coefficients. 7 channels are matched to the 3rd set of coefficients. Conj Conjugate selection Constantly set to 0 during correlation operations. Length(7:0) filter length Characterizes the filter length of the correlation operation (that is, the number of points of a set of coefficients). Let the window length be X, then, X=40*(length+1). Sel_coeff_ram(4:0) Read coefficient base address During the correlation operation, the coefficient memory is divided into two areas, and the coefficient can be replaced in real time during the operation. The upper 4 bits of Sel_coeff_ram(4:0) are always set to 0000, and the lowest bit indicates which area's coefficient is used. Sel_data whether weighted In the relevant operation mode, this is fixed as '0'. Sel_coeff_pp coefficient ping pong In the relevant operation mode, this is fixed as '0'. Result1_mod(1:0) Output 1 mode 00: result1 directly outputs I/Q; 01: result1 outputs modulus and phase angle; 10: result1 outputs logarithm and phase angle; 11: result1 is cascaded. Sel_AGC1(1:0) Output 1 gain control selection 00, 11: the gain of result1 is not processed; 01: the result of result1 is normalized by the index; 10: the result of result1 is converted from floating point to fixed point. AGC1(3:0) output 1 gain When the value of sel_AGC1 is 01 or 10, the index of the floating-point result 1 obtained by the operation is normalized according to the value of AGC1. Result2_mod(1:0) Output 2 mode 00: result2 directly outputs I/Q; 01: result2 outputs modulus and phase angle; 10: result2 outputs logarithm and phase angle; 11: result2 is cascaded. Sel_AGC2(1:0) Output 2 gain control selection 00, 11: the gain of result2 is not processed; 01: the result of result2 is normalized by the index; 10: the result of result2 is converted from floating point to fixed point. AGC2(3:0) output 2 gain When the value of sel_AGC2 is 01 or 10, the index of the floating-point result 2 obtained from the operation is normalized according to the value of AGC2.

table 3

The 64-bit control word is input through the coefficient input port coeff_in. The input mode is divided into 32-bit input and 16-bit input. The pins control_en1 and control_en2 are used as enable, and they are respectively sent when control_en1 and control_en2 are low. For 32-bit input, the function control word is divided into two groups, occupying all 32 bits of coeff_in(31:0), the low levels of control_en1 and control_en2 last for 1 coeff_en cycle respectively, and the function control word is sent during the coeff_en cycle when control_en1 is low The first 32 bits of the control word, send the last 32 bits of the control word in the coeff_en period when control_en2 is low. For 16-bit input, the function control word occupies the upper 16 bits of coeff_in(31:0), the low level of control_en1 and control_en2 lasts for 2 coeff_en cycles, and the first 32 bits of the function control word are sent within the 2 coeff_en cycles when control_en1 is low , Send the last 32 bits of the function control word in the 2 coeff_en cycles when control_en2 is low. The input timing of 32-bit control word and the timing sequence of 16-bit control word input are shown in Figure 11 and Figure 12.

On the general signal processing board with the present invention as the main processor, respectively carry out 1024 points of FFT calculation, 10-order FIR pulse group processing, 360 points of linear frequency modulation signal related calculation, its control word setting is as table 4, table 5, respectively. Table 6 shows.

control word name meaning and value work_model(4:0) Operating mode FFT: The value is 10000; length(7:0) filter length The lower four bits length (3:0) represent the data length of the FFT/IFFT operation (that is, the number of points of a set of weighting coefficients). With the base 2, the positive integer value corresponding to length(3:0) is used as the exponent, and the obtained power is the length of the operation. The value here is "1010", which corresponds to 1024 points. The value obtained by adding 1 to the positive integer value corresponding to length(6:4) represents the number of operation stages required for the large-point FFT/IFFT operation to be split into small-point radix-eight operations, and its value is related to the operation length. Here, the 1024-point calculation requires four levels, and the corresponding code is: "011". The highest bit length (7) is set to '0'. result1_mod(1:0) Output port 1 output mode There are 4 ways to output the result of the final result output port 1. Here the control word is 01, and the modulus value and phase angle are output. sel_AGC1(1:0) Output port 1 gain control The final result output port 1 can be output according to the format of the input data, and I/Q are 20-bit floating-point output respectively; it can also use the value of the control word GAC1 (3:0) as a standard to take a normalized floating-point value; I/Q can be converted into 20-bit fixed-point output. Take 10 here, fixed-point output. AGC1(3:0) Normalized level of output port 1 When sel_AGC1=01, 10, it is necessary to determine a benchmark index value, and AGC1(3:0) is the benchmark index value, which is used as the benchmark when the index is normalized or fixed-point output. The benchmark here is 1011.

Table 4

control word name meaning and value chan_num(7:0) number of channels The number of channels for FIR pulse group calculation. The rule is: number of channels=chan_num+1. Here is the 10th-order FIR pulse group operation, so chan_num is 00001001 work_model(4:0) Operating mode In the FIR pulse group operation mode, the value is 01000, here is the FIR pulse group operation mode, so it is set to 01000 conj conjugate selection Whether the coefficient is conjugate in FIR pulse group mode. If the filter bank uses the coefficients of the channel conjugate, it is equivalent to doubling the operation speed. Set to '1' here to select conjugation. length(7:0) filter length The filter operation length in FIR pulse group mode, filter length N=length+1. Here is the 10th-order FIR pulse group operation, so the length is set to 00001001 result1_mod(1:0) Output port 1 output mode There are 4 ways to output the result of the final result output port 1. Take 00 here: output I/Q data. sel_AGC1(1:0) Output port 1 gain control The final result output port 1 can be output according to the format of the input data, and I/Q are 20-bit floating-point output respectively; it can also use the value of the control word GAC1 (3:0) as a standard to take a normalized floating-point value; I/Q can be converted into 20-bit fixed-point output. Here sel_AGC1(1:0) takes 10, fixed-point output. AGC1(3:0) Normalized level of output port 1 When sel_AGC1=01, 10, it is necessary to determine a benchmark index value, and AGC1(3:0) is the benchmark index value, which is used as the benchmark when the index is normalized or fixed-point output. Here the benchmark GAC1 takes 0111

table 5

control word name meaning and value chip_id(3:0) Concatenated number When multiple slices are used in cascade, the position of this slice on the cascade chain. Single chip is used here, so chip_id is set to 0000. Chip_hum (3:0) Number of contiguous pieces When multi-chip cascading is used, it indicates how many devices there are in the cascading chain. Single chip is used here, so chip_num is set to 0000. Chan_num(7:0) number of channels The number of channels, the rule is: number of channels=chan_num+1. Here is a channel, so chan_num is set to 00000000 Work_model(4:0) Operating mode The value in the correlation calculation mode is 11000, here is the correlation calculation, and the work_model is set to 11000 coeff_num(4:0) Number of coefficient groups Indicates how many sets of coefficients are required for multi-channel operation. The value cannot exceed the current number of channels. There is only one set of coefficients here, so coeff_num is set to 00000 Coeff_chan (4:0) coefficient channel Correspondence between each group of coefficients and each channel. Here a group of coefficients corresponds to a channel, so coeff_chan is set to 00000 Length(7:0) filter length Represents the number of points for related operations. Let the window length be X, then, X=40*(length+1). Here is a 360-point correlation calculation, so the length is set to 00001001 Result1_mod(1:0) Output 1 mode Indicates the output mode of the result1 output port. Here result1_mod is set to 10, and result1 outputs logarithm and phase angle.

Table 6

Claims (2)

1, reconstructable digital signal processor, it is characterized in that: the hardware structure of processor inside and hardware line can carry out structural rearrangement by the configuration control word, thereby realize the filtering operation of fast fourier transform/invert fast fourier transformation, FIR arteries and veins group and relevant treatment form;

Hardware structure comprises input block, output unit, exchanges data unit and 4 elementary cells, comprises 160 real number floating-point multiplication totalizers in its elementary cell, and they are evenly distributed in 4 elementary cells;

Input block receives control word, control word is carried out one-level decoding, distribute control word to output unit, exchanges data unit and 4 elementary cells: input block comprises the control word receiver module, the one-level decoding module, the control word distribution module, the coefficient synchronization module, data simultaneous module, clock signal generation module in the sheet, control word and the coefficient 1 multiplexing same port that enters the mouth, the control word receiver module receives control word, send into the decoding of one-level decoding module then, produce overall control signal on the one hand and be used to produce sequential in the sheet, for coefficient and data provide synchronous, pass through the control word distribution module on the other hand respectively to output unit, exchanges data unit and 4 elementary cell emissions, the coefficient synchronization module carries out synchronously coefficient inlet 1 and coefficient inlet 2, and data simultaneous module is carried out synchronously data inlet 1 and data inlet 2;

The exchanges data unit is the switch combination of importing, exporting more a group more, swap data between 4 elementary cells;

Output unit sorts to the operation result of each elementary cell, and export according to different forms: output unit comprises elementary cell output sort result module, the module of taking the logarithm, floating-point/fixed point modular converter, ask the mould module, index normalization module, elementary cell output sort result module is arranged the output of elementary cell when working in FFT/IFFT and FIR arteries and veins group tupe according to channel order, will be from each elementary cell when working in the relevant treatment pattern, Shu Chu data are adjusted into the continuous data stream identical with importing data transfer rate frame by frame, ask the mould module to finish of the conversion of the output format of real part/imaginary part to the output format of mould value/phase angle, the module of taking the logarithm is converted to logarithm with the mould value of importing and represents, floating-point/fixed point modular converter is with real part/imaginary part or ask the output of mould module to be converted to fixed point format by floating-point format, index normalization module unifies to be fixed value by mantissa being done corresponding displacement with the index of the operation result of floating-point format, above-mentioned 4 kinds of format converting module have two covers respectively, the corresponding cover of each output port guarantees that two output ports are independently with any one form output;

Comprise data-carrier store in the elementary cell, the complex multiplication totalizer, complex multiplication totalizer submatrix, coefficient memory, sequential control circuit, data-carrier store comprises 8 512 * 40 two-port RAM, the input-buffer that is used for operational data, temporary and the operation result output buffers of intermediate results of operations, metadata cache can be added to each complex multiplication totalizer and complex multiplication totalizer submatrix to data simultaneously, coefficient memory comprises 10 256 * 32 two-port RAM, weighting coefficient when being used to store relevant treatment and FIR filter coefficient and FFT computing, the coefficient of FFT interative computation be one fixing, table with the special logic realization, corresponding 4 the real number floating-point multiplication totalizers of each complex multiplication totalizer, each complex multiplication totalizer submatrix comprises 16 real number floating-point multiplication totalizers, be equivalent to 4 complex multiplication totalizers, two complex multiplication totalizer submatrixs and complex multiplication totalizer are according to different mode matched combined, be used to finish different computings, the structure of real number floating-point multiplication totalizer is divided into 5 parts: the fixed-point multiplication part, the cut position part, the index adjustment member, the fixed point addition section, the index judgment part;

The organizational form of hardware can be recombinated by the configuration control word: by the configuration of control word and control signal, can change the organizational form of described 160 real number floating-point multiplication totalizers and exchanges data unit, make it to select different mode of operations, to adapt to three kinds of different processor active tasks: FFT/IFFT, the processing of FIR arteries and veins group, related operation;

Take corresponding organizational form when doing three kinds of filtering operations, be respectively:

When doing the FFT/IFFT computing, two complex multiplication totalizer submatrixs are respectively as the node of an interative computation of basic 8 algorithms, 4 complex multiplication totalizers in each complex multiplication totalizer submatrix are used to finish one-level base 8 interative computations: that complex multiplication totalizer of each complex multiplication totalizer submatrix front is as the windowing arithmetical unit, data are carried out windowing process, data after the windowing enter this complex multiplication totalizer submatrix and carry out one-level base 8 interative computations, the output of each grade interative computation at first imports metadata cache, and then deliver to complex multiplication totalizer submatrix in the corresponding another one elementary cell by the exchanges data unit, to carry out the next stage interative computation;

When doing the processing of FIR arteries and veins group, in parallel use of parallel multiplication in 2 complex multiplication accumulator module of elementary cell inside and 2 the complex multiplication totalizer submatrix modules, a channel of the corresponding FIR arteries and veins of each complex multiplication totalizer group, corresponding 2 channels during conjugate operation;

When carrying out related calculation, complex multiplication totalizer and the series connection of complex multiplication totalizer submatrix are used, and 10 complex multiplication totalizers are equivalent to connect.

2, reconstructable digital signal processor as claimed in claim 1 is characterized in that: the hardware scheduling scheme that is adopted is,

The hardware scheduling scheme is taked the centralized and distributed two-level scheduler method that combines: control word and control signal at first enter global control module and carry out one-level decoding and control word distribution, in this module, at first receive control word, produce overall control signal according to control word then, comprise: coordinate the action of 4 elementary cells, the output format of decision operation result, setting to major clock in the sheet, second effect of global control module is the Local Control Module emission control information to each elementary cell, comprising: mode of operation, the subtype of mode of operation, computing is counted, number of channels, the number of treatment channel;

Local Control Module in each elementary cell carries out two-stage decode to these information after the information of receiving the global control module emission, be converted into the details of hardware scheduling control signal.

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