CN100585629C - Analog processors including quantum devices - Google Patents

Abstract

An analog processor for solving a variety of computational problems is provided. Such analog processors include multiple quantum devices arranged in a lattice with multiple coupled devices. The analog processor further includes bias control systems each configured to apply a locally effective bias to a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next nearest neighbor quantum devices. The analog processor further includes a plurality of coupling control systems, each configured to adjust a coupling value of a corresponding one of the plurality of coupling devices. Such a quantum processor further includes a set of readout devices each configured to measure information from a corresponding quantum device of the plurality of quantum devices.

Description

Analog processors including quantum devices

related application

This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/638,600, filed December 23, 2004, which is hereby incorporated by reference in its entirety. This application also claims priority under 35 U.S.C. Section 119(e) to U.S. Provisional Patent Application No. 60/705,503, filed August 23, 2005, which is also incorporated herein by reference in its entirety.

technical field

The present methods, articles and systems relate to analog processing and quantum computing devices.

Background technique

2.1 Simulation calculation

Simulation computing uses physical phenomena (mechanical, electrical, etc.) to simulate the problem of interest by using physical quantities (pressure, voltage, position, etc.) to represent variables in the problem, here the problem is some abstract mathematical problem or some physical problem involving other physical quantities. In its simplest form, a simulation system (such as an analog computer) solves a problem by taking one or more input variables of the problem, representing them as physical quantities, and then deducing its state according to the laws of physics. The answer to the question is generated as a physical variable which can then be read out.

Analog systems have two advantages. The first advantage is that operations are performed in a truly parallel fashion. Because operations are generally governed by the laws of physics, there is nothing in the physical laws of most simulated systems that would prohibit one operation in one part of the simulated system while at the same time prohibiting another in another part of the simulated system. operation. A second advantage is that the analog system does not involve time domain operations and thus does not require the use of clocks. Multiple analog systems perform calculations in real time, which is faster for most physics applications than performing the same calculation on a digital computer.

Traditionally, analog systems use some physical quantity (such as voltage, pressure, temperature, etc.) to represent a continuous variable. This leads to a problem of precision, since the precision of the answer to the question is limited by the precision of the continuous variable that can be quantified. This is because simulation systems typically use physical quantities to represent variables in a problem, whereas physical quantities found in nature are inherently continuous. A digital computer, on the other hand, involves a distinction between possible word bit values "0" and "1" for which there is an easily identifiable exact state. Simulation systems also tend to be limited in the types of problems they can solve. For example, a sundial and a compass were primitive analog computers. However, both are capable of only one calculation, calculating time from the position of the sun and calculating the direction of Earth's magnetic field, respectively. A digital computer can solve both problems by reprogramming a computer of its kind. Analog systems tend to be more complex than digital computers. Also, the number of operations an analog system can perform is often limited by the degree to which the circuit/device can be replicated.

Although digital computers are useful for solving many general problems, there are still some problems whose answers cannot be computed efficiently on a conventional digital computer. In other words, the time to find the answer to the problem is not polynomially proportional to the size of the problem. In some cases it is possible to parallelize the problem. However, such parallelization is often impractical from a cost perspective. Digital computers use a finite state machine approach. Although the finite state machine approach works well for a wide variety of computational problems, it has a bottom line on the complexity of the problems it can solve. This is because the finite state machine approach uses a clock or timer to perform operations. Clocks implemented in state-of-the-art CMOS technology have a maximum clock rate (frequency) of about 5 GHz. In contrast, many analog systems do not require a clock. Answers to questions can thus be arrived at in an analog system in a natural way, often much faster, perhaps even exponentially faster, than their digital computing counterparts.

The demonstrated utility of digital computers lies in their low power consumption, the discrete, binary nature of easily distinguishable states, and their ability to solve a wide range of general-purpose computing problems. However, several specific problems in quantum simulation, optimization, NP-hard and other NP-complete problems are intractable on digital computers. An analog system can easily outperform a classical digital computer in solving important computational problems if the disadvantages of analog systems such as their finite accuracy limitations can be overcome.

2.2 Complexity categories

Computer scientists concerned with complexity routinely use different complexity class definitions. The number of complexity classes is always changing, as new complexity classes are defined and existing ones are merged in advances in computer science. Complexity classes known as polynomial-time (P), non-deterministic polynomial-time (NP), NP-complete (NPC), and NP-hard (NPH) are decision problems category. Decision problems have binary outcomes.

Problems in NP are computational problems for which there is a polynomial-time verification. That is, to verify a potential solution does not exceed polynomial time (category P) for the problem size. Generating a potential solution may take more than polynomial time. For NP-hard problems it may take longer to verify a potential solution.

A problem in NPC can be defined as a problem in NP that has been shown to be equally or harder to answer than a known problem in NPC. Equivalently, a problem in NPC is also a problem in NPH in NP. This can be expressed as NPC=NP∩NPH.

A problem is equivalent to or harder to answer than a known problem in NPC if there is a polynomial-time reduction of it from a known problem in NPC. Reduction can be seen as a generalization of mapping. The mapping can be a one-to-one function, a many-to-one function, or utilize oracles, among others. The concept of complexity categories and how complexity categories define the intractability of certain computational problems See, e.g., Garey and Johnson, 1979: Computer and Intractability: A Guide to the Theory of NP-Completeness, Freeman, San Francisco, ISBN : 0716710455 (hereinafter referred to as "Garey and Johnson"). See also Cormen, Leiserson, and Rivest, 1990: Introduction to Alrorithms, MIT Press, Cambridge, ISBN: 0262530910.

Decision problems often have an associated optimization problem that is solved to define the correct decision. The efficiency of solving a decision-based NP-complete problem leads to the efficiency of solving the corresponding optimization-based problem. This is generally true for any problem in NP. Often the problems it is solving for are optimization-based problems.

2.3 Quantum devices

Quantum computing is a relatively new method of computing that uses quantum devices to exploit quantum effects, such as superposition of ground states and entrainment of quantum devices, to perform certain calculations faster than classical digital computers. In digital computers, information is stored in bits, which can be either "0" or "1". For example, a word bit can have a low voltage representing a logic "0" and a high voltage representing a logic "1". As opposed to the bits of a digital computer, a quantum computer stores information in quantum bits (qubits), quantum devices in which data can either be in a "0" state or a "1" state, or a combination of those states. any overlay,

α|0>+β|1>.(1)

In terms of Eq. (1), the "0" state of a digital computer is analogous to the |0> ground state of a qubit. Similarly, the "1" state of a digital computer is analogous to the |1> ground state of a qubit. According to equation (1), a qubit allows the superposition of ground states of multiple qubits, where the qubit has a certain probability to be either in the |0> or |1> state. The term |α| ² is the probability of being in the |0> state and the term |β| ² is the probability of being in the |1> state, where |α| ² + |β| ² =1. Clearly the continuous variables α and β contain much larger information than a bit in a digital computer, which is simply a 0 or 1. The state of a qubit can be represented as a vector,

$\left[\begin{array}{c}\mathrm{<span\; class="notranslate">\; \&alpha;</span>}\\ \mathrm{<span\; class="notranslate">\; \&beta;</span>}\end{array}\right]<span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Although the qubit can be in a linear combination (or superposition) of states, it can only be read or measured as being in the |0> or |1> state. Quantum devices exhibit quantum properties such as quantum tunneling between quantum ground states, superposition of ground states, involvement of qubits, coherence, and simultaneous fluctuating and granular properties. In a standard model of quantum computing (also known as the circuit model of quantum computing), the operation of quantum gates in a quantum computing device is performed in the time domain on qubits. In other words, individual gates in a quantum computing device operate on states on one or more qubits for a predetermined period of time to perform a quantum computation. Multiple gates are represented as a matrix multiplied by a state vector operating on the qubit. The most basic single-qubit gates are Pauli matrices:

$\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right]<span\; class="notranslate">\; ,</span>$ $\mathrm{<span\; class="notranslate">\; Y</span>}<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 0</span>}& <span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; i</span>}\\ \mathrm{<span\; class="notranslate">\; i</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right]<span\; class="notranslate">\; ,</span>$ $\mathrm{<span\; class="notranslate">\; Z</span>}<span\; class="notranslate">\; =</span>\left[\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& <span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right]<span\; class="notranslate">\; .</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Other single-qubit gates include Hadamard gates, phase gates, and π/8 gates. See, for example, Nielson and Chuang, 2000, Quantum Computation and Quantum Information, Cambridge University Press, Cambridge, pp. 174-177.

Two qubits coupled together also obey superposition:

α ₀₀ |00>+α ₀₁ |01>+α ₁₀ |10>+α ₁₁ |11>.(4)

The state of a two-qubit system is represented by a quaternion vector, and the operation of the two-qubit gate is represented by a 4×4 matrix. Thus an n qubit system is represented by a 2 ⁿ vector of continuous variables. A subset of elementary single-gate operations, such as those denoted in (3), and one or more two-qubit gate operations form a set of gates said to be common to quantum operations. A universal set of quantum operations is the set of any quantum operation that allows all possible quantum operations.

2.4 Requirements for Quantum Computing

In general, a qubit is a well-defined physical structure that (i) has multiple quantum states, (ii) can be coherently isolated from its environment and (iii) allows Quantum tunneling between two or more quantum states connected together. See, eg, Mooji et al., 1999, Science 285, p.1036 (hereinafter "Mooji"), which is hereby incorporated by reference in its entirety. For a review of current physical systems from which qubits can be formed see Braunstein and Lo (eds.), 2001, Scalable Quantum Computers, Wiley-VCH, Berlin (hereinafter "Braunstein and Lo").

In order for a physical system to behave as a qubit, several requirements must be met. See DiVincenzo in Braunstein and Lo, Chapter 1, Chapter 1. These requirements include that the physical system (qubit) needs to be scalable. In other words, it must be able to combine a reasonable number of qubits in a coherent manner. Associated with scalability is the need to eliminate qubit decoupling. For a qubit to be usable in quantum computing also requires operations that enable the qubit to be initialized, controlled, and coupled. The control of a qubit includes performing single-qubit operations as well as operations on two or more qubits. To support quantum computing, the collection of operations needs to be a general collection. Ensembles of multiple gates are common, see for example Barenco et al., 1995, Physical Review A 52, p. 3457, which is hereby incorporated by reference in its entirety. Another requirement for quantum computing is the ability to measure the state of the qubit in order to perform computational operations and extract information. These requirements are developed for circuit models of quantum computing and can be relaxed for other models.

2.5 Superconducting qubits

Several quantum computing hardware proposals have been proposed. Among these hardware proposals, the most scalable physical systems appear to be those of superconducting structures. Superconducting materials are materials that have no electrical resistance under critical current, magnetic field and temperature. A Josephson junction is an example of such a structure.

There are two main means of realizing superconducting qubits. One approach corresponds to confinement to a well-defined charge (charge qubit). Another approach corresponds to constraints on well-defined phases (phase/energy qubits). Phase and charge are related variables that, according to fundamental quantum principles, are gauge conjugates of each other. The division of these two types of devices is outlined in Makhlin et al., 2001, Reviews of Modern Physics 73, pp. 357-400 (hereinafter "Makhlin"), which is hereby incorporated by reference in its entirety. Superconducting qubits include devices well known in the art, such as Josephson junction qubits. See, for example, Barone and Paternò, 1982, Physics and Applications of the Josephson Effect, John Wiley and Sons, New York; Martinis et al., 2002, Physical Review Letters 89, 117901, which is hereby incorporated by reference in its entirety; and Han et al. ., 2001, Science 293, p.1457, which is hereby incorporated by reference in its entirety.

2.5.1 Flux qubits

One type of flux qubit is the constant current qubit. See Mooji and Orlando et al., 1999, Physical Review B 60, 15398-15413 (hereinafter "Orlando"), which is hereby incorporated by reference in its entirety. Superconducting phase qubits are well known and have demonstrated long coherence times. See, for example, Orlando and Il'ichev et al., 2003, Physical Review Letters 91, 097906 (hereinafter "Il'ichev"), which is hereby incorporated by reference in its entirety. Certain other types of phase qubits include superconducting loops with more or fewer than three Josephson junctions. See, eg, G. Blatter et al., 2001, Physical Review B, 63, 174511, and Friedman et al., 2000, Nature 406, 43 (hereinafter "Friedman 2000"), each of which is hereby incorporated by reference in its entirety. For more details on flux qubits, see the following U.S. Patents: 6,960,780 entitled "Resonant controlled qubit system", 6,897,468 entitled "Resonant controlled qubit system", 6,897,468 entitled "Multi-junction phase qubit" 6,784,451, 6,885,325 entitled "Sub-fluxquantum generator", 6,670,630 entitled "Quantum phase-charge coupled device", 6,822,255 entitled "Finger squid qubit device", 6,979,8 entitled "Superconducting low induction qubit" the following published U.S. patent applications: No. 2004-0140537 entitled "Extra-substrate control system", No. 2004-0119061 entitled "Methods for single qubitgate teleportation", No. 2004-019061 entitled "System and method for controlling superconducting qubits" No. 0016918, No. 2004-0000666 entitled "Encoding and error suppression for superconducting quantum computers", No. 2003-0173498 entitled "Quantum phase-charge coupled device", No. 6903-01 entitled "Quantum computing integrated development environment" No. 2003-0121028 of "Quantumcomputing integrated development environment", No. 2003-0107033 entitled "Trilayer heterostructure junctions", and No. 2002-0121636 entitled "Quantum bit with a multi-terminal junction and loop with a phaseshift", they Each is hereby incorporated by reference in its entirety.

FIG. 1A shows a superconducting phase qubit 100 . Phase qubit 100 includes a loop 103 of superconducting material interrupted by Josephson junctions 101-1, 102-2, and 103-3. Josephson junctions are typically formed using standard fabrication processes, generally involving material deposition and photolithography stages. See, for example, Madou, 2002, Fundamentals of Microfabrication, Second Edition, CRC Press, Van Zant, 2000, Microchip Fabrication, Fourth Edition, McGraw-Hill, New York, Levinson, 2001, Principles of Lithography, The International Society for Optical Washingtoninghamering, Bell , and Choudhury, 1997, Handbook of Microlithography, Micromachining and Microfabrication Volume 1: Microlithography, The International Society for Optical Engineering, Bellingham Washington. Methods for fabricating Josephson junctions are described, for example, in Ramos et al., 2001, IEEE Transactions on Applied Superconductivity 11, p.998. Common substrates include, for example, silicon, silicon oxide, or sapphire. Josephson junction 101 may also include an insulating material, such as alumina. Examples of superconducting materials that can be used to form the superconducting loop 103 are aluminum and niobium. Josephson junction 101 has a size ranging from 10 nanometers (nm) to about 10 micrometers (μm). One or more Josephson junctions 101 have different parameters than the other Josephson junctions 101 in phase qubit 100 , such as junction size, junction surface area, Josephson energy, or charge flux. The difference between any two Josephson junctions 101 in a phase qubit 100 is characterized by a coefficient denoted α, which typically ranges from about 0.5 to about 1.3, where α=1 represents a Knot. In some examples, the condition α for a pair of Josephson junctions in the phase qubit is the ratio of the critical currents of the corresponding Josephson junctions. The critical current of a Josephson junction is the current flowing through the junction at which the junction is no longer superconducting. That is, below the critical current the junction is superconducting and above the critical current the junction is not superconducting. Thus, for example, the condition a of junctions 101-10 and 101-2 is defined as the ratio of the critical current of junction 101-1 to the critical current of junction 101-2.

Referring to FIG. 1A , a bias source 110 is inductively coupled to phase qubit 100 . Bias source 110 is used to pass a magnetic flux Φ _x through phase qubit 100 to provide control over the state of the phase qubit. Phase qubit 100 typically operates with a magnetic flux offset _Φx in the range of about 0.2· _Φ0 to about 0.8· _Φ0 , where _Φ0 is the flux quantum.

Phase qubit 100 has a simplified two-dimensional potential with respect to phase across Josephson junction 101 . The phase qubit Φ100 is typically biased by a magnetic flux Φx such that the characteristic curve of the two-dimensional potential energy includes regions of local energy minima where the local energy minima are separated from each other by small energy barriers and by large The Power Barrier is separate from the other areas. The potential energy is a double well potential 150 (FIG. 1B) comprising a left well 160-0 and a right well 160-1 representing clockwise 102-1 and anticlockwise 102-1 in the phase qubit of FIG. 1A, respectively. The hour hand 102-1 circulates a superconducting current. A double well potential 150 can be formed when a flux bias of about _0.5Φ0 is applied.

When the double wells 160-0 and 160-1 are degraded or nearly sharpened, meaning they are at or near the same energy potential, as shown in FIG. 1B , the quantum state of the phase qubit 100 becomes into a coherent superposition of phases, or fundamental states, and the device can operate as a phase qubit. The point at or near sharpening is referred to herein as the computational operating point of phase qubit 100 . During a computational run of the phase qubit 100, controllable quantum effects can be used to process the information stored with the phase state according to the rules of quantum computing. Because the quantum information stored and processed in the phase qubit is based on phase bits, it is insensitive to charge-based noise. Il`ichev et al. (Illichev) used a three-Josephson junction flux qubit coupled to a high-quality tank circuit for continuous observation of Rabi oscillations.

Standard quantum computing models have multiple problems that make this a challenging feat of science and technology. Quantum computing involves coherently processing quantum information. This requires sufficiently long decoupling times in the qubit while being free from noise and errors. Decoherence makes standard-model quantum computation at the time-domain gate level difficult. Therefore, it is hoped that quantum effects, such as incoherent tunneling, can be harnessed to solve useful problems and overcome the challenges of standard model quantum computing.

Contents of the invention

(i) An aspect of the methods, articles and systems provides a computing system comprising an analog (quantum) processor. The quantum processor includes a plurality of quantum devices forming nodes of a lattice, the quantum devices having first and second fundamental states and comprising loops of superconducting material interrupted by Josephson junctions. The quantum processor further includes a plurality of coupling devices that couple the quantum devices together in a nearest neighbor and/or next nearest neighbor manner.

(ii) Another aspect of the methods, articles and systems provides a method for defining the result of a computational problem using a quantum processor comprising a plurality of quantum devices and a plurality of quantum devices coupled to Coupling device together. The method includes initializing the quantum processor to an initial state by setting a state of each of the plurality of quantum devices and setting a coupling strength of each of the plurality of coupling devices state, enabling the quantum processor to calculate a final state that approximates a natural ground state of the computational problem; and reading a final state from one or more of the plurality of quantum devices to define the computational problem the result of.

(iii) Yet another aspect of the methods, articles and systems provides a computer system comprising a central processing unit and a memory coupled to the central processing unit for defining a result of a computational problem. The memory includes a user interface module including instructions for defining the computational problem, a mapper module including instructions for generating a mapping of the computational problem, and an analog processor interface module. The analog processor interface module includes instructions for transmitting the mapping to an analog processor and instructions for receiving a result from the analog processor in response to the mapping. The analog processor includes a plurality of quantum devices and a plurality of coupling devices and the map includes an initialization value for each of the plurality of quantum devices and an initialization value for each of the plurality of coupling devices . The coupling means couple the quantum devices to their nearest neighbor and/or next nearest neighbor devices.

(iv) Yet another aspect of the methods, articles and systems provides a computer program product for use in conjunction with a digital computer. The computer program product includes a computer-readable storage medium and a computer program mechanism embedded therein, and the computer program mechanism includes a user interface module including instructions for defining a calculation problem, a mapper module components, including instructions for generating a map of the computational problem, and a simulated processor interface module, including instructions for transferring the map to a simulated processor and for receiving from the simulated processor in response to the map An instruction to receive a result. The analog processor includes a plurality of quantum devices and a plurality of coupled devices, and the map includes an initialization value for each of the plurality of quantum devices and an initialization for each of the plurality of coupled devices value, and the coupling device couples the quantum devices to their nearest neighbors and/or next nearest neighbors.

(v) Yet another aspect of the methods, articles and systems provides a quantum processor. The quantum processor includes a plurality of quantum devices arranged in a lattice, a first plurality of coupling devices, and a second plurality of coupling devices. A coupling device in the first coupling device couples a first quantum device closest to a second quantum device in the lattice, and a coupling device in the second plurality of coupling devices The coupling means couples a next nearest neighbor third quantum device to a fourth quantum device in the lattice.

(vi) Yet another aspect of the methods, articles and systems provides a quantum processor comprising a plurality of quantum devices, a first plurality of coupling devices, a second plurality of coupling devices, coupled to at least one A readout means for the quantum devices, and a local bias means coupled to at least one of the quantum devices. The plurality of quantum devices and the first plurality of coupling devices form a planar rectangular array, the planar matrix has a diagonal, and at least one coupling device in the first plurality of coupling devices has a coupling strength A first quantum device is coupled to the second quantum device, the coupling strength having a value in a range between a minimum negative coupling strength and a maximum positive coupling strength. At least one coupling device in the second plurality of coupling devices couples pairs along the array with a coupling strength having a value in the range between a minimum negative coupling strength and a zero coupling strength. A third quantum device arranged diagonally is coupled to a fourth quantum device.

(vii) Yet another aspect of the methods, articles and systems provides a computing system comprising a quantum processor. The quantum processor includes a plurality of qubit devices forming a plurality of nodes of a lattice, and a plurality of coupling devices. A first coupling device in the plurality of coupling devices couples a first qubit device to a second qubit device, the first qubit device and the second qubit device being in a close proximity neighbors or in a next-nearest neighbor configuration.

(viii) Yet another aspect of the methods, articles, and systems provides a quantum processor comprising a plurality of qubit devices arranged in a lattice, a first plurality of coupling devices, and a second plurality of a coupling device. A first coupling device in the first plurality of coupling devices couples a first qubit device to a second qubit device, the first qubit device and the second qubit device being configured as the nearest neighbors in the lattice, and a first coupling device in the second plurality of coupling devices couples a third qubit device to a fourth qubit device, the third qubit device and the first qubit device The four-qubit devices are configured as the next-nearest neighbors in the lattice.

(ix) Yet another aspect of the methods, articles and systems provides a method for defining the result of a computational problem using a quantum processor. The quantum processor includes a plurality of quantum devices and a plurality of coupling devices, each coupling device is coupled to a pair of quantum devices. The method includes initializing the quantum processor to an initial state by setting a state of each quantum device and setting a coupling strength of each coupling device, allowing the quantum processor to perform calculations approximating the A final state of a natural ground state of the problem, reading out a final state of at least one quantum device thereby defining the result of the computational problem, generating a carrier wave embodying a data signal including the result of the computational problem.

(x) Yet another aspect of the methods, articles, and systems provides a computer system comprising means for inputting a computational problem to be solved for P, NP, NP-hard problems, and NP-complete problems, for The computational problem is mapped onto a quantum processor comprising qubit devices and coupling devices for coupling nearest neighbor and next nearest neighbor qubit devices, using the quantum processor to obtain a solution to the computational problem means, means for outputting a solution of the computational problem, and means for transmitting the solution as a data signal embodied in a carrier wave.

(xi) In yet another aspect of the methods, articles and systems there is provided a digital signal embodied on a carrier including corresponding values at each of the plurality of nodes. The plurality of nodes is at least two nodes in a node lattice in a quantum processor. Each node in the node lattice is a quantum device. The value of at least one of the plurality of nodes individually or collectively represents the quantum process for a time pass after having been mapped on at least one portion of the lattice by means of a graph representing the computational problem The solution to a computational problem that has been solved by a computer. .

(xii) In yet another aspect of the methods, articles and systems there is provided a digital signal embodied on a carrier wave including an answer to a computational problem defined by evaluating values at each of a plurality of nodes. The plurality of nodes is at least two nodes in a lattice of nodes in a quantum processor, and each node in the lattice of nodes is a quantum device. The value of at least one node in the plurality of nodes is defined after operating the quantum processor a time after a graph representing the computational problem has been mapped on at least a portion of the lattice.

(xiii) Yet another aspect of the methods, articles, and systems provides a digital signal embodied on a carrier wave comprising a graph of a computational problem to be solved by the quantum processor, wherein the quantum processor includes a quantum The dot matrix of the device. The graph of the computational problem to be solved includes a plurality of nodes, and for each corresponding node of the plurality of nodes, an initial value of the corresponding node and a value between the corresponding node and another node in the plurality of nodes Corresponding coupling constants. The graph of the computational problem to be solved is configured such that it can be mapped onto the lattice of the quantum processor.

(xiv) Yet another aspect of the methods, articles and systems provides a digital signal embodied on a carrier wave comprising a computational problem to be solved by a quantum processor. The quantum processor includes a lattice of quantum devices. The computational problem to be solved is converted into a graph comprising a plurality of nodes and, for each corresponding node in the plurality of nodes, an initial value of the corresponding node and a corresponding A corresponding coupling constant between a node and another node. The graph of the computational problem to be solved is configured such that it can be mapped onto the lattice of the quantum processor.

(xv) A further aspect of the methods, articles and systems provides a graphical user interface for obtaining a solution to a computational problem and comprising a first display area and a second display area. The first display area indicates when a digital signal embodied on a carrier including a respective value for each of the plurality of nodes has been received. The plurality of nodes is at least two nodes in a lattice of nodes in a quantum processor, and each node in the lattice of nodes is a quantum device. A value at at least one of the plurality of nodes individually or collectively represents a time pass through the quantum processor after a graph representing the computational problem has been mapped onto at least a portion of the lattice The solution to the computational problem that has been solved.

(xvi) A further aspect of the methods, articles and systems provides a graphical user interface for obtaining a solution to a computational problem and comprising a first display area and a second display area. The first display area indicates when the digital signal embodied on a carrier of the answer to the calculation question has been received. The answer to the computational problem is defined by evaluating the value of at least one of the plurality of nodes. The plurality of nodes is at least two nodes in a lattice of nodes in a quantum processor, and each node in the lattice of nodes is a quantum device. The value of at least one node of the plurality of nodes is determined after computing the quantum processor at a time after a graph representing the computational problem has been mapped onto at least a portion of the lattice. The second display area displays the solution to the computational problem.

(xvii) A further aspect of the methods, articles and systems provides a graphical user interface for obtaining a solution to a computational problem and comprising a first display area and a second display area. The first display area indicates when a digital signal embodied on a carrier comprising a computational problem to be solved by a quantum processor has been generated. The quantum processor includes a lattice of quantum devices. The computational problem to be solved includes a plurality of nodes and, for each corresponding node in the plurality of nodes, includes an initial value for the corresponding node and a relationship between the corresponding node in the plurality of nodes and another node corresponding to a coupling constant. The computational problem to be solved is configured such that it can be mapped onto the lattice of the quantum processor. The second display area displays the solution to the computational problem after it has been received.

(xviii) Yet another aspect of the methods, articles and systems provides a computing system. The computing system includes a local computer, a remote computer, and a remote quantum processor in communication with the remote computer. The quantum processor includes a plurality of quantum devices, wherein each quantum device of the plurality of quantum devices is a node of a lattice, and wherein a first quantum device of the plurality of quantum devices has a first fundamental state and a second base state. The quantum processor further includes a plurality of coupling devices, a first coupling device of the plurality of coupling devices couples a first quantum device of the plurality of quantum devices to one of the plurality of quantum devices The second quantum device, wherein the configuration of the first quantum device and the second quantum device in the lattice is selected from the group consisting of a nearest neighbor configuration and a next nearest neighbor configuration. The local computer is configured to send a calculation problem to the remote computer. The remote computer is configured to send an answer to the computing problem to the local computer.

(xix) Yet another aspect of the methods, articles and systems provides a computer system for defining a result of a computational problem. The computer system includes a local computer, a remote computer and an analog processor. The local computer includes a central processing unit and a memory coupled to the central processing unit. The memory of the local computer stores a user interface module including instructions for defining the computational problem, a mapper module including instructions for generating a mapping of the computational problem, and a transport module wherein Instructions are included for sending the mapping to the remote computer. The remote computer includes a central processing unit and a memory coupled to the central processing unit. The memory of the remote computer stores a receive module including instructions for receiving the map from the local computer, and an analog processor interface module including instructions for sending the map to the analog processor. The analog processor includes a plurality of quantum devices and a plurality of coupled devices. The map includes an initialization value for at least one quantum device of the plurality of quantum devices and an initialization value for at least one coupling device of the plurality of coupling devices. A coupling device of the plurality of coupling devices couples a corresponding associated quantum device of the plurality of quantum devices to at least one of a nearest neighbor and a next-nearest neighbor of the associated quantum device.

(xx) Yet another aspect of the methods, articles and systems provides a computer system for defining a result of a computational problem. The computer system includes a local computer, a remote computer and an analog processor. The local computer includes a central processing unit and a memory coupled to the central processing unit. The memory of the local computer includes instructions for defining the computational problem, and a transmission module including instructions for sending the computational problem to the remote computer. The remote computer includes a central processing unit and a memory coupled to the central processing unit. The memory of the remote computer stores a receiving module including instructions for receiving the calculation problem from the local computer. A mapper module including instructions for generating a map of the computational problem, and an analog processor interface module including instructions for sending the map to the analog processor. The analog processor includes a plurality of quantum devices and a plurality of coupled devices. The map includes an initialization value for at least one quantum device of the plurality of quantum devices and an initialization value for at least one coupling device of the plurality of coupling devices, wherein one of the plurality of coupling devices is coupled to Coupling means couples a corresponding correlated quantum device of the plurality of quantum devices to at least one of a nearest neighbor and a next-nearest neighbor of the correlated quantum device.

Description of drawings

Figures 1A and 1B show a flux qubit and a corresponding double well potential energy curve according to the prior art.

Figure 2A illustrates a lattice with orthogonal coupling between nodes according to one embodiment of the present method, article and system.

Figure 2B shows a lattice with orthogonal and diagonal couplings between nodes according to one embodiment of the present method, article and system.

Figure 2C illustrates a lattice according to another embodiment of the present methods, articles and systems.

Figure 2D shows the lattice of Figure 2B rotated by 45° according to one embodiment of the present method, article, and system.

Figures 3A and 3B illustrate one embodiment of the present method, article and system for mapping a planar view of five nodes to corresponding lattice-based phantom volumes.

Figures 4A and 4B illustrate one embodiment of the present method, article and system for mapping a planar graph of six nodes to corresponding lattice-based simulation volumes with next-nearest neighbor couplings.

Figure 5 illustrates one embodiment of the present method, article and system for making multiple coupling devices and nodes equivalent to a single coupling device.

Figures 6A and 6B illustrate an embodiment of the present method, article and system for mapping a planar figure to a corresponding lattice-based phantom.

FIG. 7 shows a first set of five complete graphs K ₁ to K ₅ according to the prior art.

Figure 8 shows a K _3,3 two-part graph according to the prior art.

Figures 9A and 9B illustrate an embodiment of the present method, article and system for mapping a non-planar figure to a corresponding lattice-based phantom with next nearest neighbor coupling.

Figures 10A and 10B illustrate an embodiment of the present method, article and system for mapping a non-planar figure to a corresponding lattice-based phantom with next-nearest neighbor coupling.

Figure 11 illustrates a system operating in accordance with an embodiment of the method, article, and system.

Figures 12A and 12B illustrate one embodiment of the method, article and system for mapping a dot-based pattern to an integrated circuit.

13A and 13B illustrate another embodiment of the method, article and system for mapping a dot-based pattern to an integrated circuit.

14A and 14B illustrate another embodiment of the method, article and system for mapping a dot-based pattern to an integrated circuit.

Figure 15 shows a photograph of an ensemble of four quantum devices coupled to each other according to one embodiment of the method, article, and system.

Figure 16 shows a layout of an analog processor according to an embodiment of the method, article and system.

Figures 17A and 17B illustrate several embodiments of the present methods, articles and systems for controlling a double well potential.

Figure 18 shows a constant current qubit according to the prior art.

In these drawings, the same reference numerals indicate similar elements or actions. The size and relative positions of the various elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not drawn to scale, and some of these elements are arbitrarily enlarged and positioned for improved legibility. In addition, the specific shapes of these elements are drawn not intended to convey any information about the actual shape of the particular elements, but are chosen for ease of identification in the drawings. Moreover, while the drawings may show specific layouts, those skilled in the art will understand that changes may be made in design, layout, and manufacture, so that the layouts shown in no way constitute limitations on the layouts of the present methods, articles, and systems.

Detailed ways

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these details. In other instances, well-known structures associated with analog processors, such as quantum devices, coupling devices, and control systems including microprocessors and drive circuits, have not been shown or described in detail to avoid unnecessarily obscuring the invention A description of the implementation. Unless the context requires otherwise, throughout the specification and appended claims, the word "comprises" and its conjugations should be interpreted in an open, implicit sense, meaning "including, but not limited to "the meaning of. References throughout this specification to "an embodiment", "an embodiment" or "an alternative", "an alternative" mean that a specific feature, structure or characteristic described is included in the In at least one embodiment of the invention. Thus appearances of such expressions in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. The subheadings herein are for convenience only and do not explain the scope and significance of the claimed invention.

Analog processors are described according to the present methods, articles and systems. In some embodiments, the analog processor includes a plurality of quantum devices arranged in a lattice and a plurality of coupling devices coupling the quantum devices together. In certain embodiments, the coupling device couples an individual quantum device of the plurality of quantum devices to its nearest neighbor and/or next nearest neighbor. In some embodiments, the analog processor is capable of approximating solutions to some problems that fall into the class of NP (non-defined polynomial time) problems.

The NP class of problems are those that can be verified in polynomial time with a non-defined Turing machine. Examples of NP-class problems include, but are not limited to, the Ising Spin Glass (ISG) problem, Maximum Independent Set, Max Clique, Max Cut, Vertex Cover ), the Traveling Salesperson (TSP) problem, k-SAT, integer linear programming, and finding an unbiased, non-tunneling spin glass ground state. These problems can all be surfaced on a graph where they are projected to consist of a vertex and an edge associated with that vertex. In general, each of these vertices and edges can have a different value or weight, and this makes the graph have different properties in terms of the relationship between the different vertices.

One computational problem that can be solved with an analog processor is the maximum independent set problem. Garey and Johnston defined the related independent set problem as follows:

Example: graph G=(V, E), positive integer K≤|V|.

Question: Does G consist of one or more independent sets of size K, i.e. is there a subset of V, $V^{\text{'}\text{'}}\&SubsetEqual;V,$ Have |V`′| ≥ K such that no two vertices in V` are connected by an edge in E?

What should be emphasized here is to show the difference between this maximum independent set and another problem called clique, which is explained below. Extending this definition, consider a non-directional edge-weighted graph with a set of vertices and a set of edges and a positive integer K less than or equal to the number of vertices of the graph. The independent set problem, hereinafter expressed as a computational problem, asks whether there is a subset of vertices of size K such that no two vertices in the subset are connected by an edge of the graph. There are several other variants of this problem and include optimization problems based on this computational problem. An example of an optimization problem is to identify the independent set of graphs that generate the maximum value of K. This is known as the largest independent set.

Mathematically, solving independent sets allows solving another problem called clique. The problem finds the clique in a graph. A clique is the collection of all interconnected vertices. Given a graph and a positive integer K, the question posed in the clique is whether there are K vertices all connected to each other (the vertices are also said to be "neighbors" to each other). Similar to the independent ensemble problem, the clique problem can be transformed into an optimization problem. The computation of cliques plays a role in economics and cryptography. Solving an independent set on a graph G ₁ = (V, E) is equivalent to solving a clique on the complement G ₂ = (V, (V×V)-E) of G ₁ ', for example, for the edge in E For all connected vertices, this edge is removed, and an edge connecting vertices not connected in G ₁ is inserted into G ₂ . Garey and Johnston define cliques as:

Example: graph G=(V, E), positive integer K≤|V|.

Question: Does G contain one or more cliques of size K, i.e. is there a subset of V, $V^{\text{'}\text{'}}\&SubsetEqual;V,$ Have |V`′| ≥ K such that every two vertices in V are connected by an edge in E?

Here, it should be emphasized to show the difference between this regiment and the independent assembly explained above. It can also be shown how cliques are related to the vertex cover problem. Likewise, all problems in NP-complete problems can be mutually reduced in polynomial time, so that a device that can efficiently solve one NP-complete problem is also likely to be used to solve other NP-complete problems.

For a graph G=(V, E) consisting of a set of vertices V and a set of edges E connecting pairs of vertices, the largest independent set M of G=(V, E) is the largest subset of V, None of them are connected by an edge in E. a maximally independent set $m\&SubsetEqual;V$ can be defined by minimizing the following objects:

$\mathrm{<span\; class="notranslate">\; E.</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&Element;</span>\mathrm{<span\; class="notranslate">\; V</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&lambda;</span>}\underset{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Element;</span>\mathrm{<span\; class="notranslate">\; E.</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

In the above formula, N is the number of vertices in V, i marks each vertex, (i, j) marks an edge between vertices i and j in E, and x is either 0 or 1. The indicator variable _xi is equal to 1 if node i is in M, otherwise it is equal to 0. The first term in formula (5) supports large sets M, while the second term can be seen as a compensation, which enforces the restriction that there are no vertices in M connected to each other by an edge. The factor λ acts as a kind of Lagrangian multiplier and weights the compensation term. For sufficiently large λ, we can be confident that this constraint is satisfied. In some examples, the Lagrangian term λ is equal to 2.

Each vertex in graph G can be represented by physical spins _si with values -1 and +1. However, in order to do this, a mapping of _xi to spin _si is required. Vertices existing in this graph G are defined to have spin +1 and nodes in G not existing in the maximum independent set solution M are defined to have spin -1. The mapping is defined as follows:

s _i =2x _i -1 (6)

Substituting formula (6) into formula (5) yields the following energy function

$\mathrm{<span\; class="notranslate">\; E.</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; the\; <figure-callout\; id="1"\; label="s"\; filenames="C2005800443480072H1.png,C2005800443480080H2.png"\; state="\{\{state\}\}">s</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; E.</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; \&Element;</span>\mathrm{<span\; class="notranslate">\; V</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; \&lambda;</span>}}{\mathrm{<span\; class="notranslate">\; 4</span>}}\underset{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Element;</span>\mathrm{<span\; class="notranslate">\; E.</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>$

where N is the total number of vertices in G, E is the total number of edges in G, and d _i is the total number of edges connected to vertex i. The solution to this maximum independent set problem can be obtained by minimizing formula (7).

Another instance of NP-like problems is the Ising spin glass (ISG) model, which is defined as:

$\mathrm{<span\; class="notranslate">\; E.</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; +</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}\underset{\mathrm{<span\; class="notranslate">\; j</span>}<span\; class="notranslate">\; ></span>\mathrm{<span\; class="notranslate">\; i</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; J</span>}}_{\mathrm{<span\; class="notranslate">\; ij</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

where s ₁ to s _N are the values of the corresponding node s, J _ij represents the value of the coupling between the s _i and s _j nodes, and h _i represents the bias on the corresponding node _ni . To arrive at a solution to the maximum independent set problem, formula (8) is restricted such that the coupling (J _ij ) has a value of +λ/4 if there is an edge between nodes i and j, and if node i There is no edge between j and j then the coupling (J _ij ) has a value of 0, and the node bias h _i has a value of +a, where defined from equation (8) a should be

An example of an NP-like problem represented by a graph is the Traveling Sales Person (TSP) problem. In this TSP problem, different cities are represented by vertices, and roads between these cities are represented by edges. The solution to any special case of TSP is the shortest path that passes through all these cities exactly once.

The TSP problem provides an excellent illustration of the limitations of state-of-the-art digital computers. In this TSP problem, a mobile salesperson has to visit N cities once and only once, returning to the starting point at the end of the trip. The determination that must be made is the best route to take. Here, "optimum" depends on the given priority, but simply optimal can refer to the minimization of the total distance traveled. More realistically, "optimum" may refer to the minimization of some combination of flight time and cost. In physics terms, what is sought is the ground state solution or "minimum" of a complex system. That is, the TSP problem seeks the lowest energy configuration (or in this case, the lowest energy run). The number of possible trips depends on the number of cities present. For N cities, including the salesperson's home base, there are (N-1)! possible paths that visit each city only once: N-1 choices for the first city, N-2 choices for the next city, and so on. For N=10 cities, this isn't too bad: only 362,880 choices. It might not be too much work for a digital computer to calculate the cost of each of these trips and determine which is the least expensive. This technique is called "force" or "exhaustive search". However, as the independent variable N grows, the factorial function grows very rapidly. In fact factorial growth is faster than exponential growth. For N=20, N! ≈2×1018. Problems of this size would also take hours to compute for a massively parallel digital computer operating at a rate of 100 terabeats. For N=40, N! ≈8×1047, which is impossible to solve using existing digital computers using the exhaustive search method. An analog processor including multiple quantum devices and multiple coupled devices can be used to minimize the above problems.

5.1 Mapping

In some embodiments of the methods, articles, and systems, a user defines a problem, such as an NP-like problem, using a graph specification (e.g., a set of vertices and a set of edges), and an interface computer then processes the Input to define a mapping to a lattice. Here, a lattice is composed of a collection of quantum devices and couplings and can be a kind of grid. As used herein, a lattice is a regular, periodic arrangement of quantum devices. On the basis of this map, the analog processor is initialized, performs calculations, and reads the results back to the interface computer. The interface computer may be a digital computer. Examples of digital computers include, but are not limited to, a supercomputer, a cluster of computers connected by a computer network, and a desktop computer.

The ISG problem defined as the minimization of equation (8) above is an example of the class of NP problems that can be defined on a graph and fall into. See, for example, Lidar's paper in 2000, New Journal of Physics 6, p. 167, which is hereby incorporated by reference in its entirety. It has been shown that other NP-like problems can be mapped to this ISG problem in polynomial steps. See, for example, "Treating the Independent Set Problems by 2D Ising Interactions with Adiabatic; Quantum Computing," Wocjan et al., 2003, arXiv.org:quant-ph/0302027 (hereinafter "Wocjan"), which is incorporated by reference in its entirety at this. According to the present methods, articles and systems, an analog processor with quantum properties designed to approximate solutions to ISG problems and, by extension, mappable solutions to other NP-class problems is described.

The ISG problem is projected onto a two-dimensional lattice containing vertices (also called nodes). Lines (also known as edges) connect these nodes. For any given instance of the problem, an initial state for each node in the lattice, a weight for each node, and a weight for each edge can be specified. Each of these nodes has an information state. For any given configuration of edge weights and node weights on a lattice of size N×M, where N and M represent the number of nodes along the sides of the lattice, the ISG problem involves determining the Ground state. In some cases, any edge in the problem may have a weight around 0, meaning there is no connection between the corresponding nodes. Edge weights can be set to values ranging from J _C ^F to J _C ^AF , where magnitude J _C ^F is the maximum coupling value for possible ferromagnetic coupling between nodes, and magnitude J _C ^AF is the possible ferromagnetic coupling between nodes Maximum coupling value for antiferromagnetic coupling. In the alternative, J _C ^F may be less than zero while J _C ^AF is greater than zero. In another alternative |J _C ^F | is greater than |J _C ^AF |. In yet another alternative |J _C ^F | is equal to or nearly equal to |J _C ^AF |. See, for example, U.S. Patent Application No. 60/640,420, entitled "Coupling Schemes for Information Processing," and U.S. Patent Application No. 11/247,857, entitled "Coupling Methods and Architectures for Information Processing," each of which is incorporated herein by reference in its entirety.

Figure 2A illustrates one embodiment of the present methods, articles and systems for a four by four rectangular lattice 200, having nodes N1 through N16 and couplings J1-2 through J15-16, for a total of 24 couplings. A coupling Ji-j connects node Ni to node Nj. For example, coupling J3-4 connects nodes N3 and N4. The nodes may represent the vertices of a graph problem, and the couplings may represent the edges of the graph problem. For clarity and to emphasize numbering conventions, only a subset of all nodes and couplings in lattice 200 are labeled in FIG. 2A. Subset 280 is a subset of lattice 200 that includes five nodes and four couplings. The central node in subset 280 has four nearest neighbor couplings, which is the highest number of nearest neighbor couplings for any node in lattice 200 .

Nodes on the perimeter of lattice 200 have only two or three nearest neighbors. Lattice 200 has a connectivity of four, since each non-perimeter node has four nearest neighbor couplings. In certain lattices used in the methods, articles and systems, the lattice has a connectivity of three, meaning that each non-peripheral quantum device has three nearest neighbor couplings.

Figure 2B illustrates one embodiment of a four by four rectangular lattice 202 having quantum devices N1 through N16 and a total of 42 coupled coupling devices J1-2 through J15-16 in accordance with the present methods, articles and systems . Each quantum device in the lattice 202 corresponds to a node N in the lattice 202 . For clarity and to emphasize numbering conventions, only a subset of all quantum devices and coupling devices in lattice 202 are labeled in FIG. 2B . Subset 282 is a subset of lattice 202 and includes nine quantum devices and twenty coupling devices. The central quantum device in subset 282 has four nearest neighbor couplings, such as J14-15, and four next-nearest neighbor couplings, such as J1-6 and J8-11, which are in lattice 202 The highest number of nearest neighbor couplings of any quantum device. Quantum devices on the perimeter of lattice 202 have only two or three nearest neighbors, and one or two next nearest neighbors, for a total of three or five couplings. Lattice 202 has a connectivity of eight, since non-perimeter quantum devices are coupled to eight neighbors.

Figure 2C shows another embodiment of a lattice according to the present methods, articles and systems. Two rectangular lattices with a connectivity of four are shown in FIG. 2C , one black 204 and the other 205 white. They are connected together by a diagonal edge, such as J2-17, which connects node N2 of lattice 205 to node N17 of lattice 204. Thus, in such a structure, each node in each lattice 204, 205 is diagonally connected to another node in the other lattice. In other words, the structure is similar to having two rectangular lattices, one on top of the other, with each node in each lattice connected to the corresponding node in the other lattice, and then shifting one lattice diagonally . FIG. 2D shows another embodiment of a connectivity-eight lattice 206 with subsets 286 . It is structurally identical to that shown in Figure 2B, except that it is rotated by 45°. In some cases, the orientation of the lattice can be rotated by an arbitrary angle without loss of functionality. The dot matrix 204, 205 of FIG. 2C can be mapped onto the dot matrix 206 of FIG. 2D without any difficulty.

Matrixes with connectivity other than 4 and 8 may be used, for example, matrixes with connectivity 2, 3, 5, 6, or 7 may be used. Lattice with connectivity less than 4 can be simulated on a matrix with connectivity of 4 by not using some couplings. For example, by not using any of the vertical couplings in FIG. 2A, lattice 200 becomes a connectivity-two lattice. Similarly, a matrix with connectivity less than 8 can be modeled on a matrix with connectivity 8 by not using some couplings. Sub-lattice 282 becomes a connectivity-six lattice, for example by not using the striped diagonal coupling in FIG. 2B. In some cases, some couplings may not be used by adjusting the corresponding coupling device so that the coupling strength of the coupling device is zero or close to zero.

Each quantum device in lattices 200 and 202 has a binary value and a locally effective bias that falls between about 100 x J _C ^F and about +100 x J _C ^AF . ^Additionally , each coupling device in lattice 202 has a value ranging from JCF to _JCAF . The absolute values of J _C ^F and J _C ^AF may be between about 30 milliKelvin (mK) and about 10 Kelvin (K), or, alternatively, the absolute values of J _C ^F and J _C ^AF may be Between about 100mK and about 1.5K. Although the true unit of J is energy, this unit can be converted to an equivalent measure of temperature, for example in Kelvin, according to the formula E= _kB T, where _kB is Boltzmann's constant. This locally effective bias can be applied simultaneously to each quantum device in lattices 200 and 202, such that more than one quantum device is biased at the same time.

3A and 3B illustrate one embodiment of the present method, article and system for use in a network with five nodes N1-N5 and four couplings (J1-3, J2-3, J3-4, J3-5). Conversion between an arbitrary planar graph 300 (FIG. 3A) and a dot-matrix-based layout 301 with four connectivity (FIG. 3B). The nodes of Figure 3A correspond to the quantum devices of Figure 3B with the same reference numerals. Figure 3B shows a nine quantum device embodiment where five quantum devices, namely N1 to N5, are active and four quantum devices are inactive. The quantum devices defined by the dashed lines in Figure 3B are inactive quantum devices, one of which is denoted by N', which are isolated from the rest of the quantum devices of the system. An inactive quantum device is isolated from an active quantum device by setting the coupling value of the coupling of the inactive quantum device to an adjacent quantum device to zero. It should be noted that, for clarity and to preserve geometry, the reference numerals of FIG. 3A are retained in FIG. 3B, moving from the upper left of FIG. 3B to the lower right of FIG. 3B. In general, the mapping from an arbitrary planar graph to a lattice of four-connectivity is known and efficient. See eg Wocjan.

4A and 4B illustrate one aspect of the present methods, articles and systems for use in a network having six nodes N1-N6 and five couplings (J1-4, J2-4, J3-4, J4-5, J4 -6) planar graph 400 (FIG. 4A) to a point with nearest neighbor couplings (J2-4, J4-5, J3-4) and second nearest neighbor couplings (J1-4, J4-6) Transformation of matrix 402 (FIG. 4B). The nodes of FIG. 4A correspond to the quantum devices of FIG. 4B with the same reference numerals. A lattice utilizing nearest-neighbor coupling and next-nearest-neighbor coupling is a connectivity-eight topology based on the lattice. Figure 4B shows a six quantum device embodiment in which all six quantum devices, N1 through N6, are active. To embed the same pattern shown in Figure 4A (connectivity five) in a connectivity four lattice with only nearest neighbor coupling would require seven activations in a lattice of nine quantum devices quantum devices. Clearly, having the next nearest neighbor coupling as well as the nearest neighbor coupling leads to a more efficient and simpler mapping.

Every quantum device in the same graph as a given quantum device can be considered as a neighboring quantum device of the given quantum device. Alternatively, a nearest neighbor quantum device may be defined as any quantum device that is in the same graph as said quantum device and shares an edge with said quantum device. In another alternative, a next-nearest neighbor quantum device can be defined as any quantum device. In yet another alternative, a next-nearest neighbor quantum device can be defined as any quantum device that is two steps away in Manhattan distance. A Manhattan distance 1 is the distance between two nodes of an orthogonal two-dimensional graph separated by a single edge. For example, N5 and N6 of graph 402 are one step away from each other when measured in terms of Manhattan distance. In another example, N4 and N5 are two steps away from each other, the first step is from N5 to N6 and the second step is from N6 to N4. In graph 402, the nearest neighbor couplings are drawn as vertical and horizontal lines, eg, coupling J3-4, while the next nearest neighbor couplings are drawn with forty-five corners, eg, coupling J1-4. This assignment of nearest neighbor couplings as vertical and horizontal and next nearest neighbor coupling as diagonal is arbitrary. The nearest neighbor couplings can be drawn as vertical and horizontal edges and the nearest neighbor couplings as diagonal edges. For example, in this case N1 and N4 of graph 402 would be one step away by Manhattan distance, while nodes N1 and N3 would be two steps away by Manhattan distance. A corresponding pair of sub-nearest neighbor couplings may be crossing, eg, couplings J1-4, and J2-3 of graph 402, while the nearest neighbor couplings are not crossing. Alternatively, each next-nearest-neighbor coupling may be crossed with another next-nearest-neighbor coupling. In another alternative, a corresponding pair of nearest neighbor couplings may be crossed while the next nearest neighbor coupling is not.

A single coupling between two quantum devices can be mapped to one or more couplings between three or more quantum devices. Such a mapping is useful in a lattice-based layout where it is not possible to arrange the quantum devices next to each other. Figure 5 shows a first graph 500 comprising a simple coupling Ji-j between nodes Ni and Nj. Graph 502 shows a series of couplings Ji-1 to Jn-j that couple end nodes Ni and Nj by coupling intermediate nodes N1 to Nn. Nodes N1 to Nn are called convenience nodes, and are used to facilitate coupling between end nodes Ni and Nj when these end nodes cannot be arranged in adjacent positions in one lattice. One of coupling Ji-1 to Jn-j may appear to be a symbol coupling. In any planar graph 500, this sign takes the same sign as the coupling Ji-j, while the remaining couplings are fixed in a ferromagnetic coupling state. For example, consider the case where the sign of the coupling Ji-j in graph 500 is positive or antiferromagnetic, and the coupling Ji-1 in graph 502 has been considered to be coupled to this sign. Then, if the graph 502 is to represent the coupling Ji-j in the graph 500, set the coupling Ji-1 to be positive or antiferromagnetic, and set the remaining couplings in the graph 502 between the nodes Ni and Nj to be Negative or ferromagnetic. Also, consider the case where the sign of coupling Ji-j in graph 500 is negative or ferromagnetic and coupling Ji-1 in graph 502 is still considered to be a coupling of that sign. In this case, the sign of Ji-1 in graph 502 is set to be negative or ferromagnetic, while the remaining couplings are also set to be negative or ferromagnetic. Therefore, Ji-1 is sign coupled, and J1-1 to Jn-j are set to be negative or ferromagnetic. To facilitate the interaction, the nodes N1 to Nn are set to have zero active local field bias, so that they become passive nodes and transmit information between nodes Ni and Nj without interference. In both examples considered, one of the couplings in graph 502 is made the same as coupling Ji-j in 500, while all remaining couplings in graph 502 are set to be negative or ferromagnetic.

When making one of the couplings in graph 502 the same as the coupling Ji-j in 500, and all the remaining couplings in graph 502 are set to be negative or ferromagnetic, it can be done by using rf-SQUIDs or dc- SQUIDs (both explained below) achieve coupling. Alternatively, the couplings in graph 502 may all be direct galvanic connections such that node Ni is electrically connected to node Nj, in which case all individual couplings are ferromagnetic, and thus the total coupling Ji-j is ferromagnetic, and nodes Ni and Nj have the same quantum state. In another alternative, the couplings in graph 502 may include a hybrid of galvanic couplings, rf-SQUID couplings, and dc-SQUID couplings, in which case the rf-SQUID or dc-SQUID couplings One is equivalent to coupling Ji-j in 500, while all remaining couplings in graph 502 are negative or ferromagnetic.

Figures 6A and 6B illustrate another aspect for a planar graph 600 (Fig. 6A) An example of conversion to and from a lattice-based connectivity-four layout 602 (FIG. 6B). The nodes of Figure 6A correspond to the quantum devices of Figure 6B with the same reference numerals. FIG. 6A shows coupling J4-5 between nodes N4 and N5. Figure 6B shows a mapping implementation for a layout based on a lattice-based connectivity of four, and also shows that a sixth quantum device N6 is used as a convenience node (quantum device) to realize the quantum device N4 The coupling between J4-5 and N5. In FIG. 6B, N4 is connected to N5 through operative coupling J4-5. Active coupling J4-5 includes quantum device N6 and couplings J4-6 and J5-6.

When coupling J4-5 in graph 600 is antiferromagnetic, coupling J4-6 in lattice 602 can be assigned a magnitude with a positive sign, where the positive sign represents an antiferromagnetic coupling . The coupling J5-6 will then be assigned an appropriate magnitude with a negative value, which here indicates a ferromagnetic coupling. This will make the spin at N6 follow the spin at N5. In other words, the spin at N5 is copied to N6. Alternatively, coupling J5-6 of lattice 602 may be chosen as a sign coupling, thereby obtaining the same sign as coupling J4-5 in graph 600 (in this case the positive sign indicates an antiferromagnetic coupling) , and J4-6 can then be fixed as a ferromagnetic coupling. This will cause the spin at N6 to follow the spin at N4. In other words, the spin at N4 is copied to N6. In both instances, the quantum device N6 is a convenience quantum device and both apply a zero-effect local bias field so that the spin state at N6 can track its ferromagnetically coupled quantum The spin state of the device.

The methods, articles, and systems provide for embedding non-planar graphics into a two-dimensional grid-based layout by utilizing nearest-neighbor and next-nearest-neighbor coupled vertices in the grid-based layout. As is well known in the art, a complete graph with n vertices denoted by _Kn is a graph with n vertices in which each vertex is connected to every other vertex by an edge between each pair of vertices Each of them is connected. The first five complete patterns, K ₁ to K ₅ , are shown in FIG. 7 . As defined herein, a non-planar graph is a graph that includes the complete graph K ₅ or the two-part graph K _3,3 as a subgraph. A graph is bipartite if its vertices can be divided into two disjoint subsets U and V such that each edge connects a vertex in U to a vertex in V. A two-part vertex is a complete two-part graph if every vertex in U is connected to every vertex in V. If U has n elements and V has m elements, the resulting complete two-part graph is denoted by K _n,m . Figure 8 shows a K _3,3 two-part graph. Any non-planar graph is an extension of either K ₅ or K _3,3 . Extend the graph by adding edges and nodes. Planar arrays can be rectangular. Example applications include the paradigm of solving a problem defined on a non-planar graph embedded in a planar array with nearest-neighbor and next-nearest-neighbor couplings.

FIGS. 9A and 9B illustrate a non-planar graph 901 with five nodes N1-N5 and ten couplings and pairs with nearest neighbor and second nearest neighbor connections (in FIG. 9A and 9B, only the transition between a dot-based layout 951 (FIG. 9B) for couplings specifically described below) is shown. The next nearest neighbor couplings in FIG. 9B are those couplings at a 45 degree angle in FIG. 9B , such as coupling 970 . Lattice 951 includes sixteen quantum devices, twelve of which (N1-N12) are active, ie connected to at least one other quantum device. The specific pattern shown in Fig. 9A is called a K5 pattern. It is a fully connected graph at five nodes, meaning that every node in the graph is connected to every other node in the graph. K5 is the smallest non-planar graph. Any graph that includes _K5 as a subgraph will also be non-planar. The K ₅ pattern 901 shown in FIG. 9A can be embedded into a dot matrix, such as the rectangular dot matrix 951 shown in FIG. 9B . Similarly, any pattern that has _K5 as a sub-pattern can be embedded in a lattice, like lattice 951. The inactive node, N', in Figure 9B is shown with a dashed line and is isolated from the rest of the system. In practice, an inactive quantum device is isolated from an active quantum device by setting the coupling value of an adjacent coupling, e.g., coupling 971, to zero or more generally to a negligible value .

The convenient quantum device is used to perform the transformation from a flat figure to a two-dimensional lattice layout. The conversion from non-planar graph 901 to two-dimensional lattice 951 is an isomorphism of quantum device, antiferromagnetic coupling plus quantum device using convenience, and ferromagnetic coupling. Nodes N1 - N5 in graph 901 correspond to quantum devices N1 - N5 in lattice 951 . Symbolic couplings between nodes correspond in part to edges in graph 901 . Edges in graph 901 are represented by signed and ferromagnetic couplings in lattice 951 . A symbolic coupling is represented by a bold solid line between a pair of quantum devices in lattice 951 , eg coupling 973 . Ferromagnetic couplings, such as coupling 972 , are represented by bold dashed lines in matrix 951 . Each ferromagnetic coupling in lattice 951 passes through a convenience quantum device. The convenient quantum devices in lattice 951 include quantum devices N6 to N12 and can be discerned in lattice 951 because they are formulated as lattice. The local field bias of each convenience quantum device can be set to zero. The convenience quantum device cooperates with this ferromagnetic coupling to propagate a sign coupling. For example, the convenience quantum device N12 propagates the symbol coupling 973 with the ferromagnetic coupling 980 .

Each symbol coupling in a two-dimensional lattice layout (eg, layout 951) can be either a ferromagnetic or an antiferromagnetic coupling. Alternatively, each symbol coupling in a two-dimensional lattice layout can be an antiferromagnetic coupling.

Figures 10A, 10B illustrate an example in which a non-planar _K3,3 graph 1001 (Figure 10A) with six nodes N1-N6 is embedded in a lattice-based layout 1051 ( In FIG. 10B ), the lattice-based layout has nearest-neighbor couplings and next-nearest-neighbor couplings. Lattice 1051 is a _K3,3 pattern embedded in a three by four array. Nodes N1 to N6 in graph 1001 correspond to quantum devices N1 to N6 of lattice 1051 . The couplings (N1, N2), (N1, N4), (N3, N2), (N3, N4), (N3, N6), (N5, N4), and (N5, N6) in lattice 1051 are Antiferromagnetic couplings correspond to the edges of pattern 1001 and are marked by bold bold lines. For example, antiferromagnetic coupling 1070 in lattice 1051 couples N1 and N2 in lattice 1051 to corresponding edge 1020 in pattern 1001 .

Couplings (N1, N6) and (N5, N2) are each via a convenient node represented by a checkered pattern (N7, and N8, N10, N9, and N11, respectively) by a bold bold line (respectively is the antiferromagnetic coupling represented by (N1, N8) and (N5, N7)) and a set of thick dashed lines (respectively (N7, N2) and (N8, N10), (N10, N9), (N9 , N11) and (N11, N6)) represent ferromagnetic coupling for propagation. Convenience quantum devices, such as N7, N8, N9, N10, and N11, are quantum devices with zero local field bias that cooperate with ferromagnetic couplings to propagate an antiferromagnetic coupling. For the lattice 1051, eleven quantum devices are used to embed the pattern 1001, however, if the quantum devices N9 and N11 are bypassed by diagonal couplings (N8, N9) and (N9, N6), as few as nine quantum devices can be used. A quantum device is embedded in the graph 1001. An inactive quantum device N' is indicated by a dotted outline.

As for the K ₅ graph shown in Fig. 7, any non-planar graph with K _{3, 3} as a sub-graph can be embedded in a lattice such as 1051,

Figure 11 illustrates a system 1100 that operates in accordance with one embodiment of the present method, article, and system. System 1100 includes a digital computer 1102 that includes

●At least one CPU 1110;

a main non-volatile storage unit 1120 controlled by a controller 1125;

A system memory 1126, preferably high-speed random access memory (RAM), is used to store system control programs, such as operating system 1130, data and application programs loaded from non-volatile storage unit 1120; system memory 1126 can also including read-only memory (ROM);

- a user interface 1114, including one or more input devices (eg, keyboard 1118, mouse 1116) and display 1112, and other optional peripheral devices;

- a network interface card (NIC) 1124 or other communications circuitry; and

• An internal bus 1106 is used to interconnect the aforementioned elements of the system 1100 .

System 1100 further includes an analog processor 1150 . Analog processor 1150 includes a plurality of quantum device nodes 1172 and a plurality of coupling devices 1174 . Although not shown in FIG. 11 , quantum device nodes 1172 and coupling devices 1174 may be arranged in a lattice-based connectivity-four layout, for example, as shown in FIGS. 2A, 3B, 6B, 12A, 12B, 13A and shown in 13B. Alternatively, quantum device nodes 1172 and coupling devices 1174 may be arranged in a lattice-based connectivity-eight topology, eg, as shown in Figures 2B, 4B, 9B, 10B, and 14B. As such, node 1172 and coupling device 1174 are equivalent in all respects to any node or coupling device shown and described with respect to these figures.

The analog processor 1150 further includes a readout device 1160 . Readout device 1160 may include a plurality of dc-SQUID magnetometers, where each dc-SQUID magnetometer is inductively connected to a different quantum device node 1172, and each dc-SQUID magnetometer is inductively connected to Measurements in readout device 1160, from which NIC 1124 receives a voltage or current.

The analog processor 1150 further includes a coupling device control system 1164 including a coupling controller for each coupling device 1174 . ^Each respective coupling controller in coupling device ^control system 1164 is capable of adjusting the coupling strength of a corresponding coupling device 1174 in the range _JCF to _JCAF , where ^magnitude _JCF is the The maximum possible coupling value of ferromagnetic coupling between nodes, and the quantity J _C ^AF is the maximum possible coupling value of antiferromagnetic coupling between nodes. Analog processor 1150 further includes a quantum device control system 1162 including a controller for each quantum device node 1172 .

Several modules and data structures can be stored and processed by system 1100 . Typically, all or part of such data structures are stored in memory 1126 and such data structures and program modules are drawn as components of memory 1126 for convenience in representing various features and advantages of the present methods, articles, and systems. It should be understood, however, that at any given time, the programs and data structures shown in system memory 1126 may be stored in non-volatile storage unit 1120 . Furthermore, all or part of such data results and program modules may be stored on a remote computer not shown in FIG. 11 so long as the remote computer is addressable by digital computer 1102. Addressable means that there is some means of communication between the remote computer and digital computer 1102 such that a data network (e.g., the Internet, a serial connection, a parallel connection. Ethernet, etc.) A communication protocol (eg, FTP, telnet, SSH, IP, etc.) exchanges data between the two computers. Taking this into consideration, such data structures and program modules are described below.

Computer 1102 may be an operating system 1130 for handling various systems, such as file services, and for performing hardware-based tasks. A number of operating systems are known in the art that may function as the operating system 1130, including, but not limited to, UNIX, Windows NT, Windows XP, DOS, LINUX, and VMX. Alternatively, there may be no operating system and the instructions may be executed in a sequential chain.

The user interface module 1132 is used to assist a user in defining and executing problems to be solved on the simulation processor 1150 . In particular, the user interface module 1132 allows a user to define a problem to be solved by setting values of couplings J _ij between nodes and local biases h _i of such nodes, and adjusting run-time control parameters such as annealing schemes question. User interface 1132 also provides instructions for scheduling a computation and obtaining a solution to the problem. In particular, the calculated solution is collected as an output from the simulation processor 1150 . User module 1132 may or may not include a graphical user interface (GUI). When a GUI is not included, the user interface module 1132 receives a sequence of instructions defining the problem to be solved. The instruction series may be in the form of a macro language decomposed by the user interface module 1132 . These commands may be XML commands and the user interface module 1132 may be an XML interpreter.

The mapper module 1136 maps the computational problem to be solved defined by the user interface module 1132 into a specification of the corresponding problem that can be solved by the simulation processor 1150 . The mapper module 1136 can map the problem from an input graphical representation to the desired graphical representation required by the particular configuration of the simulation processor 1150 . The mapper module 1136 may include mapping a problem defined in a disconnectivity-eight representation to an equivalent problem defined in a connectivity-eight representation. The mapper module 1136 can map certain NP problems (eg, maximum independent set, maximum clique, maximum cut, TSP problem, k-SAT integer linear programming, etc.) into equivalent representations in the ISG model.

Once a desired graphical representation required to solve a desired problem has been mapped by a mapper module 1136, the analog processor interface module 1138 is used to create the corresponding coupling means 1174 and Coupling values and local bias values for quantum device nodes 1172. The functionality of the analog processor interface module 1138 can be divided into three discrete program modules: an initialization module 1140 , an algorithm module 1142 , and an output module 1144 .

The initialization module 1140 determines the appropriate coupling value J _ij of the coupling device 1174 and the value h _i of the local bias of the quantum device node 1172 of the analog processor 1150 . The initialization module 1140 can include instructions that can be programmed into the simulation processor 1150 to convert aspects of the problem definition into physical values, such as coupling strength values and node bias values. The initialization module 1140 then sends the appropriate signals along the internal bus 1106 into the NIC 1124. NIC 1124 in turn sends such instructions to quantum device control system 1162 and coupling device control system 1164 .

For any given problem, at each point in time during the calculation, the calculation module 1142 determines the coupling J _ij of the coupling device 1174 for the analog processor 1150 and the local bias _hi of the quantum device node 1172 Appropriate values to complete certain predetermined calculation schemes. Such signals are sent along bus 1106 and into NIC 1124 once algorithm module 1142 has determined appropriate coupler values and local bias values for an algorithm scheme. NIC 1124 in turn sends such commands to quantum device control system 1162 and coupled device control system 1164 .

The calculation of the analog processor 1150 may be an adiabatic calculation or an annealing calculation. Adiabatic calculations are calculations used in adiabatic quantum calculations, and calculation module 1142 may include instructions to extrapolate the state of processor 1150 from the calculations used in adiabatic quantum calculations. See, for example, US Patent Publication Nos. 2005-0256007, 2005-0250651, and 2005-0224784, each entitled "Adiabatic Quantum Computation with Superconducting Qubits," each of which is hereby incorporated by reference in its entirety. Annealing is another form of computation that may be used with some analog processors 1150, and computation module 1142 may include instructions to extrapolate the state of analog processor 1150 from the annealing computation.

The simulation processor 1150 solves a quantum problem based on the signals provided by the initialization module 1140 and the calculation module 1142 . Once the problem has been solved, the solution to the problem can be measured from state quantum device node 1172 via readout device 1160 . The output module 1144 works in conjunction with the readout device 1160 of the quantum processor 1150 to read the solution.

System memory 1126 may also include a driver module 1146 for outputting signals to analog processor 1150 . NIC 1124 may include appropriate hardware required to interface with quantum device nodes 1172 and coupled devices 1174 of analog processor 1150, whether this is directly or through readout device 1160, quantum device control system 1162, and/or coupled devices. Connect device control system 1164. Alternatively, NIC 1124 may include software and/or hardware to translate commands from driver module 1146 into signals (e.g., voltages, currents) applied directly to quantum device nodes 1172 and coupling devices 1174. In another alternative, NIC 1124 may include converting signals from quantum device nodes 1172 and coupling devices 1174 (representing a solution to a problem or some other form of feedback) so that they can be interpreted by output module 1144 software and/or hardware. Thus, in some cases, initialization module 1140, algorithm module 1142, and/or output module 1144 communicate with driver module 1146 rather than directly with NIC 1124 to send and receive signals from analog processor 1150.

The functionality of the NIC 1124 can be divided into two functional categories: data acquisition and control. Each of these discrete functional categories can be handled using a different type of chip. Data collection is used to measure the physical properties of the quantum device node 1172 after the analog processor 1150 has completed a calculation. Any number of custom or commercially available data acquisition microcontrollers may be used including, but not limited to, data acquisition cards manufactured by Elan Digital Systems (Fareham, UK), including AD 132, AD 136, MF 232, MF 236 , AD 142, AD 218 and CF 241 cards. Alternatively, data acquisition and control may be handled by a single type of microprocessor, such as an Elan D403C or D480C. There may be multiple NICs 1124 to provide sufficient control over the quantum device nodes 1172 and coupling devices 1174, and to measure the results of quantum computations on the analog processor 1150.

Digital computer 1102 may also include means for transmitting the solution of a computational problem processed by analog processor 1150 to other systems. Devices for implementing these means include, but are not limited to, a telephone modem, a radio modem, a local area network connection, or a wide area network connection. Digital computer 1102 may generate a carrier wave embodying a digital signal that encodes the answer to the computational problem processed by analog processor 1150 .

Analog processor 1150 may be a superconducting quantum computer, examples of which include qubit registers, readout devices, and auxiliary devices. Superconducting quantum computers typically operate at milliKelvin temperatures, and often in a kind of dilution refrigerator. An example of a dilution refrigerator is a model of the MNK 126 series from Leiden Cryogenics (Netherlands, Galgewater No. 21, 2311 VZ Leiden). Some or all of the components of the analog processor 1150 may be housed within the dilution refrigerator. For example, the quantum device control system 1162 and the coupling device control system 1164 may be located outside the dilution refrigerator, while the remaining components of the analog processor 1150 are installed within the dilution refrigerator.

User interface module 1132, analog processor interface module 1138, and driver module 1146, or any combination thereof, may be implemented using existing software packages. Applicable software packages include but are not limited to MATLAB (MathWorks, Natick, Massachusetts) and LabVIEW (National Instruments, Austin, Texas).

The methods, articles and systems can be implemented as a computer program product comprising computer program mechanisms embodied in a computer readable storage medium. For example, the computer program product may contain program modules as shown in FIG. 11 . These modules can be stored on a CD-ROM, DVD, disk storage product, or any other computer readable data and program storage product. The software modules in the computer program product are also distributed electronically via the Internet or otherwise by transmission of a computer data signal embodied in a carrier wave in which the software modules are embedded.

5.2 Processors and Quantum Devices

According to one embodiment of the method, article and system, a machine simulation of the ISG problem capable of approximating a ground state solution may be provided in the form of a simulation processor (eg, simulation processor 1150 of FIG. 11 ). Such an analog processor includes a hardware structure that includes a set of quantum devices (eg, quantum device node 1172 of FIG. 11 ). Each such quantum device is defined by at least two ground states and is capable of storing binary information in these ground states. The analog processor further includes a readout device for the quantum device (eg, readout device 1160 of FIG. 11 ), capable of detecting binary information stored in the corresponding quantum device. The analog processor further includes a set of coupling means (e.g., coupling means 1174 of FIG. 11 ) that connects each node to its nearest neighbor node(s) and/or the next nearest neighbor node(s), As described above with reference to Figures 2A, 2B, 3A, 3B, 4A, 4B, 6A, 6B, 9A, 9B, 10A and 10B. The analog processor further includes a coupling controller (eg, installed within coupling device control system 1164 of FIG. 11 ) for each coupling device. Each respective coupling controller is capable of adjusting the coupling strength J of a corresponding coupling device to a range of values J _C ^F to J _C ^AF , where J _C ^F is the maximum ferromagnetic coupling strength and is negative Whereas J _C ^AF is the maximum antiferromagnetic coupling strength and is positive. A J value of zero for a given coupling between two nodes means that the two nodes are not coupled to each other.

The analog processor further includes a node controller for each quantum device (eg, installed within quantum device control system 1162 shown in FIG. 11 ). Each such node controller is capable of controlling the effective bias applied to a corresponding quantum device. Such effective biases vary from about -100×|J| to about +100×|J|, where J is the average maximum coupling value for the corresponding node.

The quantum devices in the quantum processor can have different information ground states to facilitate readout and initialization. The quantum device can utilize quantum properties, such as incoherent quantum tunneling between ground states, coherent quantum tunneling between ground states, or involvement between states of different quantum devices, and the quantum properties of the quantum device can be enhanced The computing power of the simulated processor.

The analog processor performs a calculation to approximate the ground state of the mapped system. The information state spans an energy landscape, which depends on the conditions specified by the paradigm of the problem. In this energy form, the ground state energy is the lowest energy point, called the global minimum. The energy form contains a local minimum that can capture the state of the system (including all quantum devices and couplings inside the lattice) and prevent it from moving towards lower energy minima. Introducing quantum properties allows the state of the analog processor to tunnel away from this local minimum, so that the state can move to a lower energy minimum more easily, or with greater probability than without quantum tunneling. Move to lower flux minimum. Such an analog processor is capable of processing information with substantially lower constraints than a digital processor.

5.2.1 Superconducting devices

In certain embodiments of the methods, articles, and systems, the quantum device of the analog processor (eg, quantum device node 1172 of FIG. 11 ) is a plurality of superconducting qubits. In such embodiments, the analog processor can include any number of superconducting qubits, such as four or more, ten or more, twenty or more, 100 or more, or between 1,000 between 1,000,000 and 1,000,000 superconducting qubits.

Superconducting qubits have two modes of operation relative to the armed state in which information is stored. When the qubit is initialized or measured, the information is classical, ie 0 or 1, and the states representing this classical information are also classical to facilitate reliable state preparation. Thus, a first mode of operation of a qubit is to allow state preparation and measurement of classical information. This first mode of operation is useful for various embodiments of the methods, articles and systems.

A second mode of operation of a qubit occurs during quantum computing. During such quantum computations, the information states of the device are dominated by quantum effects, so that the qubits can be manipulated as a coherent superposition of these states and, in some cases, become identical to the Other qubits are implicated. However, this second mode of operation is difficult to implement at a high enough quality for general-purpose quantum computing.

Superconducting qubits can be used as nodes. Operation in the first mode makes them ideal for readout and significantly reduces the limitations that exist in the second mode of operation, such as difficulties in reading out the qubit, time requirements for coherence, etc. A superconducting qubit can act as a node in the analog processor and stay in the first mode of operation so that the qubit remains in the first mode of operation and also performs calculations when not being read out. In this way, minimal quantum properties are evident and disturbances to the state of the qubit are minimal.

Superconducting qubits generally have properties that fall into two types: phase qubits and charge qubits. Phase qubits are qubits that store and process information in the phase state of the device. In other words, phase qubits use phase as an information-carrying degree of freedom. Charge qubits store and process information in the state of charge of the device. In other words, charge qubits use charge as an information-carrying degree of freedom. In a superconducting material, there is a phase difference between different points in the superconducting material, and the elementary charge is represented by a pair of electrons called a Cooper pair that flows in the superconducting material. The division of such devices into two categories is outlined in Makhlin's text. Phase and charge are related values in superconductors and, at energy levels where quantum effects dominate, a phase qubit has a well-defined phase state for storing quantum information, and a charge qubit has a well-defined phase state for storing quantum information. defined state of charge. In the present methods, articles, and systems, phase qubits, charge qubits, or superconducting qubits that are a hybrid of phase and charge qubits can be used in analog processors.

The experimental realization of a superconducting device as a qubit was made by Nakamura et al. 1999 in Nature 398, p.786, which is hereby incorporated by reference in its entirety, where they developed a Charge qubits, but the qubits have poor (short) descattering times and tightly controlled parameters.

5.3 Mapping to superconducting integrated circuits

According to embodiments of the method, article and system, the layout based on the ISG lattice maps directly to an integrated circuit that fulfills all the requirements for performing calculations that approximate or exactly define the ground state of the system. The analog processor can include:

(i) a set of nodes, each node comprising a loop of superconducting material interrupted by one or more Josephson junctions;

(ii) a set of coupling devices, each coupling device in the set of coupling devices is coupled to two nodes in the set of nodes;

(iii) a set of readout devices, each readout device in the set is configured to read the state of one or more corresponding nodes in the set of nodes; and

(iv) a set of local bias devices, wherein each local device in the set of local bias devices is configured to apply a local bias field on one or more corresponding nodes of the set of nodes .

One or more coupling means of the set of coupling means may each comprise a loop of superconducting material interrupted by one or more Josephson junctions. The parameters of this coupling device are set on the basis of the size of the loop and the characteristics of the Josephson junction. Such coupling means are typically adjusted by a corresponding control system by applying either a magnetic or electrical bias.

FIG. 12A shows a graph 1200 with two nodes N1 and N2 and a single coupling device J1-2 coupling the labeled nodes N1 and N2. FIG. 12B shows the transformation of graph 1200 node N1 of node N1 and coupling device J1 - 2 into an integrated circuit 1202 . Integrated circuit 1202 includes superconducting nodes N1 and N2 , which correspond to nodes N1 and N2 of graph 1200 . Integrated circuit 1202 also includes bias means 110-1 and 110-2 and readout means 120-1 and 120-2, respectively, and a single coupling means J1-2. In FIG. 12B , nodes N1 and N2 are each rf-SQUIDs, which may include a single Josephson junction 130 and a composite Josephson junction 131 . The composite Josephson junction 131 can also be expressed as a dc-SQUID interrupting a superconducting loop. Magnetic flux can then be applied to the composite Josephson junction 131 to provide an additional degree of modulation of the node parameters. In particular, the tunneling rate of the quantum device (superconducting node N1 ) can be tuned by varying the current applied by the device 11 . Equivalently, the height of the energy barrier 1700 of the system (shown in FIG. 17 and described below) can be adjusted.

Nodes N1 and N2 may be three Josephson junction qubits. Such a structure consists of a superconducting loop interrupted by three Josephson junctions. Nodes N1 and N2 in integrated circuit 1202 each have two states corresponding to two possible directions of current, or supercurrent, flowing in its respective superconducting loop. For example, a first state of nodes N1 and N2 is represented by currents circulating clockwise in their corresponding superconducting loops and a second state is represented by currents circulating counterclockwise in their corresponding superconducting loops. The circulating current bands corresponding to each of the states represent the different magnetic fields generated by such circulating currents.

Readout devices 120-1 and 120-2 and coupling device J1-2 are shown with the same shaded boxes in FIG. 12B because in some embodiments they are the same type of device, having similar structures and The components, however, are configured to perform different functions within integrated circuit 1202 . For example, coupling device J1-2 may be a dc-SQUID configured to adjustably couple nodes N1 and N2. The coupling device J1-2 can be monostable, which means it has only one minimum value of potential energy. Readout devices 120-1 and 120-2 may be dc-SQUIDs that are inductively coupled to corresponding nodes and configured to controllably detect current flow in those nodes. Alternatively, the sensing devices 120-1 and 120-2 may be any devices capable of detecting the states of the corresponding nodes N1 and N2.

Biasing devices 110-1 and 110-2 are shown in Figure 12B as metallic loops. A local magnetic field can be applied from a bias device 110 to the corresponding node by driving a current through the bias device. Bias device 110 may be fabricated from low temperature superconducting metals such as aluminum and niobium. The biasing means may not be a loop, but may simply be a wire passed around the corresponding node N to couple magnetic flux into the loop. Each bias device 110 may include a wire that passes around the corresponding node and then connects to another metal layer using a via on the chip, such as a backplane. An integrated circuit such as circuit 1202 of FIG. 12B can map directly from this ISG matrix and include all required degree of control to process information.

Figure 13A shows one embodiment of a lattice-based set of nodes 1300, comprising a graph having five nodes N1 through N5, and four coupling devices J1-3, J2-3, J3-4, and J3 -5. FIG. 13B shows a conversion of dot matrix 1300 to integrated circuit 1302 . Integrated circuit 1302 includes five quantum devices N1 to N5, corresponding to five nodes of lattice 1000, and four coupling devices J1-3, J2-3, J3-4, and J3-5 connecting the five quantum devices , corresponding to the coupling device of lattice 1000. Integrated circuit 1302 further includes local bias means 110-1, 110-2, 110-4, and 110-5 and readout means 120-1, 120-2, 120-4, and 120-5. For clarity, Fig. 13B does not explicitly show a local biasing means or sensing means for node N3. Various aspects of integrated circuit 1302 may be placed on separate layers to optimize space constraints. In this case, a local biasing device or readout device for node N3 may be placed above or below the layer in which this N3 is fabricated. Individual components of integrated circuit 1302 may be identical to corresponding components of integrated circuit 1002 (Error! Reference source not found. 10B), with the exception that node N3 in the center shares four couplings with adjacent nodes N1, N2, N4, and N5 device.

There may be unused quantum devices in integrated circuit 1302 next to N1, N2, N4, and N5. For clarity, however, such unused quantum devices are not shown in Figure 13B. Each pattern encoded in integrated circuit 1302 may utilize any number of qubits present in the integrated circuit.

One or more quantum devices N1 through N5 of integrated circuit 1302 may be configured as a magnetic gradiometer loop such that the magnetic field affects the gradiometer loop only when the magnetic field is not uniform across the loop. A gradiometer is useful to assist in coupling and to reduce the susceptibility of the system to external magnetic field noise. Nearest neighbor nodes may be arranged at perpendicular angles or near perpendicular angles to reduce parasitic coupling (eg, crosstalk) between adjacent nodes. A first and second node may be considered to be arranged at a mutually perpendicular angle when a first major axis of the first node and a second major axis of the second node are aligned perpendicular to each other.

FIG. 14A shows an embodiment of a lattice-based node 1400 group with nine activated nodes N1 to N9 and corresponding coupling devices, while FIG. 14B shows a lattice 1400 to a group with nine nodes N1 Conversion to integrated circuit 1402 of N9 and twenty coupled devices. For clarity, only nodes N1, N2, N4 and N5, and couplings J1-4, JN1-5, JN2-4 and J4-5 are labeled in FIGS. 14A and 14B. Local bias means 110-1, 110-7, 110-8, and 110-9, and readout means 120-3, 120-6, and 120-9 are also identified in integrated circuit 1402. Figure 14B does not exhaustively include local biasing arrangements for all nodes. Aspects of integrated circuit 1402 may be placed on separate layers to optimize space constraints. In this case, a local biasing device or readout device of the nodes for which no local biasing device is shown in FIG. 14B can be arranged above or below the layer in which these nodes are produced. These biasing devices may not be loops, but simple wires that pass around node N and couple flux into the loop. The biasing device can consist of a wire passing near the qubit on the same or a different layer, and then connected to a via that connects to another metal layer on the chip, such as a backplane .

Each component of integrated circuit 1402 may be identical to components of integrated circuits 1202 and 1302 . Such components have been described above with reference to Figures 12B and 13B. One difference between the integrated circuit 1402 and other circuits is that the next nearest neighbor coupling devices JN, such as JN2-4 and JN1-5, are added in the integrated circuit 1402. As shown in the figure, the next nearest neighbor coupling device JN2-4 spans the next nearest neighbor coupling device JN1-5. The wires in one or both of the coupling devices JN1-5 and JN2-4 may be on multiple layers.

The next nearest neighbor coupling devices, such as coupling devices JN2-4 and JN1-5, may be dc-SQUIDs, or alternatively may be rf-SQUIDs. They may be equivalent to the coupling device J of Fig. 12B, differing only in their structure. Only three readout devices 120-3, 120-6, 120-9 are shown in FIG. 14B for reading out corresponding nodes N3, N6, and N9, respectively. All other nodes may have corresponding readout devices 120 . Alternatively, only a few readouts can be used, and a classical state replication technique can be used to replicate the state of the internal nodes to the peripheral nodes N3, N6, N9, e.g. ,” U.S. Patent Application Serial No. 60/675,139, which is hereby incorporated by reference in its entirety.

Although not shown in FIG. 14B , there may be unused quantum devices in integrated circuit 1402 next to peripheral quantum devices N1 , N2 , N3 , N4 , N6 , N7 , N8 , and N9 . One or more quantum devices N1 through N9 in integrated circuit 1402 may be configured as a magnetic gradiometer loop such that the magnetic field affects the gradiometer loop only when the magnetic field is not uniform across the loop. A gradiometer loop is useful to aid in coupling and to reduce the susceptibility of the system to external magnetic field noise. The closest nodes may be arranged at perpendicular angles or near perpendicular angles to reduce parasitic coupling (eg, crosstalk) between neighboring nodes.

Figure 15 shows a photograph of an example of a physical layout of the method, article and system as present. Four flux-based quantum devices, 1501-1 through 1501-4, have been fabricated on a superconducting integrated circuit. Each quantum device is connected to every other quantum device in the photo using nearest neighbor and next nearest neighbor couplings. For example, coupling device J1-3 is a nearest neighbor coupling device for coupling quantum devices 1501-1 and 1501-3 together. Nearest neighbor coupling also exists between quantum devices 1501-1 and 1501-2, between 1501-2 and 1501-4, and between 1501-3 and 1501-4, although these coupling devices are not exhaustively labeled out. Coupling device J2-3 is an example of a next nearest neighbor coupling and couples quantum devices 1501-2 and 1501-3 together. Another next-nearest neighbor coupling exists between quantum devices 1501-1 and 1501-4, although it is not exhaustively labeled. There are also readout means and local bias means on this circuit, but they are not shown in FIG. 15 .

Figure 16 shows another alternative layout as the present method, article and system. There are six quantum devices in the figure, three of them are labeled 1601-1, 1601-2, and 1601-3. However, the layout shown in the figure can be easily extended to any number of quantum devices. The quantum devices 1601-1 and 1601-2 are connected together through the coupling device J1-2. The coupling device J1-2 may be an rf-SQUID, or alternatively a dc-SQUID. The quantum devices 1601-1 and 1601-3 are coupled together through the coupling device J1-3, which is a direct current coupling in FIG. 16 . Thus, quantum devices 1601-1 and 1601-3 are ferromagnetically coupled and have the same quantum state. Implementations of the coupling device J1-3 may include utilizing multiple vias to create a path of the coupling device using multiple metal layers. An example is the junction J1-3-A in Figure 16, where a part of the coupling device J1-3 is fabricated on another metal layer and connected to the original layer using two vias. Such techniques are well known in the art.

5.4 Simulation processing

5.4.1 System level

One aspect of the methods, articles and systems provides a method of finding the lowest energy configuration or approaching the lowest energy configuration given a set of initial conditions. These methods usually involve mapping a problem to be solved onto a lattice layout topology. The topology of the lattice layout is mapped onto a circuit comprising a lattice of quantum devices between which couplings are arranged. The quantum device and coupling are individually initialized and run-time control is induced by using local bias control on the quantum device and coupling or by using a global bias field. In this way, the topology of the lattice layout representing the problem to be solved is mapped onto a physical lattice of quantum devices. The final state of the lattice of the quantum device is then taken as the solution to the problem. The solution may be in the form of a binary number.

5.4.2 Initialization

Cat State in an rf-SQUID，”arXiv.org：cond-mat/0004293v2，该文通过引用全文结合在此。图17A和17B各示出一个双阱势能的图形。能量表示在y-轴上，而一些其他的与该装置相关联的从属变量，譬如该量子装置的内部通量表示在x-轴上。该系统由一个在该势曲线内移动的一种粒子说明。如果该粒子在左阱中，它就处于|L>状态，并且如果该粒子处于右阱中，它就处于|R>状态。这两个状态可以分别地标示为|0>和|1>，或者分别地标示为|1>和|0>。在一个超导通量量子位或者稳恒电流量子位中，这两个状态对应于环流电流的两个不同的方向，左环流和右环流。每个节点处的状态的初始化可以通过本地调整每个节点处的偏置，或通过使用一种全局偏置场进行。可选择的是，这样的调整还可以通过降低状态之间的壁垒高度来进行。如果该势能曲线向一侧倾斜，如在图17A中所示，该粒子将有较大的概率移动进入较低的通量阱中。在图17A的情况下，这会是|R>状态160-1。如果该势能阱曲线在另一侧倾斜，该粒子将有较大的概率移动进入对置的阱中。在图17A的情况下，这会是|L>状态160-0。Initialization of an analog processor with quantum features includes initializing the state at each quantum device and initializing the state of each coupled device that will be used to represent the problem being solved. The potential energy curve of a quantum device representing a node in a graph to be solved can be a double well potential energy, similar to the "Detection of a

Cat State in an rf-SQUID," arXiv.org:cond-mat/0004293v2, which is hereby incorporated by reference in its entirety. Figures 17A and 17B each show a graph of the potential energy of a double well. Energy is represented on the y-axis, While some other dependent variables associated with the device, such as the internal flux of the quantum device are represented on the x-axis. The system is described by a particle moving within the potential curve. If the particle is in the left trap , it is in the |L> state, and if the particle is in the right well, it is in the |R> state. These two states can be denoted as |0> and |1>, respectively, or as | 1> and |0>. In a superconducting flux qubit or a constant current qubit, these two states correspond to two different directions of the circulating current, left and right. The state at each node The initialization of can be done by locally adjusting the bias at each node, or by using a global bias field. Optionally, such adjustment can also be made by reducing the barrier height between states. If the potential energy curve Tilting to one side, as shown in Figure 17A, the particle will have a greater probability of moving into the lower flux well. In the case of Figure 17A, this would be |R>state 160-1. If The potential well curve is sloped on the other side, and the particle will have a higher probability of moving into the opposite well. In the case of Figure 17A, this would be |L>state 160-0.

Initializing a quantum device whose state is described by a particle's position in a double-well potential involves tilting the potential on one side by adjusting the local bias at the node, and waiting long enough for the particle to move with some high probability to lower potential energy. The local field bias may be a magnetic field, and adjusting the local field bias at the node may include applying a current to a superconducting loop or coil in close proximity to the quantum device, thereby generating A local magnetic field bias. After a sufficient time, the state of the device will relax into the lower flux well of the double well potential, which is the desired initial state. The state of the device may fall into a lower energy well through thermal runaway, or the state of the device may reach a lower energy through a tunneling process across the barrier 1700 . In some cases, both thermal runaway and tunneling processes contribute to initialization.

Initializing the local field bias at each quantum device includes setting up a global field bias across the entire lattice of the quantum device and waiting for a certain length of time. Applying a global field bias causes all quantum devices to be initialized to the same state. The global bias can be a magnetic field. Each quantum device representing a node can consist of one or more loops of Josephson-interrupted superconducting material, where initialization can be performed across all quantum devices by applying a global magnetic field, which causes each quantum device to Initialize to the same constant current state.

A quantum device in an integrated circuit that can be used to solve a computational problem is a loop of superconducting material interrupted by one or more Josephson junctions. Such a loop may be suitably constructed to have a potential energy characteristic similar to that illustrated by a double well potential depicted in FIG. 17A or 17B. The two wells in the double well potential correspond to two different directions of the steady state current (eg, currents 102-0 and 102-1 of FIG. 1A ) of the superconducting material loop. The loop can be initialized to the desired state by ramping the double well potential, as shown in Figure 17A. Such tilting can be induced, for example, by applying an external flux bias through the superconducting loop. In some cases, the external flux bias can be removed once it is determined that the state of the quantum device has been initialized to the lowest energy state. An external flux can be applied to a superconducting loop by placing a loop or coil of wire in close proximity to the superconducting loop and applying a bias current through the loop or coil of wire. Passing this bias current through the superconducting loop causes a change in the magnetic field that affects the potential energy of the quantum device.

The height of barrier 1700 can be varied by changing the critical current of the Josephson junction that interrupts the superconducting loop. In a standard rf-SQUID, this change can be made during fabrication, but once the device is constructed, the critical current of a junction is generally fixed. However, if a single Josephson junction in the rf-SQUID is replaced by a composite Josephson junction, it is possible to tune the effective critical current even after fabrication. This is accomplished by applying a magnetic field to the small-slit junction loop, and adjusting the magnetic field changes the effective critical current of the rf-SQUID.

One or more quantum devices acting as nodes in an integrated circuit can be rf-SQUIDs. An rf-SQUID is a loop of superconducting material interrupted by one or more Josephson junctions. A device with three Josephson junctions in this loop is called a 3JJ qubit. Such an rf-SQUID type device can be configured so that its potential energy characteristic curve is described by a double well potential. The two wells in this double well potential correspond to two different directions of the galvanostatic current in the loop of superconducting material. Devices with rf-SQUIDs exhibiting quantum properties are described in the 2000 paper by Friedman. An external flux can be applied to the superconducting loop of the rf-SQUID by applying a bias current to a loop or coil of wire placed in close proximity to the superconducting loop of the rf-SQUID.

式中

是结i的规范不变性相位。图18中的各个结X的Josephson能量的一个特性在于它是两个相位的函数。对于一个磁抑制f的范围这两个相位

和

允许有两个稳定配置，该两个两个稳定配置对应于相反方向流动的DC电流。如在Orlando中所讨论，通过考虑该结中的充电能量(电容性能量)和机械上考虑该电路量子，可以把该电路参数调节为使f＝1/2附近的该系统的两个最低状态将对于相反的环流电流的两个经典状态。Each quantum device (eg, quantum processor) in an integrated circuit used to solve a quantum problem can be a loop of superconducting material interrupted by three Josephson junctions. The methods of initialization of these types of qubits can be the same as those explained above in the case of rf-SQUID quantum devices. These types of devices do not require large loop inductances, and thus large loop areas, to have a double well potential characteristic. A device with three Josephson knots is described in Orlando. One or more of the quantum devices may be a constant current qubit, such as the one shown in Figure 18, reproduced from Orlando's paper. Such a device can be used as a quantum device as in the present methods, articles and systems. Each Josephson junction in Fig. 18 is marked by an X and is modeled by the parallel combination of an ideal Josephson junction and a capacitor _Ci . Parallel resistive channels are assumed to be negligible. An ideal Josephson junction has a current phase relationship

In the formula

is the gauge invariant phase of junction i. One property of the Josephson energy of each junction X in Figure 18 is that it is a function of two phases. For a range of magnetic suppression f these two phase

and

Two stable configurations are allowed, corresponding to DC currents flowing in opposite directions. As discussed in Orlando, by considering the charging energy in the junction (capacitive energy) and mechanistically considering the circuit quantum, the circuit parameters can be tuned to make the two lowest states of the system around f = 1/2 will be for the two classical states of opposite circulating currents.

All or part of the quantum devices in an integrated circuit for solving a computational problem can be composite Josephson junction rf-SQUIDs. A composite Josephson junction rf-SQUID is similar to an rf-SQUID, except that a single Josephson junction is replaced by a dc-SQUID connected to the rf-SQUID loop, which is also called a composite Josephson junction. A dc-SQUID consists of two or more Josephson structures connected in parallel with two electrical contacts formed between the junctions. The device behaves similarly to an rf-SQUID, except that it has an additional degree of control in the sense that the critical current can be changed in the loop by adjusting the flux through the dc-SQUID loop. Adjusting the critical current changes the barrier height separating the left and right well states |L> and |R> of the double well potential. The flux through the large rf-SQUID loop still adjusts the tilt of the double well potential, as in a standard rf-SQUID. Initializing the quantum device can include either tilting the double well potential by applying a flux bias to the rf-SQUID, lowering the barrier height by applying a bias to the dc-SQUID loop, or both , and then wait for the device to initialize to the ground state. Adjusting the flux through the dc-SQUID loop represents ^σX control over the state of the quantum device.

Each quantum device in an integrated circuit used to solve a computational problem may be a magnetic gradient quantum qubit. Gradient counter bits are initialized in a manner similar to rf-SQUIDs. The method of initializing the gradient meter subbit involves applying a flux bias and waiting for a certain length of time. An external flux is applied to a loop by applying a bias current to a coil or loop of wire placed in close proximity to the loop. Gradient qubits consist of two superconducting lobes that are in electrical communication with each other and have opposite current directions. Initialization may involve applying a flux bias to either or both of the two lobes.

Methods for initializing quantum devices have been discussed above. The coupling device is also initialized. In some cases, by setting the coupling device to a desired initial state and then waiting for a certain period of time that is characteristic of the coupling device to ensure that the coupling device is in fact set to the desired initial state state. As a result of such initialization, the coupling device is initialized to a state of J=-1 or J=1, where the coupling strength J is normalized such that for a given problem, the desired coupling The intensity corresponds to J=|1|.

At least one coupling device in an integrated circuit may be a quantum superconducting device. For example, the coupling means may be an rf-SQUID in the integrated circuit. In such cases, initialization of an rf-SQUID used as a coupling device may include applying a local flux bias to the coupling device. This can be done by placing a bias current through a superconducting loop or coil in close proximity to the coupling device. An Rf-SQUID used as a coupling device can be monostable, meaning that its potential energy function has only one minimum. All or some of the coupling devices in the integrated circuit (eg, quantum processor) may be dc-SQUIDs, and initialization of such coupling devices includes applying a bias current directly to such coupling devices.

All or part of the coupling means in the integrated circuit (eg quantum processor) may be gradiometer couplings. A method of initializing the coupling of a gradiometer for use as a coupling device in an integrated circuit includes applying a flux bias to one lobe of the gradiometer or to both lobes of the gradiometer.

5.4.3 Runtime control

According to embodiments of the methods, articles, and systems, a method of performing run-time control of an analog processor includes varying the quantum device effective bias. This can be done by adjusting the respective local field bias at each quantum device in the analog processor, adjusting the coupling strength of the coupling between pairs of quantum devices in the analog processor, or by adjusting the The adjustment of the barrier height is equivalent to changing the effective temperature of the system consisting of a quantum device and a lattice of coupled elements.

A corresponding decrease or increase in the barrier height of the quantum device is sufficient to increase or decrease the effective temperature of the system. The barrier height of a quantum device is the potential energy barrier between the two potential wells of that energy form, shown as barrier 1700 in Figures 17A and 17B. If the quantum device includes a composite junction, the barrier height of the quantum device can be changed by adjusting the external magnetic field through the loop of the composite junction.

If the effective temperature is used to reach an analog processor end state, the potential energy barrier of all quantum devices is lowered first, which increases the effective temperature by making the quantum state of the analog processor susceptible to thermal escape from a local minimum. The potential energy barrier of the quantum device is then slowly raised, thereby lowering the effective temperature, allowing the analog processor's quantum state to find a lower minimum.

Annealing purely by thermal runaway is called classical annealing because it does not exploit the quantum effects of the system. The method of finding the terminal state of this simulated processor can be completely classical. Alternatively, quantum annealing can be performed in addition to classical annealing. One form of quantum annealing is quantum tunneling, in which the quantum state of the analog processor finds a lower minimum than the state it is currently in by tunneling through the barrier rather than by thermal runaway. Thus, quantum annealing can help the quantum state find a lower minimum when the probability of thermal escape from its existing minimum is statistically small.

Finding the final state of an analog processor can be performed by adiabatic quantum calculus. In adiabatic quantum evolution, the analog processor is initialized to a ground state of a known quantum state of the Hamiltonian. The quantum state is then allowed to evolve adiabatically to a terminal Hamilton function. The adiabatic evolution is usually slow enough to prevent the quantum state from moving from the ground state to an excited state. Adiabatic evolution can be performed by adjusting the coupling strength between the quantum devices in the processor or by adjusting the individual biases of the quantum devices, or by adjusting a global bias affecting all quantum devices. The terminal ground state represents the solution to a computational problem encoded by the terminal Hamilton function. More information on this process can be found, for example, in the aforementioned US Patent Application Publication Nos. 2005-0256007, 2005-0250651, and 2005-0224784.

A method of performing runtime control of an analog processor includes a method of increasing the actual temperature of the analog processor by a thermal annealing process. The thermal annealing process may include increasing the temperature of the system from a base temperature to a temperature between 30 mK and 3K, and then decreasing the temperature of the system to the base temperature.

5.4.4 Readout

A method of reading out the state of a quantum device (eg, quantum processor) in an integrated circuit may include initializing a readout device and measuring a physical characteristic of the readout device. A quantum device has two possible readout states, the |0> state and the |1> state. Reading out a quantum device collapses the quantum state of the device into one of two classical states. Wherein the barrier height on the quantum device is adjustable, and the barrier height can be increased before reading out the state of the quantum device. Raising the barrier, such as barrier 1700 of Figure 17, freezes the quantum device in either the |0> state or the |1> state.

The readout device may include a dc-SQUID magnetometer inductively connected to the quantum device, in which case determining the state of the quantum device may include measuring a voltage or current from the dc-SQUID magnetometer. The voltage or current can then be converted to a value representative of the magnetic field at the quantum device.

Classical state replication can be used to reduce the number of readout devices required. See, eg, previously referenced US Patent Application 60/675,139.

After reading out the state of the quantum device, the result of the measurement can be transmitted using a data signal embodied on a carrier wave. The data signal can be a digital signal, and in some cases, digital computer 1102 (shown in FIG. 11 ) can be used to generate the carrier wave.

5.5 Cited references

All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent literature mentioned in this specification include but are not limited to US 6,670,630, US 6,784,451, US 6,822,255, US 6,885,325, US 6,897,468, US 6,960,780、US 6,979,836、US 2002-0121636、US2003-0107033、US 2003-0121028、US 2003-0169041、US2003-0173498、US 2004-0000666、US 2004-0016918、US2004-0119061、US 2004-0140537、US 2005 - 0224784, US2005-0250651, US 2005-0256007, US Patent Application Serial Nos. 60/640,420, 60/675,139, and 11/247,857, are hereby incorporated by reference in their entirety and for all purposes.

5.6 Alternative Implementations

It will be apparent to those skilled in the art that the various embodiments set forth above can be combined to provide further embodiments. Aspects of the invention can be modified, if desired, to utilize the systems, circuits and concepts of the various patents, applications and documents to provide further embodiments of the invention. This or that change can be made to the present invention based on the foregoing description. In conclusion, in the appended claims, the terms used should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments, together with the All equivalents to which the claims are entitled. Accordingly, the invention is not limited by what has been disclosed, but rather its scope should be determined solely by the appended claims.

Claims (47)

1. A computing system comprising: a computer; and a quantum processor in communication with the computer, the quantum processor comprising: (i) a plurality of quantum devices, wherein each quantum device of the plurality of quantum devices is a node of a lattice, and wherein a quantum device of the plurality of quantum devices has a first basis state and a second basis status: and (ii) a plurality of coupling devices, wherein a first coupling device in the plurality of the coupling devices adjustably couples a first quantum device in the plurality of quantum devices to the plurality of quantum devices A second quantum device in , wherein the configuration of the first quantum device and the second quantum device in the lattice is selected from the group consisting of a nearest neighbor configuration and a next nearest neighbor configuration. 2. The system of claim 1, wherein a quantum device of the plurality of quantum devices comprises a loop of superconducting material interrupted by at least one Josephson junction. 3. The system of claim 2, wherein at least one Josephson junction in the quantum device is a composite Josephson junction. 4. The system of claim 1 , wherein the plurality of quantum devices is arranged in a two-dimensional array, wherein the two-dimensional array has a width defined by a first plurality of nodes n and defined by a second plurality of nodes m defines the length, and where the two-dimensional array includes an interior and a perimeter. 5. The system of claim 4, wherein each quantum device in the interior is coupled to four nearest neighbor quantum devices in the lattice and to four nearest neighbors in the lattice. on the nearest neighbor quantum devices. 6. The system of claim 1, wherein the quantum device of the plurality of quantum devices has a gradiometer configuration. 7. The system of claim 1, wherein the first quantum device and the second quantum device are nearest neighbors in the lattice; and A second coupling device in the plurality of coupling devices adjustably couples the first quantum device to a third quantum device in the plurality of quantum devices, wherein the first quantum device and the third The quantum device is the next nearest neighbor in the lattice. 8. The system of claim 1, wherein at least one coupling device of the plurality of coupling devices comprises a loop of superconducting material interrupted by at least one Josephson junction. 9. The system of claim 1, wherein at least one coupling device of the plurality of coupling devices comprises a loop of superconducting material interrupted by at least one composite Josephson junction. 10. The system of claim 1, wherein at least one coupling device of the plurality of coupling devices is selected from the group consisting of an rf-SQUID and a dc-SQUID. 11. The system of claim 1, the quantum processor further comprising: A readout device configured to read out a state of at least one quantum device of the plurality of quantum devices. 12. The system of claim 11, wherein the readout device is selected from the group consisting of a dc-SQUID and a magnetometer. 13. The system of claim 1, wherein the first coupling device is configured to adjust a coupling strength between the first quantum device and the second quantum device such that the first quantum device and the The second quantum device is coupled ferromagnetically. 14. The system of claim 13, wherein the first coupling device is configured to apply a zero-effect local field bias to the first quantum device. 15. The system of claim 1, wherein the first coupling device is configured to adjust the coupling strength between the first quantum device and the second quantum device such that the first quantum device and the second quantum device The two quantum devices are diamagnetically coupled. 16. The system of claim 1, wherein the first quantum device and the second quantum device are nearest neighbors in the lattice. 17. The system of claim 1, wherein the first quantum device and the second quantum device are next nearest neighbors in the lattice. 18. The system of claim 1, wherein the quantum processor is used to solve a computational problem selected from a problem with complexity P, a problem with complexity NP, a problem with complexity NP - A set of hard problems and a problem of complexity NP-complete. 19. The system of claim 18, wherein the quantum processor is coupled to a transmitter, and wherein the transmitter is configured to send a solution to the computational problem as a data signal embodied in a carrier wave . 20. The system of claim 1, wherein the computer is a digital computer. 21. A method of determining the result of a computational problem using a quantum processor, the method comprising: (i) initializing the quantum processor to an initial state, wherein the quantum processor includes a plurality of quantum devices and a plurality of coupling devices, and wherein each coupling device in the plurality of quantum devices is tunably coupling a pair of quantum devices of the plurality of quantum devices, wherein the initialization includes setting a state of at least one quantum device of the plurality of quantum devices, and setting at least one coupling of the plurality of coupling devices A coupling strength of the coupling device; (ii) allow the quantum processor to be calculable to a final state, wherein the final state approximates a natural ground state of the computational problem; and (iii) reading out an end state of at least one quantum device of the plurality of quantum devices to determine a result of the computational problem. 22. The method of claim 21, wherein at least one quantum device of the plurality of quantum devices comprises a loop of superconducting material interrupted by at least one Josephson junction. 23. The method of claim 21, wherein at least one quantum device of the plurality of quantum devices is an rf-SQUID. 24. The method of claim 21, wherein at least one quantum device of the plurality of quantum devices comprises a loop of superconducting material interrupted by at least one Josephson junction and at least one composite Josephson junction. 25. The method of claim 21 , wherein allowing the quantum processor to evolve to a terminal state includes at least one of reducing the effective temperature of the quantum processor and adiabatically evaluating the quantum processor . 26. The method of claim 21 , wherein the computational problem is selected from a problem of complexity P, a problem of complexity NP, a problem of complexity NP-hard, and a problem of complexity NP - Complete set of questions. 27. The method of claim 21, wherein initializing the quantum processor to a terminal state comprises: initializing a first quantum device of the plurality of quantum devices to have a local field bias of zero effect; and A coupling device of the plurality of coupling devices is initially ferromagnetically coupled to a second quantum device of the plurality of quantum devices to a first quantum device of the plurality of quantum devices. 28. The method of claim 27, wherein the computational problem is a maximum independent set problem. 29. A computer system for determining a result of a computational problem, the computer system comprising: a user interface module including instructions for defining the computational problem; a mapper module comprising a mapping for generating the computational problem; An analog processor interface module including: (i) means for transmitting the map to an analog processor, wherein the analog processor includes a plurality of quantum devices and a plurality of coupling devices, the map including a map for at least one quantum device in the plurality of quantum devices an initialization value, and an initialization value for at least one coupling device of the plurality of coupling devices, wherein a coupling device of the plurality of coupling devices is a corresponding associated quantum device of a plurality of quantum devices tunably coupled to at least one of a nearest neighbor of the associated quantum device and a next-nearest neighbor of the associated quantum device; and (ii) means for receiving a result from the analog processor responsive to the mapping. 30. The computer system according to claim 29, the memory further stores a driver module, the driver module comprising: means for transmitting the map to the analog processor; and means for receiving the result from the analog processor; and wherein The means in the analog processor interface module for transferring the map to the analog processor includes means for transferring the map to the driver module; and The means for receiving the result in the analog processor interface module includes means for receiving the result from the analog processor from the driver module in response to the mapping. 31. The computer system of claim 29, wherein the means for defining the computational problem comprises means for analyzing a set of instructions encoding the computational problem. 32. The computer system of claim 29, wherein the computational problem is selected from a problem of complexity P, a problem of complexity NP, a problem of complexity NP-hard, and a problem of complexity The set of NP-complete problems. 33. The computer system of claim 29, wherein the computational problem is selected from the group consisting of an Ising spin glass problem, a maximum independent set problem, a maximum clique problem, a maximum cut problem, a traveling salesman problem, a k -A set of SAT problems and an integer linear programming problem. 34. A quantum processor comprising: Multiple quantum devices arranged in a lattice; A first plurality of coupling devices, wherein a coupling device in the first plurality of coupling devices adjustably couples a first quantum device and a second quantum device of the plurality of quantum devices , wherein the first quantum device and the second quantum device are nearest neighbors in the lattice; and a second plurality of coupling devices, wherein a coupling device in the second plurality of coupling devices adjustably couples a third quantum device and a fourth quantum device of the plurality of quantum devices , wherein the third quantum device and the fourth quantum device are the next nearest neighbors in the lattice. 35. The quantum processor of claim 34, further comprising a readout device coupled to a quantum device of the plurality of quantum devices such that the readout device can measure the quantum device's a state. 36. The quantum processor of claim 35, wherein the readout means are arranged on a perimeter of the lattice. 37. The quantum processor of claim 34, further comprising a local bias device coupled to at least one quantum device of the plurality of quantum devices. 38. The quantum processor of claim 34, wherein a pattern is embedded in the lattice; and wherein A group of quantum devices of the plurality of quantum devices is a node of the graph; A set of coupling devices in the first plurality of coupling devices is assigned a non-zero value such that at least two quantum devices in the set of quantum devices are adjustably coupled to each other according to the graph; and A group of coupling devices in the second plurality of coupling devices is assigned a non-zero value such that at least two quantum devices in the group of quantum devices are adjustably coupled to each other according to the graph. 39. The quantum processor of claim 38, wherein the graph is non-planar. 40. The quantum processor of claim 34, wherein The first quantum device and the second quantum device are nearest neighbors in the lattice determined by Manhattan distance; and The third quantum device and the fourth quantum device are the next closest neighbors in the lattice as determined by the Manhattan distance. 41. The quantum processor of claim 34, wherein at least two coupling means in the first plurality of coupling means are arranged such that they do not intersect; and At least two coupling means in the second plurality of coupling means are arranged such that they intersect. 42. A quantum processor comprising: multiple quantum devices; A first plurality of coupling devices, wherein the plurality of quantum devices and the first plurality of coupling devices form a planar rectangular array having a diagonal, and wherein in the first plurality of coupling At least one coupling device in the coupling device couples a first quantum device of the plurality of quantum devices and a second quantum device of the plurality of quantum devices with a coupling strength of a value in the range between a minimum negative coupling strength and a maximum positive coupling strength; a second plurality of coupling devices, wherein at least one coupling device in the second plurality of coupling devices couples a third quantum device of the plurality of quantum devices to the plurality of quantum devices with a coupling strength A fourth quantum device in the device is adjustably coupled, the coupling strength has a value in the range between a minimum negative coupling strength and a zero coupling strength, and wherein the third quantum device and the fourth quantum device is arranged along a diagonal of the planar rectangular array; a readout device coupled to at least one quantum device of the plurality of quantum devices; and A local biasing device coupled to at least one quantum device of the plurality of quantum devices. 43. The quantum processor of claim 42, wherein a graph is embedded in the array; and wherein A group of quantum devices of the plurality of quantum devices is a node of the graph; A group of coupling devices in the first plurality of coupling devices is assigned a non-zero value to couple at least two quantum devices in the group of quantum devices to each other according to the graph; and A group of coupling devices in the second plurality of coupling devices is assigned a non-zero value to couple at least two quantum devices in the group of quantum devices to each other according to the graph. 44. The quantum processor of claim 43, wherein the graph is non-planar. 45. A quantum processor comprising: (i) multiple qubit devices forming individual nodes of a lattice; and (ii) a plurality of coupling devices, wherein a first coupling device of the plurality of coupling devices tunably couples a first qubit device of the plurality of qubit devices to the plurality of qubit devices A second qubit device in the device, and wherein a configuration of the first qubit device and the second qubit device in the lattice is selected from a nearest neighbor configuration and a next nearest neighbor The configuration consists of groups. 46. A computer system comprising: means for inputting a computational problem to be solved, wherein the computational problem is selected from a problem of complexity P, a problem of complexity NP, a problem of complexity NP-hard, and a problem of complexity The set of NP-complete problems; means for mapping the computational problem onto a quantum processor, wherein the quantum processor includes qubit means and means for coupling nearest neighbor and next nearest neighbor qubit means; means for obtaining a solution of the computational problem using the quantum processor; means for outputting a solution to the computational problem; and means for transmitting the solution as a data signal embodied in a carrier wave. 47. A computing system comprising: a local computer; a remote computer; a remote quantum processor in communication with the remote computer, the quantum processor comprising: (i) a plurality of quantum devices, wherein each quantum device of the plurality of quantum devices is a node of a lattice, and wherein a first quantum device of the plurality of quantum devices has a first basis state and a second base state; and (ii) a plurality of coupling devices, wherein a first coupling device of the plurality of coupling devices connects a first quantum device of the plurality of quantum devices with a second quantum device of the plurality of quantum devices Tunably coupled, wherein a configuration of the first quantum device and the second quantum device in the lattice is selected from the group consisting of a nearest neighbor configuration and a next nearest neighbor configuration; wherein the local computer is configured to send the remote computer a computational problem to be solved; and The remote computer is configured to send an answer to the computing problem to the local computer.

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