CN100585580C - Method for dynamically distributing interrupt pins - Google Patents
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- CN100585580C CN100585580C CN200710096815A CN200710096815A CN100585580C CN 100585580 C CN100585580 C CN 100585580C CN 200710096815 A CN200710096815 A CN 200710096815A CN 200710096815 A CN200710096815 A CN 200710096815A CN 100585580 C CN100585580 C CN 100585580C
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Abstract
The invention discloses a method for dynamically distributing interrupt pins, which is suitable for distributing a plurality of interrupt pins of a control chip. The method comprises the steps of firstly detecting the interrupt times of a plurality of device paths in unit time, and sequencing the device paths according to the sequence of the interrupt times of the device paths from large to small; calculating the interrupt checking times required by checking the device path sending the interrupt when each interrupt is generated on each interrupt pin; when distributing the next device path, adding the interrupted device path into each interrupt pin, and respectively calculating the interrupt checking times of each interrupt pin after the device path added with the interrupt is multiplied by a ratio according to the interrupt times of each device path; and selecting and distributing the interrupted device path to the interrupt pin with the least number of interrupt checking times.
Description
Technical field
The invention relates to a kind of wiring (Routing) method, and particularly relevant for a kind of method of dynamic assignment interrupt pins.
Background technology
(Interrup Request is when certain device will carry out specific action IRQ) to interrupt request, in order to notify and to require the processor break-off, to carry out corresponding calculating action.The transmission of this interrupt request is to carry out by so-called interrupt line, and the number of these interrupt lines can be different because of the interruptable controller that mainboard adopts.Traditional computer adopts programmable interrupt controller, and (Programmable Interrupt Controller, PIC), it includes 16 interrupt lines.Yet, being still very little the computer equipment that these interrupt lines are day by day powerful for function, input-output device is weeded out the old and bring forth the new, most interrupt line all can be occupied, even must a plurality of hardware units shared together.In view of the above, some new mainboards have then adopted advanced programmable interrupt controller (AdvancedProgrammable Interrupt Controller, APIC), this kind interruptable controller just can be managed and be generally 24 interrupt request and (be built in the IOAPIC of Intel ICHx and ESB2 series for example, but wherein some is used for information signal interruption (Message Signal Interrupt) again), and can provide the more hardware unit of number to use, more do not have the shared situation of interrupt line yet.
If use the mainboard of PIC, have only 4 interrupt lines to use usually actually for pci bus; On the other hand, if use the new mainboard of APIC, then there are 8 interrupt lines to use.Even if 6 PCI slots are arranged on this expression mainboard, they also must use 4 or 8 IRQ reluctantly.In addition, AGP (AcceleratedGraphics Port, AGP), universal serial bus (Universal Serial Bus, USB), Redundant Array of Independent Disks (RAID) (Redundant Array of Independent Disks, RAID) (Local Area Network, LAN) interface, 1394 interfaces and SATA (Serial ATA) interface also all will be used IRQ for controller and some plate-carried LANs.In this case, the situation of the shared IRQ of a plurality of PCI slots is unavoidable.
Fig. 1 illustrate is the hardware configuration of existing P IC/IOAPIC mainboard.Please refer to Fig. 1, existing P IC mainboard disposes CPU (central processing unit) 110, north bridge chips 120, South Bridge chip 130 and 4 PCI slots 140,150,160 and 170.Wherein, PCI slot 140,150,160 and 170 can transmit 4 interrupting informations (Interrupt message) INTA/INTB/INTC/INTD respectively to the wiring of the interruption on the north bridge chips 120 register (Interruptrouting register) Rx_A, Rx_B, Rx_C and Rx_D (x=1,2,3,4).And because the mainboard of PIC is only supported 4 IRQ, so north bridge chips 120 reality are when transmitting interrupting information and give South Bridge chip 130, PCI slot 140,150,160 and 170 is that shared 4 interrupt lines send interrupting information.130 of South Bridge chips are to receive respectively by north bridge chips 120 by 4 interruption route register (Interrupt router register) RA, RB, RC and RD to transmit the interrupting information of coming.These interrupting informations then can be sent to a programmable interrupt controller (8259PIC), and propose interrupt request by 8259PIC to CPU (central processing unit) 110.What deserves to be mentioned is that existing IOAPIC mainboard then is to have more an advanced programmable interrupt controller (IOAPIC) than PIC mainboard, and propose interrupt request to CPU (central processing unit) 110 by 8259PIC and IOAPIC.
Fig. 2 illustrate is the wiring allocation list of existing interrupt pins.Please refer to Fig. 2, wherein pin A, the B of each PCI slot, C, D mapping are to different interrupting information INTA/INTB/INTC/INTD, and Basic Input or Output System (BIOS) (Basic Input/Output System, BIOS) carrying out start selftest (Power-On SelfTest, POST) also can corresponding different interrupting information INTA/INTB/INTC/INTD the time, configuration is used/shared interrupt request.For instance, pin A, the B of slot # 2, C, D are that interrupting information INTD/INTA/INTB/INTC is arrived in mapping, therefore when the configure interrupt request, also be in order, storage numeral 4,1,2,3 in the interruption of correspondence wiring register R2_A, R2_B, R2_C and R2_D is so that trigger interrupt request to the interrupt pins 1,2,3 of IO APIC respectively.
If above-mentioned 4 PCI slots are all respectively plugged a pci interface card, and each pci interface card all needs to use when interrupt pins 1,2,3,4 triggers (trigger) 4 respectively and interrupts, then shared hardware unit number is 4 on each IOAPIC interrupt line, and the hardware drive program of required serial connection also all is 4 on these 4 interrupt lines.Hence one can see that, and in the case, each IOAPIC interrupt line is all identical by shared situation, has been optimized situation.
Above-mentioned method is based on situation that frequency that the PCI device that is configured on each PCI slot sends interruption the is more or less the same PCI allocation slot that gets off, yet, in the application of reality, each different PCI device sends the inferior number average of interruption in the unit interval inequality, be that some PCI device is very busy, some PCI device is then idle relatively.This characteristic still can cause interrupt pins to distribute uneven situation, so prior art still is not best allocation scheme.
Summary of the invention
In view of this, purpose of the present invention is exactly in the method that a kind of dynamic assignment interrupt pins is provided, according to the frequency that takes place on each interrupt pins to interrupt, distributor path, when interrupting to reduce each generation, judgement is which driver to send required inspection number of times by.
For reaching above-mentioned or other purposes, the present invention proposes a kind of method of dynamic assignment interrupt pins, be suitable for distributing a plurality of interrupt pins of a control chip, the method comprises the following steps: at first, detect the interruption times that takes place on the unit interval inherent multiple arrangement path, then then according to the interruption times that takes place on each device path from big to little order, calculate when every generation is interrupted on each interrupt pins, check that the required interruption in device path of sending described interruption checks number of times; When distributing next device path, device path with described interruption adds each interrupt pins earlier, interruption times according to each device path is multiplied by a proportion, calculate the device path that adds described interruption respectively after, number of times is checked in the interruption of each interrupt pins; And select the device path allocation of described interruption is checked on the interrupt pins of least number of times to interruption.
In an embodiment of the present invention, check that the required interruption in device path send interruption checks that the mode of number of times is to check by driver of the hardware unit that disposed on corresponding each device path.
In an embodiment of the present invention, calculate when one of every generation is interrupted on each interrupt pins, inspection is sent the required interruption in the device path of described interruption and is checked that the step of number of times comprises at the device path that is dispensed on each interrupt pins and set up an order, the device path ordering of the described interruption of the described a plurality of interrupt pins of wherein up-to-date adding after.
In an embodiment of the present invention, send after the required interruption in the device path of described interruption checks the step of number of times in inspection, also comprise at being dispensed to device path on each interrupt pins and set up an order, the device path ordering of the described interruption of the described a plurality of interrupt pins of wherein up-to-date adding after; And being connected in series the driver of the hardware unit that each device disposed on path according to said sequence, described hardware unit comprises interface card.
In an embodiment of the present invention, the mode that detects the interruption times that takes place on the unit interval inherent multiple arrangement path is to detect by the corresponding driver that each installs the hardware unit that is disposed on path, and these device paths and corresponding interruption times thereof then then are recorded in the storer.This storer comprise nonvolatile RAM (Non-Volatile Random Access Memory, NVRAM).
In an embodiment of the present invention, above-mentioned interrupt pins comprises and is connected to programmable interrupt controller (Programmable Interrupt Controller, PIC) and advanced programmable interrupt controller (the I/O Advanced Programmable Interrupt Controller of input and output, IOAPIC) one of them, above-mentioned control chip then comprise north bridge chips and South Bridge chip one of them.
The present invention adopts based on each hardware unit and produces the number of times that interrupts, calculate the frequency that interruption takes place on each interrupt pins, with the device path on each interrupt pins of dynamic assignment, and according to these orders of being assigned with of device paths, the driver of the hardware unit of concatenated configuration on these device paths, and can reduce when each generation is interrupted, judgement is which driver to send required inspection number of times by.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrate is the hardware configuration of existing PIC/IOAPIC mainboard.
Fig. 2 illustrate is the wiring allocation list of existing interrupt pins.
Fig. 3 is the method flow diagram of the dynamic assignment interrupt pins that illustrates according to one embodiment of the invention.
Fig. 4 is the interruption occurrence record table that illustrates according to one embodiment of the invention.
Fig. 5 is the interruption occurrence record table after the ordering that illustrates according to one embodiment of the invention.
Fig. 6 is the allocation result of the interrupt pins that illustrates according to one embodiment of the invention.
Embodiment
In order to allow the distribution of interrupt pins can reach optimization, the practice of the present invention is to carry out in the process of start selftest at BIOS, promptly send the number of times of interruption according to present each device path, the value of register on the control chip is done dynamic adjustment, and make that issuable interruption times is comparatively average on every interrupt pins, when each generation was interrupted, looking for was the inspection number of times what driver to be sent required execution by with reduction.In order to make content of the present invention more clear, below the example that can implement according to this really as the present invention especially exemplified by embodiment.
Fig. 3 is the method flow diagram of the dynamic assignment interrupt pins that illustrates according to one embodiment of the invention.Please refer to Fig. 3, present embodiment is suitable for distributing a plurality of interrupt pins of a control chip, this control chip for example is north bridge chips or South Bridge chip, these interrupt pins then for example are to be connected to programmable interrupt controller (Programmable Interrupt Controller, PIC) or the advanced programmable interrupt controller of input and output (I/O Advanced Programmable Interrupt Controller, IOAPIC).
At first, in a unit interval, detect the interruption times (step S310) that is taken place on the multiple arrangement path.This interruption times is to obtain by the driver (driver) of the hardware unit that is disposed on each device path, driver will be added up in this unit interval, number of times by the interruption that it sent, and with its pairing PCI device/functional address (PCI device/function address, PFA), data returns such as device path (the device path of broad sense comprises PCI device/functional address) and interruption times are given operating system, and collected the data of all driver repayment by operating system after, converging whole is that an interruption occurrence record table is deposited in the storer of system.Wherein, above-mentioned hardware unit for example is an interface card, and storer then for example is that (Non-Volatile Random Access Memory NVRAM), and does not limit its scope to a nonvolatile RAM.Fig. 4 is the interruption occurrence record table that illustrates according to one embodiment of the invention.Please refer to Fig. 4, wherein (Device Path, DP), the interruption times of each corresponding generation of device path institute has then been put down in writing on second hurdle in first hurdle record device path.
Then, the interruption times that takes place on path according to above-mentioned each device is to these device paths sort (step S320).Wherein, the mode of ordering for example is to adopt ordering from large to small, so that the usefulness of follow-up arrangement interrupt pins.Fig. 5 is the interruption occurrence record table after the ordering that illustrates according to one embodiment of the invention.As shown in Figure 5, in all device paths, take place interruption times maximum be 500 times of DP3; 10 times of minimum then is DP0.
At last, can install the path the preceding by ordering and begin, in regular turn each device path allocation be checked that number of times is minimum so that each interrupt pins when one of every generation is interrupted, is checked the required interruption in device path of sending interruption to interrupt pins.This step comprises the interruption times of elder generation according to the device path of precedence record, calculate on each interrupt pins each and produce when interrupting, be used for checking to be that the interruption inspection number of times (step S330) that interrupts required cost is sent in which device path, and number of times is checked in the interruption that calculates at present based on each interrupt pins, when distributing next device path, earlier this device path is added each interrupt pins, and after calculating this device path of adding respectively, when one of every generation is interrupted on each interrupt pins, inspection is sent the required interruption in device path of interruption and is checked number of times (step S340), and last just selection will be installed path allocation and be checked to interruption on the interrupt pins of least number of times (step S350).Then, judge whether that all device paths assign (step S360) all.If unallocated finishing then returns step S330 again, continue to calculate the required interruption of each interrupt pins inspection interruption at present and check number of times, and distribute next device path; Otherwise,, just finish the step of the dynamic assignment interrupt pins of present embodiment if all device paths assign all.
What deserves to be mentioned is, when present embodiment is checked number of times in the above-mentioned interruption of calculating, also comprise at the device path that is dispensed on each interrupt pins and set up an order, and this order can be via advanced framework power interface (Advanced Configuration and Power Interface, ACPI) ordered advanced framework power interface source language (ACPI Source Language, ASL) system is given in the sign indicating number repayment, and be used for being connected in series the driver of the hardware unit that is disposed on each device path, to check that interrupting is that number of times is checked in the interruption of required cost when by which driver being sent when reducing to.
Wherein, the practice of above-mentioned foundation order be with the device path ordering of up-to-date or the last adding after, and calculating when interrupting checking number of times, the interruption times that is about to each device path will be multiplied by a proportion, and, check number of times and obtain final interruption with the product addition in each device path.
For instance, suppose that the interrupt pins of present system has 4, and according to interruption occurrence record table that Fig. 5 illustrated with the device path allocation on these interrupt pins.Originally 4 all unallocated any device of interrupt pins paths, therefore will sort very naturally and be configured to respectively on these 4 interrupt pins in preceding 4 device path, the device path that dispose on each interrupt pins this moment has only one, so when number of times is checked in the interruption of calculating each interrupt pins, also be to check number of times with the interruption times in each device path as interruption, this moment, the interruption of each interrupt pins checked that number of times is as follows:
Checkcount[1]＝500
Checkcount[2]＝130
Checkcount[3]＝100
Checkcount[4]＝70
In above-mentioned these interrupt pins, check least number of times with the interruption of the 4th interrupt pins again.In view of the above, next step then is with on 4 interrupt pins of device path DP7 priority allocation to the, and recomputates the interruption inspection number of times of the 4th interrupt pins.The step of calculating comprises that elder generation sorts the pairing driver of the device path DP7 of up-to-date adding before device path DP5, calculate the interruption of the 4th interrupt pins again and check number of times, and after distributing device path DP5, total interruption of each interrupt pins checks that number of times is as follows:
Checkcount[1]＝500
Checkcount[2]＝130
Checkcount[3]＝100
Checkcount[4]＝70+60*2＝190
Wherein, since device path DP7 ordering after, if interrupt is when being sent by device path DP7, then actually checking that interrupting is when by what person being sent, can check earlier to sort and install path DP5 the preceding, if check it is not when being sent by device path DP5 that the back is found to interrupt, and just can go to check whether be to be sent by device path DP7 again.Therefore, actual calculating when interrupting checking number of times must check that number of times adds that the interruption of the required cost of testing fixture path DP5 checks number of times 60+60 time for 70 times to the interruption of the required cost of testing fixture path DP7, and always interrupted checking the result of number of times 190 times.
According to above-mentioned principle, when distributing next device path DP4, then can select to be assigned to the 3rd interrupt pins that least number of times (100 times) is checked in present interruption, and number of times is checked in the interruption of calculating the 3rd interrupt pins, and after distributing device path DP4, total interruption of each interrupt pins checks that number of times is as follows:
Checkcount[1]＝500
Checkcount[2]＝130
Checkcount[3]＝100+50*2＝200
Checkcount[4]＝70+60*2＝190
By that analogy, remaining device path is assigned on the interrupt pins of interrupting the inspection least number of times successively, can be connected in series the device path more than 2 or 2 on one of them interrupt pins, do not limit its scope.At last, total interruption that can obtain each interrupt pins checks that number of times is as follows:
Checkcount[1]＝500
Checkcount[2]＝130+40*2＝210
Checkcount[3]＝100+50*2+10*3＝230
Checkcount[4]＝70+60*2+30*3＝280
The final allocation result and the interruption of each interrupt pins check that number of times is illustrated in Fig. 6.Please refer to Fig. 6, originally total interruption times of being sent by each device path is 500+130+100+70+60+50+40+30+10=990 time, after distributing, only need 500+210+230+280=1220 time interruption to check that number of times just can check out whether interruption is sent by hardware unit own by driver via the method for the dynamic assignment interrupt pins of present embodiment.In view of the above, can reach the optimization that interrupt pins is distributed.
In sum, the method for dynamic assignment interrupt pins of the present invention has following advantage at least:
1. according to issuable interruption times on each device path, give interrupt pins with these device path mean allocation, and can effectively reduce when the generation of interruption is arranged, finding out is which driver to send required interruption by to check number of times.
2. will be dispensed to the device path ordering of same interrupt pins, and, therefore can reduce and on single interrupt pins, look for the required interruption inspection number of times of driver that sends interruption in order to the serial connection driver.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (10)
1. the method for a dynamic assignment interrupt pins, a plurality of interrupt pins that are suitable for distributing a control chip, described method comprises the following steps:
Detect the interruption times that takes place on a unit interval inherent multiple arrangement path;
, from big extremely little order sorted in described multiple arrangement path according to the interruption times that takes place on each device path;
Calculate when every generation is interrupted on each interrupt pins, check the required interruption inspection number of times in device path that sends described interruption;
When distributing next device path, device path with described interruption adds each interrupt pins earlier, interruption times according to each device path is multiplied by a proportion, calculate the device path that adds described interruption respectively after, number of times is checked in the interruption of each interrupt pins; And
Selection is checked the device path allocation of described interruption on the interrupt pins of least number of times to interruption.
2. the method for dynamic assignment interrupt pins as claimed in claim 1 is characterized in that, calculates when every generation is interrupted on each interrupt pins, and inspection is sent the required interruption in device path of described interruption and checked that the step of number of times comprises:
Set up an order at being dispensed to device path on each interrupt pins, the device path ordering of the described interruption of the described a plurality of interrupt pins of wherein up-to-date adding after.
3. the method for dynamic assignment interrupt pins as claimed in claim 1, it is characterized in that inspection is sent the required interruption in device path of described interruption and checked that the mode of number of times is to check by corresponding driver that each installs a hardware unit that is disposed on path.
4. the method for dynamic assignment interrupt pins as claimed in claim 3 is characterized in that, sends after the required interruption in the device path of described interruption checks the step of number of times in inspection, also comprises:
Set up an order at being dispensed to device path on each interrupt pins, the device path ordering of the described interruption of the described a plurality of interrupt pins of wherein up-to-date adding after; And
Be connected in series the described driver of the described hardware unit that is disposed on each device path according to described order.
5. the method for dynamic assignment interrupt pins as claimed in claim 3 is characterized in that, described hardware unit comprises interface card.
6. the method for dynamic assignment interrupt pins as claimed in claim 1, it is characterized in that the mode that detects the interruption times that takes place on the inherent described multiple arrangement path of described unit interval is to detect by the corresponding driver that each installs a hardware unit that is disposed on path.
7. the method for dynamic assignment interrupt pins as claimed in claim 1 is characterized in that, after the step that detects the interruption times that takes place in the described unit interval on described multiple arrangement path, also comprises:
The described interruption times that writes down described multiple arrangement path and correspondence thereof is in a storer.
8. the method for dynamic assignment interrupt pins as claimed in claim 7 is characterized in that, described storer comprises nonvolatile RAM.
9. the method for dynamic assignment interrupt pins as claimed in claim 1 is characterized in that, described a plurality of interrupt pins comprise be connected to the advanced programmable interrupt controller of a programmable interrupt controller and input and output one of them.
10. the method for dynamic assignment interrupt pins as claimed in claim 1 is characterized in that, described control chip comprise north bridge chips and South Bridge chip one of them.
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| CN200710096815A CN100585580C (en) | 2007-04-04 | 2007-04-04 | Method for dynamically distributing interrupt pins |
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| CN200710096815A CN100585580C (en) | 2007-04-04 | 2007-04-04 | Method for dynamically distributing interrupt pins |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152965A (en) * | 1994-06-08 | 1997-06-25 | 英特尔公司 | Disk drive connector interface for use PCI bus |
| US20030145147A1 (en) * | 2002-01-25 | 2003-07-31 | Dell Products L.P. | Information handling system with dynamic interrupt allocation apparatus and methodology |
| US6704823B1 (en) * | 2000-07-20 | 2004-03-09 | International Business Machines Corporation | Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing |
| US20050060460A1 (en) * | 2003-08-20 | 2005-03-17 | International Business Machines Corporation | Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system |
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- 2007-04-04 CN CN200710096815A patent/CN100585580C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152965A (en) * | 1994-06-08 | 1997-06-25 | 英特尔公司 | Disk drive connector interface for use PCI bus |
| US6704823B1 (en) * | 2000-07-20 | 2004-03-09 | International Business Machines Corporation | Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing |
| US20030145147A1 (en) * | 2002-01-25 | 2003-07-31 | Dell Products L.P. | Information handling system with dynamic interrupt allocation apparatus and methodology |
| US20050060460A1 (en) * | 2003-08-20 | 2005-03-17 | International Business Machines Corporation | Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system |
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