CN100583483C - Phase change memory cell and method of making same - Google Patents

Abstract

The present invention relates to a phase change memory cell, which is part of a phase change memory device, comprising: first and second electrodes; a phase change element electrically connected to the first and second electrodes; at least a portion of the phase change element includes a higher reset transition temperature portion and a lower reset transition temperature portion; and the lower reset transition temperature portion includes a phase change region that transitions from a substantially crystalline state to a substantially amorphous state by passing a current therethrough at a transition temperature that is lower than the transition temperature of the higher reset transition temperature portion.

Description

Phase change memory cell and manufacturing method thereof

parties to a joint research contract

International Business Machinery Corporation of New York, Macronix International Co., Ltd. of Taiwan, and Infineon Technologies A.G. of Germany are parties to the joint research contract.

technical field

The invention relates to a high-density storage device using phase-change storage materials and a manufacturing method thereof, and the phase-change storage materials include chalcogenide and other materials.

Background technique

Storage materials based on phase change are widely used in reading and writing optical discs. These materials include at least two solid phases, including, for example, a substantially amorphous solid phase and a substantially crystalline solid phase. Laser pulses are used in reading and writing optical discs to switch between the two phases and to read the optical properties of the material after the phase change.

These phase-change memory materials, such as chalcogenides and similar materials, can be induced to change in crystal phase by applying a current with a magnitude suitable for integrated circuits. In general, the amorphous state is characterized by a higher electrical resistance than the crystalline state, and this resistance value can be easily measured as an indication. This property has sparked interest in using programmable resistive materials to form non-volatile memory circuits, etc., which can be used for random access reading and writing.

The transition from the amorphous state to the crystalline state is generally a low current step. The transition from a crystalline state to an amorphous state (hereinafter referred to as reset) is generally a high current step, which includes a brief pulse of high current density to melt or destroy the crystalline structure, after which the phase change material will cool rapidly, inhibiting The process of phase change enables at least part of the phase change structure to be maintained in an amorphous state. Ideally, the magnitude of the reset current that causes a phase change material to transition from a crystalline state to an amorphous state should be as low as possible. To reduce the magnitude of the reset current required for reset, it can be achieved by reducing the size of the phase change material element in the memory, and reducing the contact area between the electrode and the phase change material, so that a relatively low voltage can be applied to the phase change material element. A higher current density is achieved with a small absolute current value.

One approach developed in this field is to create tiny holes in integrated circuit structures and fill them with tiny amounts of programmable resistive material. Patents devoted to these tiny holes include: U.S. Patent No. 5,687,112, issued November 11, 1997, entitled "Multibit Single Cell Memory Element Having Tapered Contact," by Ovshinky; U.S. Patent No. 5,789,277, titled "Method of Making Chalogenide[sic] Memory Device", inventors are Zahorik et al.; U.S. Patent No. 6,150,253 published on November 21, 2000, titled "Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same", the inventor is Doan et al.

Problems arise when it is desired to fabricate devices of very small size within the tight process control variables required for large-scale fabrication of memory devices. It would be advantageous to provide a memory cell structure with small dimensions and low reset current, and to provide a method of fabricating the structure that can comply with the stringent process variables required for mass production of memory devices.

Contents of the invention

The present invention describes a phase change random access memory device (PCRAM) suitable for large scale integrated circuits.

According to an object of the present invention, it provides a phase-change memory unit, which is a part of a phase-change memory device, and the phase-change memory unit includes: first and second electrodes; One is electrically connected to the second electrode; at least a part of the phase change element includes a higher reset transition temperature portion and a lower reset transition temperature portion, the lower reset transition temperature portion is positioned at the higher reset transition temperature Between temperature portions, the lower reset transition temperature portion is electrically connected to the first and second electrodes; and the lower reset transition temperature portion includes a phase change region that is substantially crystallized by passing an electric current. The transition temperature for the state transition to the roughly amorphous state is lower than the transition temperature for this higher reset change temperature portion.

According to another object of the present invention, it provides a phase-change memory cell, which is a part of a phase-change memory device. The phase-change memory cell includes: first and second electrodes, the surfaces of the two electrodes are formed by separated by a gap; the phase change element is located between the first and second electrodes and is electrically connected to the first and second electrodes; the phase change element includes a tubular exterior and an interior surrounded by the exterior, the The exterior includes a higher reset transition temperature portion and the interior includes a lower reset transition temperature portion, the reset transition temperature of the higher reset transition temperature portion being at least higher than the reset transition temperature of the lower reset transition temperature portion 100° C. or higher; and the lower reset transition temperature portion includes a phase change region that is converted from a crystalline state to an amorphous state by passing an electric current at a transition temperature lower than that of the higher reset transition temperature portion Convert temperature.

According to another object of the present invention, it provides a method for manufacturing a phase-change memory cell, which is a part of a phase-change memory device, the method comprising: electrically connecting the first and second electrodes and the phase-change element, The phase change element includes a phase change material; and, the step of electrically connecting provides a higher reset transition temperature portion and a lower reset transition temperature portion, the lower reset transition temperature portion is placed on the higher reset transition temperature portion In between, the lower reset transition temperature portion is electrically connected to the first and second electrodes, and the lower reset transition temperature portion generates a phase change region that can be substantially crystallized by passing an electric current between the two electrodes. state and a substantially amorphous state, the transition temperature of the phase change region from the crystalline state to the amorphous state by passing an electric current is lower than the transition temperature of the higher reset change temperature portion.

According to another object of the present invention, it provides a method for manufacturing a phase-change memory cell, which is a part of a phase-change memory device, the method comprising: electrically connecting the first and second electrodes and the phase-change element, The phase change element is located between and in contact with the first and second electrodes, the phase change element includes a phase change material; the reset transition temperature of the phase change material on the tubular exterior of the phase change element is changed to change between the phase change A higher reset transition temperature portion is generated on the tubular exterior of the element and a lower reset transition temperature portion is generated on the tubular interior of the phase change element, the lower reset transition temperature portion comprising a phase change region that can be activated by passing an electric current in the phase change element. The two electrodes are switched between a crystalline state and an amorphous state; and the step of changing the reset transition temperature includes implanting a material in the exterior of the phase change element to increase the reset transition temperature of the exterior, generating The higher resets the transition temperature part.

The method of the present invention involves forming guide bridges or other phase change devices in PCRAM memory cells, and this method can be used to manufacture tiny guide bridges for other purposes. Nanotechnology devices with very small phase change structures, using materials other than phase change materials, including metals, dielectrics, organic materials, semiconductors, etc.

The structure and method of the present invention will be described in detail below. The purpose of this summary of the invention is not to limit the invention. The invention is defined by the claims. All embodiments, features, objects and advantages of the present invention can be fully understood through the following description, claims and accompanying drawings.

Description of drawings

FIG. 1 shows an embodiment of a thin film guided bridge phase change memory element.

FIG. 2 shows the current path of the thin film bridge phase-change memory element in FIG. 1 .

FIG. 3 shows a phase-change active region of the thin-film guided bridge phase-change memory element of FIG. 1 .

FIG. 4 shows the dimensions of the thin film guided bridge phase-change memory element in FIG. 1 .

Figure 5 shows a pair of phase change memory elements with access circuitry below the electrode layer and bit lines above the electrode layer.

FIG. 6 is a layout diagram of the structure of FIG. 5 .

FIG. 7 is a schematic diagram of a memory array including phase change memory elements.

FIG. 8 is a block diagram of an integrated circuit device including a thin film resistive phase change memory array and other circuitry.

FIG. 9 is a cross-sectional view of a substrate including circuits formed by a front-end process and fabricated in a step of fabricating the phase change memory element structure of FIG. 5. FIG.

FIG. 10 shows a cross-sectional view of an initial step of a formation step for forming an electrode layer in the structure of FIG. 5 .

11A and 11B show plan and cross-sectional views of patterning the structure of FIG. 10 to form electrode stacks in electrode layers.

FIG. 12 shows a cross-sectional view of a corresponding step of forming sidewall isolation on the electrode stack of FIG. 11B .

FIG. 13 shows a cross-sectional view of the corresponding steps of forming a layer of conductive material on the structure of FIG. 12 .

FIG. 14 shows a cross-sectional view of the corresponding step of grinding the conductor material away from the sidewalls in the structure of FIG. 13 .

FIG. 15 shows a cross-sectional view of corresponding steps of forming a phase change material thin film layer and a protective covering layer on the structure in FIG. 14 .

16A and 16B show plan and cross-sectional views of corresponding steps of patterning the phase change material thin film layer of FIG. 15 , including forming strips of photoresist on the phase change material.

17A and 17B show plan and cross-sectional views of corresponding steps of patterning the phase change material thin film layer of FIG. 15 , including etching the strip photoresist of FIGS. 16A and 16B to form narrower strip photoresist.

18A and 18B show a plan view and a cross-sectional view of a phase change strip structure after etching the phase change material film layer according to the photoresist pattern of FIGS. 17A and 17B .

FIGS. 19A and 19B are plan views and cross-sectional views of the stripe pattern of phase change material in FIGS. 18A and 18B , which are used to form bridges of phase change material on the electrode layer.

20A and 20B show plan and cross-sectional views of phase change material bridges after etching according to the pattern of FIGS. 19A and 19B .

Figure 21 shows a cross-sectional view of forming a dielectric layer on the structure of Figures 20A and 20B (including the electrode layer and the phase change bridge),

22A and 22B illustrate plan and cross-sectional views of the structure of FIG. 21 forming a conductive plug in a layer of dielectric material contacting a phase change material bridge.

FIG. 23 shows cross-sectional views of corresponding steps of forming a patterned conductive layer on the structure of FIGS. 22A and 22B .

Figures 24-41 illustrate embodiments of the invention wherein the phase change material includes higher and lower change temperature portions.

Figure 24 shows phase change material deposited on first and second electrodes separated by an insulating member.

FIG. 25 shows the result of the structure of FIG. 24 after depositing a photoresist mask mask and etching steps.

Figure 26 shows the result of the structure of Figure 25 undergoing a mask trimming step.

Fig. 27 shows the result of implanting elements on the exposed part of the phase change material.

28 and 29 are schematic and cross-sectional views of a phase change memory cell with the photoresist mask removed.

Figure 30 shows an alternative implantation technique to Figure 27, where the implantation is performed at an oblique angle to create a smaller phase change region.

Figure 31 shows a cross-sectional view taken along line 31-31 of Figure 30 showing the narrower phase change region created by the off-angle implant.

Fig. 32 is a simplified cross-sectional view of a phase change memory device of the present invention.

FIG. 33 shows the memory cell access layer of FIG. 32 .

FIG. 34 shows the result of depositing a layer of phase change material on the memory cell access layer of FIG. 33 .

FIG. 35 shows the result of forming a lithographic mask on the phase change material layer of FIG. 34 .

FIG. 36 shows the result of etching the exposed phase change material in FIG. 35 to create a phase change element.

FIG. 37 shows trimming results for the lithographic mask of FIG. 36 .

Figure 38 shows the results of implanting in the exposed generally tubular exterior of the phase change element.

FIG. 39 shows the result of removing the lithography mask and depositing an oxide layer on the memory cell access layer and the upper surface of the phase change device.

FIG. 40 shows the results of chemical mechanical polishing of the structure of FIG. 39 .

FIG. 41 is a simplified perspective view of the phase change element of FIG. 40. FIG.

Description of main component symbols

10 storage units

11 storage material guide bridge

12 first electrode

13 Second electrode

14 Insulation components

12a, 13a, 14a upper surface

16 active channels

20 Semiconductor substrate

23, 24 Polysilicon word lines

25, 26, 27 n-type terminals

28 Common source line

29, 30 Embolic structures

31 electrode layer

32～34 electrode assembly

35a, b insulation barrier

36, 37 Thin film storage material guide bridge

38 Tungsten plug

39 Substrate components

40 patterned conductive layer

41, 42 Metal bit lines

45 Y decoder and word line driver

46 X decoder and sense amplifier

50-53 access transistor

60 storage arrays

61 column decoder

62 word line

63 line decoder

64 bit line

65, 67 bus

66 Sense amplifier and data read-in

69 Bias Arrangement State Machine

71 Data input circuit

72 Data output circuit

74 Other circuits

75 integrated circuits

99 structure

101, 102 groove

103～105 Doped area

106 source line

107 polysilicon

108 silicide covering layer

109 Medium layer

110, 112, 113, 114 Embolization

111 Polysilicon wire

115, 116 Doped regions

117, 118 word line

120 Thin dielectric layer

121 Conductive electrode material layer

130～132 Electrode stack

133, 134 side wall

140～143 Media side wall

150 electrode material layer

160～162 Electrode assembly

163, 164 Insulation components

170 film layer

171 Protective covering

180 photoresist layer

180a, 180b Strip photoresist

190 photoresist layer

190a, 190b Strip photoresist

200 Thin film storage material layer

201 Protective covering

210, 211 Photoresist layer

210a, 210b, 211a, 211b, 212a, 212b photoresist structure

215 The first electrode assembly

216 Second electrode assembly

217 The third electrode assembly

218 Storage material guide bridge

220～222 Unit structure

220a, b, 221a, b, 222a, b unit structure

225～227 Groove

230 medium filling layer

240～242 embolism

240a,b Embolization

250 Conductive layer

310 phase change memory cells

311 phase change guide bridge

312 first electrode

313 second electrode

314 Insulation components

316 phase change materials

318 photoresist mask

320 smaller size masks

322 Implantation

324 Higher change temperature part

326 Lower change temperature part

328 phase change region

410 phase change memory device

412 storage unit access layer

414 storage unit layer

416, 418 second grid

420, 422 First and second embolization

424 common source line

426 Dielectric film layer

428 flat upper surface

430 Electrode Surface

432 phase change material layer

434 Lithographic masks

436 phase change element

440 Implantation

442 Tubular exterior

444 internal (core)

446 oxide layer

448 surface

450 outer end

452 bit lines

454 electrode surface

456 central area

Detailed ways

The thin film fuse phase change memory cells, memory arrays thereof, and methods for manufacturing these cells of the present invention will be described in detail below with reference to FIGS. 1-23. The embodiments of FIGS. 24-31 are a first set of examples of phase change memory cells with higher and lower reset change temperature portions. The embodiments of FIGS. 32-41 are a second set of examples of phase change memory cells with higher and lower reset change temperature portions.

The following description of the invention generally refers to specific structural embodiments and methods. It should be understood that there is no intent to limit the invention to the particular disclosed embodiments and methods. The method can be implemented using other features, elements, methods and embodiments. Similar elements in different embodiments are generally designated with similar reference numerals.

Fig. 1 shows the basic structure of a memory cell 10, which includes a storage material bridge 11 on an electrode layer, the electrode layer includes a first electrode 12, a second electrode 13, and includes an electrode between the first electrode 12 and the second electrode 13 Insulation assembly 14. As shown, the first and second electrodes 12, 13 have upper surfaces 12a, 13a, respectively. Similarly, the insulating component 14 also has an upper surface 14a. The upper surfaces 12a, 13a, 14a of the electrode layers define a substantially planar upper surface on the electrode layers of the illustrated embodiment. The storage material bridges 11 are located on the flat upper surface of the electrode layer such that contacts between the first electrode and the bridges 11 , and between the second electrode 13 and the bridges 11 are formed via the bottom side of the bridges 11 .

FIG. 2 shows the current path between the first electrode 12 , the bridge 11 and the second electrode 13 in the memory cell structure. The access circuit can be contacted to the first electrode 12 and the second electrode 13 using different configurations to control the operation of the memory cell such that it can be programmed to set the bridge 11 in one of the two solid phases, thus Two solid state phases can be reversibly implemented using memory materials. For example, using a chalcogenide phase change memory material, the memory cell can be set to a relatively high resistivity state as well as a relatively low resistivity state, wherein at least a portion of the bridge in the current path is amorphous State, to achieve a high resistivity state, and most of the bridge in the current path is in a crystalline state, to achieve a low resistivity state.

Figure 3 shows the active channels of the guide bridge 11, wherein the active channel 16 is the region where the material is induced to transition between at least two solid state phases. It will be appreciated that the active channel 16 can be very small in the configuration shown to reduce the magnitude of the current required to induce the phase change.

FIG. 4 shows important dimensions of the storage unit 10 . The length L (x-axis) of the active region 20 is defined by the thickness of the insulating component 14 (referred to as channel medium in the figure) between the first electrode 12 and the second electrode 13 . This length L can be controlled by controlling the width of the insulating member 14 in the memory cell embodiment. In a representative embodiment, the insulating walls 14 are wide enough to form thin sidewall dielectric layers on the sides of the electrode stack using thin film deposition techniques. Accordingly, the channel length L in embodiments of the memory cell is less than 100 nanometers. The channel length L in other embodiments is 40 nm or less. In other embodiments, the channel length is less than 20 nanometers. It can be understood that the channel length can even be much smaller than 20 nanometers, which can be realized by thin film deposition techniques such as atomic layer deposition depending on the requirements of specific applications.

Similarly, the bridge thickness T (y-axis) in memory cell embodiments can be very small. The bridge thickness T may be formed on the upper surfaces of the first electrode 12 , the insulating component 14 , and the second electrode 13 by using a thin film deposition technique. Therefore, in the embodiment of the memory cell, the thickness T of the guide bridge is less than 50 nanometers. In other embodiments of the memory unit, the thickness of the guide bridge is less than 20 nanometers. In other embodiments, the thickness T of the guide bridge is less than 10 nanometers. It can be understood that the thickness T of the guide bridge can even be less than 10 nanometers by using techniques such as atomic layer deposition, depending on the needs of specific applications, as long as the thickness is sufficient for the guide bridge to achieve its purpose as a storage element, even if the guide bridge It has at least two solid phases and can be reversibly induced by applying a current or voltage between the first and second electrodes.

As shown in FIG. 4, the guide bridge width W (z axis) is also very small. In a preferred embodiment, the bridge width W is less than 100 nm. In some embodiments, the bridge width is less than 40 nanometers.

Examples of memory cells include phase change memory materials in the bridge 11, including chalcogenide materials and others. Chalcogenides include any of the four elements: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), which form part of Group VI on the periodic table. Chalcogenides include the combination of chalcogen elements with more electropositive elements or free radicals. Chalcogenide alloys include combining chalcogenides with other substances such as transition metals, etc. Chalcogenide alloys generally include one or more elements selected from the sixth column of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include complexes of one or more of the following elements: antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical papers, including the following alloys: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb /tellurium, gallium/selenium/tellurium, tin/antimony/tellurium, indium/antimony/germanium, silver/indium/antimony/tellurium, germanium/tin/antimony/tellurium, germanium/antimony/selenium/tellurium, and tellurium/germanium/ Antimony/Sulphur. Within the germanium/antimony/tellurium alloy family, a wide range of alloy compositions can be tried. This composition can be represented by the following characteristic formula: Te _a Ge _b Sb _100-(a+b) .

One researcher described the most useful alloys as containing an average tellurium concentration in the deposited material well below 70%, typically below 60%, and in general type alloys ranging from a minimum of 23% Up to 58%, and optimally a tellurium content between 48% and 58%. The concentration of germanium is above about 5%, and its average range in the material is from a minimum of 8% to a maximum of 30%, generally below 50%. Optimally, the germanium concentration ranges from 8% to 40%. The remaining major component in this composition is antimony. The above-mentioned percentages are atomic percentages, and the sum of all constituent elements is 100%. (Ovshinky '112 patent, columns 10-11) Special alloys evaluated by another investigator include Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ , and GeSb ₄ Te ₇ (Noboru Yamada, "Potential of Ge-Sb -Te Phase-change Optical Disks for High-Data-Rate Recording", SPIE v.3109, pp.28-37(1997)). More generally, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys of the above can be combined with germanium/antimony/ Tellurium combines to form a phase change alloy that includes programmable resistive properties. Specific examples of memory materials that may be used are described in the Ovshinsky '112 patent at columns 11-13, examples of which are incorporated herein by reference.

The phase change alloy is capable of switching between a first structural state in which the material is generally amorphous and a second structural state in which the material is generally crystalline solid, in sequence of its position within the active channel region of the unit. These materials are at least bistable. The term "amorphous" refers to a relatively disordered structure, which is more disordered than a single crystal, yet has detectable characteristics, such as higher electrical resistance than the crystalline state. The term "crystalline state" refers to a relatively ordered structure that is more ordered than the amorphous state and thus includes detectable features such as lower electrical resistance than the amorphous state. Typically, phase change materials are electrically switchable to all detectably different states between fully crystalline and fully amorphous. Other material properties affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. This material can be switched into different solid states, or can be switched into a mixture of two or more solid states, providing a gray scale part between the amorphous state and the crystalline state. Electrical properties in this material may also change accordingly.

Phase change alloys can be switched from one phase state to another by applying an electrical pulse. Previous observations indicate that shorter, higher amplitude pulses tend to change the phase state of a phase change material to a substantially amorphous state. Longer, lower amplitude pulses tend to change the phase state of the phase change material to a substantially crystalline state. The energy in the shorter, larger-amplitude pulses is high enough to break the bonds of the crystalline structure, but short enough to prevent the atoms from rearranging into a crystalline state. Appropriate pulse volumetric curves that are particularly suitable for a particular phase change alloy can be determined without undue experimentation. In the remainder of this article, this phase change material will be referred to as GST, while it should be understood that other types of phase change materials can also be used. One suitable material for use in PCRAM described herein is Ge ₂ Sb ₂ Te ₅ , and is commonly referred to as GST.

The present invention is described in relation to phase change materials. However, other storage materials (also sometimes referred to as programmable materials) may also be used. In the present invention, the storage material is a material whose electrical properties (such as resistance value, etc.) can be changed by applying energy; the change can be stepwise change, continuous change, or a mixture of the two. Other programmable storage materials that can be used in other embodiments of the present invention include _N2 -doped GST, _GexSby , or other substances whose resistance is determined by changes _in different crystal states _{; PrxCayMnO3} , _PrSrMnO , ZrO _x or other materials that use electric pulses to change the state of resistance; or other substances that use electric pulses to change the state of resistance; tetracyanodimethylbenzoquinone (TCNQ, 7,7,8,8-tetracyanoquinodimethane), methane Fullerene 66 phenyl C61 butyric acid methyl ester (PCBM, methanofullerene6, 6-phenyl C61-butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other substances , or any other polymeric material comprising bistable or multistable resistance states controlled by electrical pulses. Other examples _of programmable resistive memory materials include: GeSbTe, GeSb, NiO, Nb- _SrTiO3 , Ag-GeTe, PrCaMnO, ZnO, _Nb2O5 , Cr- _SrTiO3 .

For information on the manufacture, component materials, use and operation of phase change random access memory devices, please refer to U.S. Patent Application No. 11/155,067, filed on 2005/6/14, entitled "Thin Film Fuse Phase Change Ram and Manufacturing Method".

Figure 5 shows the structure of a PCRAM cell. This cell is formed on a semiconductor substrate 20 . An insulating structure, such as a shallow trench isolation dielectric (STI) (not shown), separates the paired columns of memory cell access transistors. This access transistor is formed in a p-type substrate 20 with n-type terminal 26 serving as a common source region and n-type terminals 25, 27 serving as drain terminals. The polysilicon word lines 23, 24 serve as the gates of the access transistors. A dielectric fill layer (not shown) is formed over the polysilicon wordlines. This layer is a patterned conductive structure, forming eg common source line 28 and plug structures 29 , 30 . The conductive material can be tungsten or other materials, and combinations of materials suitable for plug and circuit structures. The common source line contacts source region 26 and acts as a common source line along a column in the array. Plug structures 29, 30 are contacted to drain terminals 25, 26, respectively. The filling layer (not shown), the common source line 28 , and the plug structures 29 , 30 all have substantially flat upper surfaces, and are suitable as substrates for forming the electrode layer 31 .

The electrode layer 31 comprises electrode components 32 , 33 , 34 separated from each other by insulating components such as insulating side walls 35 a , 35 b , and a substrate component 39 . In the structure of this embodiment, the substrate assembly 39 may be thicker than the insulating gates 35a, 35b and isolate the electrode assembly 33 from the common source line 28 . For example, the thickness of the substrate assembly can be between 80 and 140 nm, while the insulating gate is much narrower because the capacitive coupling between the source line 28 and the electrode assembly 33 must be reduced. In this embodiment, the insulating gates 35a, 35b include a thin film dielectric material on the sidewalls of the electrode components 32, 34, and the thickness on the surface of the electrode layer 31 is determined by the thickness of the film on the sidewalls.

A thin-film storage material bridge 36 (such as GST) is located on one side of the electrode layer 31, across the insulating sidewall 35a to form a first memory cell, while a thin-film storage material bridge 37 (such as GST) is located on the other side of the electrode layer 31. On one side, a second memory cell is formed across the insulating gate 35b.

A dielectric fill layer (not shown) overlies the thin film bridges 36,37. The dielectric fill layer includes silicon dioxide, polyimide, silicon nitride, or other dielectric fill materials. In an embodiment, the fill layer comprises a relatively good thermal and electrical insulator, providing good thermal and electrical isolation of the conductive bridge. The tungsten plug 38 is in contact with the electrode assembly 33 . A patterned conductive layer 40 comprising metal or other conductive material (including the bit lines in the array structure) overlies the dielectric fill layer and contacts plug 38 to establish memory cells corresponding to thin film bridges 36 and 37 access.

FIG. 6 shows the structure on the semiconductor substrate 20 of FIG. 5 in a layout manner. Therefore, the arrangement of the word lines 23, 24 is substantially parallel to the common source line 28, and is arranged along the common source line in the memory cell array. The plugs 29, 30 contact the terminals of the access transistors in the semiconductor substrate, and the bottom sides of the electrode assemblies 32, 34, respectively. The conductive bridges 36, 37 of thin film storage material are located on the electrode assemblies 32, 33, 34 and the insulating gates 35a, 35b, which separate the electrode assemblies. The plug 38 contacts the bottom side of the electrode assembly 33 between the bridges 35 and 37 and the metal bit line 41 (transparent in FIG. 6 ) under the patterned conductive layer 40 . Metal bit lines 42 (non-transparent) are also shown in FIG. 6 to emphasize the array layout of this structure.

In operation, access to memory cells corresponding to bridge 36 is accomplished by applying control signals to word line 23, which connects common source line 28 via terminal 25, plug 29, and electrode assembly 32 to Film guide bridge 36. The electrode assembly 33 is connected to a bit line in the patterned conductive layer 40 via the contact plug 38 . Similarly, access to memory cells corresponding to the bridge 37 is achieved by applying control signals to the word line 24 .

It will be appreciated that a variety of different materials may be used in the structures of FIGS. 5 and 6 . For example, copper metallization may be used. Other types of metallization, such as aluminum, titanium nitride, and tungsten-containing materials, etc., can also be used. Meanwhile, non-metal conductive materials such as doped polysilicon can also be used. The electrode material used in the above embodiments is preferably titanium nitride or tantalum nitride. Alternatively, the electrode may be aluminum titanium nitride or aluminum tantalum nitride, or may include more than one element selected from the following group: titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), tantalum (Ta), copper (Cu), platinum (Pt), iridium (Ir), lanthanum (La), nickel (Ni), and ruthenium (Ru), and alloys composed of these elements. The inter-electrode insulating gates 35a, 35b can be silicon dioxide, silicon oxynitride, silicon nitride, aluminum oxide, or other low dielectric constant dielectrics. Alternatively, the interelectrode insulating layer may include one or more elements selected from the group consisting of silicon, aluminum, fluorine, nitrogen, oxygen, and carbon.

FIG. 7 shows a schematic diagram of a memory array, which may be implemented with reference to the description made with reference to FIGS. 5 and 6 . Therefore, the reference numerals in FIG. 7 correspond to the reference numerals in FIGS. 5 and 6 . It can be appreciated that the array structure shown in FIG. 7 can be implemented with other cell structures. In the illustration of FIG. 7 , common source line 28 , word line 23 , and word line 24 are substantially parallel to the Y axis. Bit lines 41 and 42 are substantially parallel to the X-axis. Therefore, the Y decoder and the wordline driver in block 45 are connected to the wordlines 23,24. The X decoder in block 46 and a set of sense amplifiers are then connected to the bit lines 41,42. The common source line 28 is connected to the source terminals of the access transistors 50 , 51 , 52 , 53 . The gate of the access transistor 50 is connected to the word line 23 . The gate of the access transistor 51 is connected to the word line 24 . The gate of the access transistor 52 is connected to the word line 23 . The gate of the access transistor 53 is connected to the word line 24 . The drain of the access transistor 50 is connected to the electrode assembly 32 to connect to the conductive bridge 35 , and the conductive bridge 35 is further connected to the electrode assembly 34 . Similarly, the drain of the access transistor 51 is connected to the electrode assembly 33 to connect to the bridge 36 , which in turn is connected to the electrode assembly 34 . The electrode assembly 34 is connected to the bit line 41 . For the convenience of illustration, the electrode assembly 34 and the bit line 41 are located at different positions. It can be understood that in other embodiments, different memory cell bridges can use different electrode assemblies. Access transistors 52 and 53 are also connected on bit line 42 to corresponding memory cells. It can be seen from the figure that the common source line 28 is shared by two columns of memory cells, and the columns are arranged along the Y axis. Similarly, the electrode assembly 34 is shared by two memory cells in one row of the array, and the rows in the array are arranged along the X-axis.

Figure 8 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. Integrated circuit 75 includes memory array 60 built on a semiconductor substrate using thin film fuse phase change memory cells. The row decoder 61 is connected to a plurality of word lines 62 and arranged along each row in the memory array 60 . The column decoder 63 is connected to a plurality of bit lines 64 arranged along each column in the memory array 60 for reading and programming data from the thin film phase change memory cells in the array 60 . The address is supplied on bus 65 to column decoder 63 as well as to row decoder 61 . The sense amplifiers and data input structures in block 66 are connected to column decoder 63 via bus 67 . Addresses are supplied from bus 65 to column decoder 63 and row decoder 61 . The sense amplifiers and data read-in lines in block 66 are connected to column decoder 63 via data bus 67 . Data is provided to the data input structures of block 66 via data input lines 71 from input/output ports of integrated circuit 75 , or from other internal or external data sources of integrated circuit 75 . In the illustrated embodiment, the integrated circuit includes other circuits 74, such as a general purpose processor or a dedicated application circuit, or an integrated module that provides system-on-a-chip functionality supported by an array of thin-film insurance phase-change memory cells. Data is transmitted from the sense amplifiers in block 66 via data output lines 72 to input/output ports of integrated circuit 75 , or to other data destinations internal or external to integrated circuit 75 .

In this embodiment, the controller of the bias arrangement state machine 69 is used to control the application of the bias arrangement supply voltage 68, such as read, program, erase, erase confirm and program confirm voltages. This controller can use well-known special purpose logic circuits. In an alternative embodiment, the controller includes a general-purpose processor, which can be implemented in the same integrated circuit that executes the computer program to control the operation of the device. In yet another embodiment, the controller uses a combination of special purpose logic and a general purpose processor.

FIG. 9 shows the structure 99 after the front-end process, forming standard CMOS elements, which in the illustrated embodiment correspond to the word lines, source lines, and access transistors in the array shown in FIG. 7 . In FIG. 9, the source line 106 covers the doped region 103 in the semiconductor substrate, wherein the doped region 103 corresponds to the first access transistor on the left in the figure and the second access transistor on the right in the figure. The source terminal of the transistor. In this embodiment, source line 106 extends to the upper surface of structure 99 . In other embodiments, the source line does not extend completely to the surface. The doped region 104 corresponds to the drain of the first access transistor so far. A word line comprising polysilicon 107 and a silicide capping layer 108 serves as the gate of the first access transistor. The dielectric layer 109 is located on the polysilicon 107 and the silicide capping layer 108 . The plug 110 contacts the doped region 104 and provides a conductive path to the surface of the structure 99 for connection to the memory cell electrode in the manner described below. A word line including a polysilicon line 111 and a silicide capping layer (not shown) serves as the gate of the second access transistor. Plug 112 contacts doped region 105 and provides a conductive path to the upper surface of structure 99 for connection to the memory cell electrode in the manner described below. Isolation trenches 101, 102 separate the two-transistor structure coupled to plugs 110 and 112 from adjacent two-transistor structures. On the left side of the figure, doped regions 115, word line polysilicon 117 and plugs 114 are shown. On the right side of the figure, doped regions 116, wordline polysilicon 118 and plugs 113 are shown. Structure 99 in FIG. 9 provides a substrate for forming memory cell elements, including first and second electrodes, and memory material bridges, as described in more detail below.

FIG. 10 shows the next step in the process, where a thin dielectric layer 120 comprising silicon nitride or other materials such as silicon dioxide, silicon oxynitride, aluminum oxide, etc., is formed on the surface of structure 99 . Next, a conductive electrode material layer 121 such as titanium nitride (TiN) or a suitable conductive material such as titanium nitride (such as tantalum nitride, aluminum alloy, copper alloy, doped polysilicon, etc.) is formed on the dielectric layer 120 .

11A and 11B show the next step in this process, where the conductive electrode layer 121 and the dielectric layer 120 are patterned to define electrode stacks 130, 131, 132 (131a, 132a in FIG. 11A ) on the surface of the structure 99. , 133a). In one embodiment, the electrode stack is defined by a mask lithography step, which creates a patterned photoresist layer, followed by known dimensional measurement and determination steps, and then etches titanium nitride and silicon nitride for to form the structure of layers 121 and 120 . The stack has sidewalls 133 and 134 .

Figure 12 shows the next step of this process, wherein the dielectric sidewalls 140, 141, 142, 143 are formed on the stacks 130, 131 by forming a thin film dielectric layer (not shown) conformal to the stack and the sidewalls of the stack. , on the sidewalls of 132, and then anisotropically etches the thin film dielectric layer to remove it from the area between the stacks and the stack surface, leaving the remaining formed on the sidewalls. In an embodiment of the process, the material used to form the sidewalls 140 , 141 , 142 , 143 includes silicon nitride or other dielectric materials such as silicon dioxide, silicon oxynitride, aluminum oxide, and the like.

FIG. 13 shows the next step in the process, where a second electrode material layer 150 is formed over the stacks 130 , 131 , 132 and sidewalls 140 , 141 , 142 , 143 . The electrode material layer 150 includes titanium nitride or other suitable conductive materials, such as tantalum nitride, aluminum alloy, copper alloy, doped polysilicon, and the like.

Figure 14 shows the next step in this process, where the second electrode material layer 150, sidewalls 140, 141, 142, 143, and stacks 130, 131, 132 are etched and planarized to define the electrode layer in structure 99 provided on the substrate. Examples of abrasive processes include chemical mechanical abrasive processes followed by brush cleaning and liquid or gas cleaning procedures, as are known in the art. The electrode layer includes electrode components 160, 161, 162, and insulating components 163, 164 between the electrode components. The electrode layer, in the described embodiment, has a substantially planar upper surface. In this embodiment, parts of the insulating components 163, 164 also extend below the electrode component 161 to isolate the electrode component 161 from the source line. In other exemplary structures, different materials may be used for the electrode assembly and the insulation assembly.

Figure 15 shows the next step in this process, in which a thin film phase change memory material layer 170 is formed on the substantially planar surface of the electrode layer. The memory material is deposited at about 250° C. using misaligned sputtering. When the phase change storage material used is Ge ₂ Sb ₂ Te ₅ , the thickness of the formed film is about 60 nanometers or less. Embodiments involve sputtering the entire wafer onto its flat surface to a thickness of about 40 nanometers. In some embodiments, the thickness of the thin film layer 170 is less than 100 nanometers, and more preferably less than 40 nanometers. In an embodiment of the memory device, the thin film layer 170 has a thickness of less than 20 nanometers, such as 10 nanometers. After the thin film layer 170 is formed, a protective cover layer 171 is formed. The protective cover layer includes low temperature deposited silicon dioxide or other dielectric material formed on the thin film layer 170 . The protective cover layer 171 is preferably a good electrical and thermal insulator, and protects the memory material from exposure during subsequent steps, such as photoresist stripping steps, which may damage the memory material. This process involves forming a low temperature substrate dielectric, eg a silicon nitride layer or a silicon dioxide layer, using a process at a temperature below 200°C, for example. One of the suitable processes is the application of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD). After the protective cap layer 171 is formed, a dielectric filling layer can be applied on the storage material by using a high temperature process such as high density plasma chemical vapor deposition (HDPCVD).

Figures 16A and 16B illustrate the next step in the process, in which a photoresist layer 180 is formed and patterned in a mask lithography process to define strips of photoresist 180a, 180b over the thin film layer 170 and protective cover layer 171 . As shown in FIG. 16A, insulating components 163, 164 are exposed between strip photoresists 180a, 180b. Depending on the lithography process used, this strip photoresist should be as thin as possible. For example, the width of the strip photoresist is equal to the minimum feature size F of the lithography process used, where in the current mask lithography process, the minimum feature size of the process can be 0.2 microns, 0.14 microns, or 0.09 order of magnitude of microns. Clearly, embodiments of this process can achieve narrower minimum feature sizes as the lithographic process advances.

Figures 17A and 17B illustrate the next step in the process, where the strip photoresist 180a, 180b of Figure 16A is trimmed to form narrower strip photoresist 190a, 190b. As shown in FIG. 17B, the thickness of the trimmed photoresist 190 is also smaller than the thickness of the photoresist layer 180 in FIG. 16B. In one embodiment, the strip photoresist is trimmed by isotropic etching, which uses a process such as reactive ion etching. This etch process trims the strip photoresist to smaller line widths. In an embodiment of the narrower strip photoresist 190a, 190b, the width is less than 100 nanometers. In other embodiments of the narrower strip photoresist 190a, 190b, the width is less than 40 nanometers. Photoresist trimming uses oxygen plasma to isotropically etch the photoresist to trim its width and thickness to ~40nm in a lithography process with a minimum feature size of 0.09 micron (90nm). In an alternative embodiment, a hard mask layer, such as a layer of low temperature deposited silicon nitride or silicon dioxide, can be placed at the bottom of the photoresist pattern to avoid etching damage to the memory material during the photoresist stripping process.

Figures 18A and 18B illustrate the next step in the process, where narrower strips of photoresist 190a, 190b are used as etch masks while a lithographic etch is performed on the thin film memory material layer 200 to define the strips of memory material 200a, 200b , whether there is a protective cover layer 201 or not. As shown, the strips of memory material 200a, 200b extend across the insulating assemblies 163, 164, as well as electrically. In an embodiment of the process, the memory material comprises a GST chalcogenide material and is etched using, for example, a chlorine or fluorine reactive ion etching process.

Figures 19A and 19B illustrate the next step in the process, where another photoresist layer 210, 211, 212 is formed and patterned to define photoresist structures 210a, 210b, 211a, 211b, 212a, 212b. This cell structure corresponds to pairs of memory cells, as described below. This cell structure is wider than the strip-shaped memory material 200a, 200b because it is equal to the width achievable by the lithography process used (eg, photomask lithography process) and is not trimmed. Thus, the width in some embodiments is equal to the minimum feature size F of the lithographic process used to form this layer.

Figures 20A and 20B illustrate the next step in this process, wherein photoresist structures 210a, 210b, 211a, 211b, 212a, 212b use the left etch mask, by etching trenches 225, 226 for the isolation dielectric structure of structure 99, and Trenches 227 perpendicular to the word lines are etched between rows of cells to define cell structures 220a, 220b, 221a, 221b, 222a, 222b (220, 221, 222 in FIG. 20B). The unit structure 220 a includes a first electrode assembly 215 , a second electrode assembly 216 , and a third electrode assembly 217 . The insulating component 163 separates the first electrode component 215 and the second electrode component 216 . The insulating component 164 separates the first electrode component 215 and the third electrode component 217 . Memory material bridges 218 are positioned over electrode assemblies 215 , 216 , 217 and insulating assemblies 163 , 164 to create two memory cells on structure 220 .

FIG. 21 shows the next step in the process, where a dielectric fill layer 230 with a flat upper surface is formed over the electrode structures and fills the trenches and trenches between the electrode structures. In an embodiment of the process, the fill layer 230 is deposited using high density plasma chemical vapor deposition (HDPCVD), followed by chemical mechanical polishing and cleaning. The dielectric fill layer may include silicon dioxide, silicon nitride, and other insulating materials, preferably having good thermal and electrical insulating properties.

In some embodiments, a thermal isolation structure for the conductive bridge is provided in addition to, or instead of, the dielectric fill layer. In an embodiment, this thermally insulating structure is achieved by providing a thermally insulating cover layer on the bridge (218), which selectively covers the electrode layer, prior to applying the dielectric fill layer. Representative materials of the thermal insulating material layer include materials composed of the following elements: silicon, carbon, oxygen, fluorine, and hydrogen. Thermally insulating materials suitable for use as thermally insulating cover layers include silicon dioxide, silicon oxycarbide, polyimide, polyamide, and fluorocarbon polymers. Other materials suitable for use in the insulating layer include fluorinated silicon dioxide, silsesquioxane, polyarylene ether, parylene, fluoropolymers, Fluorine amorphous carbon, diamond-like carbon, porous silica. In other embodiments, the thermal isolation structure includes gas-filled cavities in the dielectric filling layer formed on the conductive bridge 218 to provide thermal insulation. Single or multiple layers can provide thermal and electrical insulation.

Figures 22A and 22B illustrate the next step in the process, where vias (not shown) are etched in the fill layer 230, through the memory material and fill layer to the electrode material. The via etch process can use a single anisotropic etch process to etch the fill layer and memory material layer, or use a two-stage process where the fill layer is etched with a first etch chemistry and the memory is etched with a second etch chemistry. material layer. After the via hole is formed, the via hole is filled with tungsten metal or other conductive material to form a plug 240 (240a, 240b in FIG. 22A ), 241, 242 contacting the first electrode component (such as component 215) in the electrode structure. , to make electrical connection with the circuit on the electrode layer. In an embodiment of the process, the vias are substrated with a diffusion barrier layer and/or an adhesion layer, as known in the art, and filled with tungsten metal or other suitable conductive material. The structure is then planarized by chemical mechanical polishing and subjected to a cleaning step. Finally, a clean etch process is applied to form a clean structure.

FIG. 23 shows the next step in the process, where a patterned conductive layer 250 is formed and contacts the plugs on the fill layer, providing the bit lines and other conductors required for the memory elements, resulting in the structure shown in FIG. 5 . In an embodiment of this process, a copper alloy damascene metallization process is used, in which fluorosilicate glass (FSG) is deposited on the exposed surface to form a patterned conductive layer, followed by a predetermined photoresist pattern. Etching is then performed to remove the exposed fluorosilicate glass, followed by deposition of the substrate and seed layer in this pattern. Copper electroplating is then performed to fill this pattern. After electroplating, an annealing step is performed followed by a grinding process. Other embodiments may use an aluminum-copper process, or other known metallization processes.

The cell described herein includes two bottom electrodes with a dielectric therebetween, and a phase change material bridge over the electrodes and across the dielectric. The bottom electrode and the dielectric are formed in the electrode layer on the front-end process CMOS logic structure or other functional circuit structures, providing a structure that can easily support the built-in storage body and functional circuits on a single chip. This chip can be, for example, a system single chip. element.

24-31 show the embodiment of the phase change memory cell manufactured by the present invention. FIG. 24 shows first and second electrodes 312 , 313 separated by an insulating component 314 . Phase change material 316 is deposited on electrodes 312 , 313 and insulating element 314 . Figure 25 shows the result of depositing a photoresist mask 318 over the phase change material 316, followed by removal of the phase change material 316 not covered by the mask 318, typically using a suitable etching process. This step will generate the phase change element, especially the phase change bridge 311 . The photoresist mask 318 is then trimmed to produce the smaller-sized mask 320 in FIG. 26 . The width of smaller size mask 320 is much smaller than the smallest lithographic feature size used to generate mask 318 . The trimming step is typically performed by a photoresist oxygen plasma trimming process, but other processes may also be used. The smaller-sized mask 320 is placed approximately in the center of the length of the phase-change bridge 311 to expose the bridge 311 for the subsequent implantation process of FIG. 27 .

Implantation step 322 (eg, ion step) may use a single element or a composition of multiple elements to increase the temperature at which phase change material 316 changes (ie, when phase change material 316 changes from a substantially amorphous state to a substantially crystalline state) ) and the change temperature when resetting (ie, when the phase change material 316 changes from a substantially crystalline state to a substantially amorphous state). These elements include carbon, silicon, nitrogen, and aluminum. Removal of the mask 318 results in a phase change memory cell 310 that includes the phase change bridge 311 of FIGS. 28 and 29 . The phase change guide bridge 311 includes a higher temperature change portion 324 on both sides of a lower change temperature portion 326 . In this embodiment, the implant is used to increase the temperature changing portion of the phase change bridge 311 . In one embodiment, when the higher transition temperature portion 324 is substantially amorphous and the lower transition temperature portion 326 is substantially crystalline, the transition temperature of the higher transition temperature portion 324 is typically at least higher than the lower transition temperature. The change temperature of the temperature portion 326 is 100°C. As the current passes through the first and second electrodes 312, 313, before the implanted phase change material portion 324 on both sides of the phase change region 328 can undergo a phase change, the phase change region 328 of the portion 326 above the insulating component 314, Switchable between substantially crystalline and substantially amorphous states. In some embodiments, implants may be used to lower the transition temperature of portion 326 rather than to increase its transition temperature.

FIGS. 30 and 31 illustrate a high angle implant 330 that produces a narrower phase change region 328 compared to the phase change region 328 of FIG. 29 . This result helps to further concentrate the current in the phase change region 328 to reduce the current and energy required to generate the desired substantially crystalline to substantially amorphous phase change.

An advantage of the invention described above in FIGS. 24-31 is that by isolating the phase change region 328 by placing the lower change temperature portion 326 between the higher change temperature portions 324, greater heat generation can be made to the phase change region 328. Insulation effect to reduce reset current and power.

Another aspect of the invention relates to thermal conductivity when both the higher and lower varying temperature portions 324, 326 are substantially crystalline or substantially amorphous. Preferably, the thermal conductivity of the higher varying temperature portion 324 is less (and more preferably at least 50% less than) the thermal conductivity of the lower varying temperature portion 326 when both are substantially amorphous. Similarly, the thermal conductivity of the higher varying temperature portion 324 is less (and preferably at least 50% less) than the thermal conductivity of the lower varying temperature portion 326 when both are substantially crystalline. These factors help to further thermally insulate phase change region 328 of portion 326 . Suitable implant elements include nitrogen, oxygen, and silicon.

Another aspect of the invention concerns the resistivity of the higher and lower varying temperature portions 324,326. Preferably, the resistivity of the higher varying temperature portion 324 is greater (more preferably at least 50% greater) than the resistivity of the lower varying temperature portion 326 when both are substantially amorphous. Similarly, the resistivity of the higher varying temperature portion 324 is greater (and preferably at least 50% greater) than the resistivity of the lower varying temperature portion 326 when both are substantially crystalline. In addition, the resistance value of the higher changing temperature portion 324 is greater (more preferably at least 50% greater than) the resistance value of the lower changing temperature portion 326 when both are substantially amorphous. Similarly, the resistance value of the higher varying temperature portion 324 is greater (more preferably at least 50% greater) than the resistance value of the lower varying temperature portion 326 when both are substantially crystalline. These aspects help to concentrate the current in the phase change region 328 of the lower transition temperature portion 326 to facilitate reducing transition temperature and energy, especially during reset.

Preferably, the higher changing temperature portion 324 is substantially amorphous and remains in the substantially amorphous state because the thermal and electrical conductivity of the material in the substantially amorphous state is typically less than that in the substantially crystalline state. conductivity.

Figures 32-41 depict an alternative embodiment to the embodiment of Figures 24-31 in which the phase change element is located between the electrode surfaces. The phase change element of this embodiment has a generally tubular exterior surrounding an interior or core. The transition temperature on the outside is typically higher than the inside. The exterior helps to thermally insulate the interior to facilitate phase change between the substantially amorphous and substantially crystalline states.

FIG. 32 is a simplified cross-sectional view of a phase-change memory element 410 manufactured by the present invention. The device 410 includes a memory cell access layer 412 formed on a substrate (not shown), and a memory cell layer 414 formed on the access layer 412 . Access layer 412 typically includes access transistors; other types of access devices may also be used. The access layer 412 includes first and second polysilicon word lines, which serve as second gates 416, 418, first and second plugs 420, 422, and a common source line 424, all of which are located in the dielectric within the film layer 426 .

The phase change element 410 and its fabrication method will be described in detail with reference to FIGS. 33-41 , and then with reference to FIG. 32 . Referring to FIG. 33 , the memory cell access layer 412 has a substantially flat upper surface 428 . The upper surface 428 is defined in part by the first electrode surface 430 at one end of the plugs 420,422. Next, a layer 432 of phase change material, typically GST, is deposited over the upper surface 428 . The thickness of this layer 432 is typically about 10 nm, preferably between 3 nm and 20 nm. FIG. 35 shows the result of depositing a lithographic mask 434 over layer 432 and aligned to the electrode surfaces 430 of the plugs 420 , 422 . Plugs 420, 422 and associated mask 434 have a generally cylindrical cross-sectional shape; however, other cross-sectional shapes, whether regular or irregular polygonal, and shapes with curved and/or straight segments, may also be used for other Examples.

In FIG. 36, portions of layer 432 not protected by mask 434 are removed, leaving a generally cylindrical phase change element 436 in this embodiment. FIG. 37 shows the result of the generation of a trimmed lithographic mask 438 of generally cylindrical shape (this embodiment) on a phase change element 436 . The width or diameter of trimmed mask 438 is much smaller than the minimum lithographic feature size of the process used to create mask 434 . Trimming is typically done with a photoresist oxygen plasma trim process, but other processes can be used. Thereafter, the structure of FIG. 37 is implanted 440 with appropriate elements or materials, such as discussed with respect to FIG. 27 . This implantation will result in a phase change element 436 having a generally tubular outer portion 442 surrounding an inner portion or core 444 . The implantation step causes the reset change temperature of the exterior 442 to be higher than the interior 444 . The reset change temperature of the outer portion 442 is preferably at least 100° C. greater than the reset change temperature of the inner portion 444 .

Trimmed lithographic mask 438 is removed, followed by deposition of an oxide such as silicon dioxide to produce oxide layer 446 as shown in FIG. 39 . Chemical mechanical polishing is then performed on the structure of FIG. 39 to produce the structure of FIG. 40 to produce surface 448 including outer end 450 of phase change element 436 . Afterwards, a metal bit line 452 is formed on the surface 448 , and the bit line 452 serves as a second electrode and contacts the outer end 450 of the phase change element 436 through the electrode surface 454 .

FIG. 41 is a simplified diagram showing a generally cylindrical phase change element 436 including a generally tubular outer portion 442 and inner portion 444 . The cross-section of the generally tubular outer portion 442 of the phase change element 436 may be a generally cylindrical cross-section, as shown; however, other cross-sectional shapes for the generally tubular outer portion 442 are possible, including regular or irregular polygons, and shapes having curved lines and /or the shape of a line segment.

The outer portion 442 acts as a thermal insulator for the inner portion 444 to help the inner portion 444 change. The inner portion 444 changes from a substantially crystalline state to a substantially amorphous state by passing an electric current, and its transition temperature is lower than that of the outer portion 442 . The interior 444 has a central region 456 disposed along the interior of the interior 444 . The central region 456 may first change from a substantially crystalline state to a substantially amorphous state before the inner portion 444 undergoes a phase change, as the ends of the inner portion are cooled by the heat dissipation effect formed by the adjacent electrode surfaces 430 , 454 . Thus, the central region may be the only portion of the interior 444 that can effectively change from a substantially crystalline state to a substantially amorphous state in use, and thus acts as a phase change region for the interior 444 . However, in other embodiments, all or most of the interior 444 may transition from a substantially crystalline state to a substantially amorphous state such that all or all of the interior 444 may serve as a phase change region.

Electrode 452 is preferably composed of titanium nitride. Although other materials such as tantalum nitride, aluminum titanium nitride, or aluminum tantalum nitride can also be used for the electrode 452, because titanium nitride can form good contact with the phase change material GST, it is widely used in semiconductor manufacturing, and Titanium nitride is the preferred material because it provides a good diffusion barrier at the high temperature at which the phase change material changes (typically between 600 and 700°C). Plugs 420, 422 and common source line 424 are typically formed of tungsten.

Words used in the description of the present invention, such as above, below, top, bottom, etc., are only used to make readers understand the present invention better, but not to limit the present invention.

While the present invention has been described with reference to preferred embodiments, it should be understood that the invention is not limited to the details described therein. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. In particular, according to the structure and method of the present invention, all combinations of components that are substantially the same as those of the present invention to achieve substantially the same results as the present invention do not depart from the scope of the present invention. Accordingly, all such alternatives and modifications are intended to come within the scope of the invention as defined in the appended claims and their equivalents.

Any patent applications and publications mentioned above are incorporated by reference in this application.

Claims (24)

1. phase change memory cell, this memory cell is the part of phase-change memory, this phase change memory cell comprises:

First and second electrode;

Phase change element, first and second electrode of itself and this is electrically connected;

At least one part of this phase change element comprises higher replacement inversion temperature part and low replacement inversion temperature part, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, should low replacement inversion temperature part be electrically connected with this first and second electrode; And

This low replacement inversion temperature partly comprises phase change region, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement transformation temperature part.

2. phase change memory cell as claimed in claim 1, wherein the replacement inversion temperature of this higher replacement inversion temperature part is higher than at least 100 ℃ of this low replacement inversion temperature replacement inversion temperatures partly.

3. phase change memory cell as claimed in claim 1, wherein:

The surface of this first and second electrode is separated by a gap; And

This phase change element places between this first and second electrode.

4. phase change memory cell as claimed in claim 1, wherein this phase change element is included as the outside of tubulose and by the inside that this outside surrounded, this outside comprises that higher replacement inversion temperature part and this inside comprise low replacement inversion temperature part.

5. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the thermal conductivity of this higher replacement inversion temperature part was less than the thermal conductivity of this low replacement inversion temperature part.

6. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the thermal conductivity of this higher replacement inversion temperature part thermal conductivity than this low replacement inversion temperature part at least was little by 50%.

7. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistivity of this higher replacement inversion temperature part was greater than the resistivity of this low replacement inversion temperature part.

8. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistivity of this higher replacement inversion temperature part resistivity than this low replacement inversion temperature part at least was big by 50%.

9. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistance value of this higher replacement inversion temperature part was greater than the resistance value of this low replacement inversion temperature part.

10. phase change memory cell as claimed in claim 1, wherein when this higher replacement inversion temperature part partly was crystalline state with this low replacement inversion temperature, the resistance value of this higher replacement inversion temperature part resistance value than this low replacement inversion temperature part at least was big by 50%.

11. phase change memory cell as claimed in claim 1, wherein this phase change element comprises first and second higher replacement inversion temperature part, and above-mentioned two parts are positioned at the not homonymy of this low replacement inversion temperature part.

12. phase change memory cell as claimed in claim 1, but wherein in this higher replacement inversion temperature part cloth be implanted with cloth and plant element, but should cloth plant element be not present in should low replacement inversion temperature partly in.

13. phase change memory cell as claimed in claim 12 comprises in following at least a but wherein should cloth plant element: carbon, silicon, oxygen, nitrogen and aluminium.

14. phase change memory cell as claimed in claim 1, wherein this phase change element comprises the composition that is selected from following group of material more than two kinds: germanium, antimony, tellurium, selenium, indium, titanium, gallium, bismuth, tin, copper, palladium, lead, silver, sulphur and gold.

15. phase change memory cell as claimed in claim 1, wherein this first and second electrode comprises element and the alloy thereof that is selected from following group: titanium, tungsten, molybdenum, aluminium, tantalum, copper, platinum, iridium, lanthanum, nickel and ruthenium.

16. a phase change memory cell, this memory cell are the some of phase-change memory, this phase change memory cell comprises:

First and second electrode, the surface of this two electrode is separated by a gap;

Phase change element and is electrically connected with this first and second electrode between this first and second electrode;

This phase change element is included as the outside of tubulose and by inside that this outside surrounded, this outside comprises that higher replacement inversion temperature part and this inside comprise low replacement inversion temperature part, and the replacement inversion temperature of this higher replacement inversion temperature part is higher than the replacement inversion temperature of this low replacement inversion temperature part more than 100 ℃ at least; And

This low replacement inversion temperature partly comprises phase change region, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement inversion temperature part.

17. the method in order to the manufacturing phase change memory cell, this memory cell is the part of phase-change memory, and this method comprises:

Be electrically connected first and second electrode and phase change element, this phase change element comprises phase-transition material; And

This electrical connection step provides higher replacement inversion temperature part and low replacement inversion temperature part, this low replacement inversion temperature partly places between this higher replacement inversion temperature part, this low replacement inversion temperature part is electrically connected with this first and second electrode, this low replacement inversion temperature partly generates phase change region, its can by by electric current between this two electrode and between crystalline state and amorphous state, change, this phase change region by by electric current to be converted to amorphous inversion temperature from crystalline state, be lower than the inversion temperature of this higher replacement transformation temperature part.

18. method as claimed in claim 17, wherein this electrical connection step comprises and forms this phase change element between this first and second electrode and be in contact with it.

19. method as claimed in claim 17, wherein this replacement inversion temperature higher and phase-transition material that partly provides step to comprise the tubular outer that changes this phase change element than low replacement inversion temperature.

20. method as claimed in claim 17, wherein this higher and low replacement inversion temperature replacement inversion temperature of partly providing step to comprise this tubular outer that increases this phase change element.

21. method as claimed in claim 17, this higher and low replacement inversion temperature replacement inversion temperature of partly providing step to comprise at least one part phase-transition material that changes this phase change element wherein is to generate higher replacement inversion temperature part and this hangs down replacement inversion temperature part.

22. method as claimed in claim 21, wherein this higher and low replacement inversion temperature partly provides in the some that step is included in this phase change element cloth to plant material, to change the replacement inversion temperature of this part.

23. method as claimed in claim 21, wherein this higher and low replacement inversion temperature partly provides in the some that step is included in this phase change element cloth to plant material, to increase the replacement inversion temperature of this part.

24. the method in order to the manufacturing phase change memory cell, this memory cell is the part of phase-change memory, and this method comprises:

Be electrically connected first and second electrode and phase change element, this phase change element is between this first and second electrode and be in contact with it, and this phase change element comprises phase-transition material;

Change the replacement inversion temperature of phase-transition material of the tubular outer of this phase change element, generating higher replacement inversion temperature with the tubular outer at this phase change element partly reaches in the tubular inner of this phase change element and generates low replacement inversion temperature part, this low replacement inversion temperature partly comprises phase change region, its can by by electric current between this two electrode and between crystalline state and amorphous state, change; And

This replacement inversion temperature changes step and comprises with a material and being implanted in the outside of this phase change element, to increase the replacement inversion temperature of this outside, generates this higher replacement inversion temperature part.

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