CN100578672C

CN100578672C - Shift Register

Info

Publication number: CN100578672C
Application number: CN200610110934A
Authority: CN
Inventors: 蔡政宏; 黄俊尧; 廖亿丰
Original assignee: Chunghwa Picture Tubes Ltd
Current assignee: Chunghwa Picture Tubes Ltd
Priority date: 2006-08-03
Filing date: 2006-08-03
Publication date: 2010-01-06
Anticipated expiration: 2026-08-03
Also published as: CN101118787A

Abstract

The invention discloses a shift register, which comprises a plurality of stage circuits, wherein each stage circuit comprises a shift circuit used for receiving an input signal and providing an output signal. The output signal is derived from the input signal by logic operation and delay. In addition to the first one of the above-mentioned stage circuits, each stage circuit further includes a logic circuit for generating at least one control signal according to the internal signal of the stage circuit to replace at least one of the clock pulse signals required for the operation of the corresponding shift circuit.

Description

Shift register

Technical field

The present invention is about a kind of shift register (shift register), and especially in regard to a kind of internal signal carried out logical operation to replace the shift register of clock pulse signal.

Background technology

Shift register now is widely used, for example be applied in the source electrode driver (source driver) and the gate drivers (gate driver) of film display panels (thinfilm transistor liquid crystal display panel abbreviates TFT LCD panel as).Shift register is to be composed in series by a plurality of classes circuit, and Fig. 1 is the circuit diagram of one of them class's circuit of traditional shift register.

Class's circuit of Fig. 1 comprises phase inverter (inverter) I1 ~ I4, three-phase inverter T1 ~ T4 and Sheffer stroke gate (NAND gate) NG.Class's circuit of Fig. 1 (stage circuits) receives the input signal IN from last class's circuit, and output signal OUT is provided when output enable signal OE enables.Phase inverter I3 receive clock pulse signal CK exports anti-phase clock pulse signal CKB.Clock pulse signal CK and CKB control three-phase inverter T1 ~ T4.Three-phase inverter T3 then provides the input signal of next class circuit.

Fig. 2 is the signal timing diagram with five class's circuit serial operations as shown in Figure 1, wherein IN is the input signal of first class's circuit, CK is a clock pulse signal, and OE is the output enable signal, and O1 to O5 is respectively the output signal of first to the 5th class's circuit.As shown in Figure 2, output signal O1 ~ O5 can be used as the wherein thin film transistor switch signal of five sweep traces of TFT LCD panel.

Each three-phase inverter of Fig. 1 all has same structure, is example with T1, and Fig. 3 is the circuit diagram of three-phase inverter T1.Three-phase inverter T1 comprises P-type mos field effect transistor (p-channelmetal oxide semiconductor field effect transistor, abbreviate the PMOS field effect transistor as) P1, P2 and N type metal oxide semiconductor field effect transistor (n-channel metal oxidesemiconductor field effect transistor abbreviates the NMOS field effect transistor as) N1, N2.Three-phase inverter T1 has four end points, is respectively input end SI, output terminal SO, the first control end SC1 and the second control end SC2.As shown in Figure 3, PMOS field effect transistor P1 is electrically connected at input end SI and voltage source V DD.PMOS field effect transistor P2 is electrically connected at control end SC1, PMOS field effect transistor P1 and output terminal SO.NMOS field effect transistor N1 is electrically connected at input end SI and earth terminal GND.At last, NMOS field effect transistor N2 is electrically connected at control end SC2, NMOS field effect transistor N1 and output terminal SO.Circuit by three-phase inverter T1 can be derived output state as shown in table 1.

Table 1, the output state of three-phase inverter

The shortcoming of above-mentioned traditional shift register is that three-phase inverter can be because the coupling of external clock pulse signal causes the instability of state, and then cause unnecessary power consumption, and because the operating frequency of the concussion frequency ratio shift register of external clock pulse is high, for example if above-mentioned shift register is applied in the gate drivers of the TFT LCD panel of 320x240 resolution, then the cycle of clock pulse signal CK and CKB is about 50us, and the operating cycle of shift register is about 16.6ms, differ 333 times, unnecessary high frequency oscillation also can cause unnecessary power consumption.Above power consumption reason if can be eliminated, the power consumption of entire circuit can be reduced.

Summary of the invention

The objective of the invention is is providing a kind of shift register of low power consumption.

For reaching above-mentioned and other purpose, the present invention proposes a kind of shift register, comprises a plurality of classes circuit, and each above-mentioned class circuit all comprises shift circuit, in order to receiving inputted signal and output signal is provided.This output signal is that input signal comes through logical operation and delay.In the middle of above-mentioned class circuit first, each class's circuit also comprises logical circuit, produce at least one control signal in order to internal signal, to replace at least one in the middle of the required clock pulse signal of corresponding shift circuit operation according to affiliated class circuit.

Above-mentioned shift register, in one embodiment, shift circuit comprises two phase inverters and four three-phase inverter.Wherein first three-phase inverter has input end, first control end, second control end, reaches output terminal, with the input end receiving inputted signal, receives first clock pulse signal with first control end, receives the second clock pulse signal with second control end.First phase inverter has input end and output terminal, electrically connects the output terminal of first three-phase inverter with input end.Second three-phase inverter has input end, first control end, second control end, reaches output terminal, electrically connect the output terminal of first phase inverter with input end, receive first control signal with first control end, receive second control signal with second control end, electrically connect the input end of first phase inverter with output terminal.The 3rd three-phase inverter has input end, first control end, second control end, reaches output terminal, electrically connect the output terminal of second three-phase inverter with input end, receive the second clock pulse signal with first control end, receive first clock pulse signal with second control end.Second phase inverter has input end and output terminal, electrically connects the output terminal of the 3rd three-phase inverter with input end, and above-mentioned output signal is produced by the output according to second phase inverter.The 4th three-phase inverter has input end, first control end, second control end, reaches output terminal, electrically connect the output terminal of second phase inverter with input end, receive first control signal with first control end, receive second control signal with second control end, electrically connect the input end of second phase inverter with output terminal.

Above-mentioned shift register, in one embodiment, logical circuit comprises biconditional gate (XNOR gate) and the 3rd phase inverter.Biconditional gate has first input end, second input end, and output terminal, and the output terminal of second phase inverter of class's circuit under electrically connecting with first input end electrically connects the output terminal of first phase inverter with second input end, exports first control signal.The 3rd phase inverter receives first control signal and exports second control signal.

Above-mentioned shift register also comprises a Sheffer stroke gate in one embodiment.This Sheffer stroke gate has first input end, second input end, reaches output terminal, receives the output enable signal with first input end, electrically connects the output terminal of second phase inverter with second input end.Above-mentioned output signal produces for the output according to this Sheffer stroke gate.

Above-mentioned shift register also comprises the 5th phase inverter in one embodiment.This 5th phase inverter has input end and output terminal, with the output terminal of input end electric connection Sheffer stroke gate, exports above-mentioned output signal.

Described according to preferred embodiment of the present invention, the present invention uses the internal signal of class's circuit to produce control signal, in order to replace the required part clock pulse signal of same class circuit operation.Therefore can avoid the instability that coupling caused of external clock pulse signal, also can avoid unnecessary high-frequency clock pulse concussion, and then reduce the power consumption of shift register.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. is described in detail below.

Description of drawings

Fig. 1 is the circuit diagram of class's circuit of existing shift register.

Fig. 2 is the signal timing diagram of existing shift register.

Fig. 3 is the circuit diagram of three-phase inverter.

Fig. 4 is the circuit diagram that is pursuant to the shift register of one embodiment of the invention.

Fig. 5 is the biconditional gate synoptic diagram of Fig. 4.

Fig. 6 and Fig. 7 are the signal timing diagram of the shift register of Fig. 4.

Embodiment

Fig. 4 is the circuit diagram that is pursuant to the shift register of preferred embodiment of the present invention.The shift register of Fig. 4 comprises three class's circuit 410,420,430.Wherein first class's circuit 410 includes only shift circuit 411, all the other each class's circuit all comprise a shift circuit and a logical circuit, that is to say, class's circuit 420 comprises shift circuit 421 and logical circuit 422, and class's circuit 430 comprises shift circuit 431 and logical circuit 432.

Shift circuit 411,421,431 is receiving inputted signal IN1～3 and output signal OUT1～3, each output signal are provided separately all is that corresponding input signal is through logical operation and delay separately.First input signal IN1 is that the system by the outside provides, and all the other each input signals all are to provide the circuit to next class by last class's circuit.As for the effect of logical circuit 422 is that internal signal according to affiliated class circuit 420 produces at least one control signal, replaces in the middle of the required clock pulse signal of corresponding shift circuit 421 operations at least one with above-mentioned control signal then.In like manner, the effect of logical circuit 432 is that the internal signal according to affiliated class circuit 430 produces at least one control signal, replaces in the middle of the required clock pulse signal of corresponding shift circuit 431 operations at least one with above-mentioned control signal then.

Though the shift register of present embodiment only comprises three class's circuit, in other embodiments of the invention, shift register can comprise class's circuit of any amount.

The circuit of shift circuit 411 and Fig. 1 is identical, does not give unnecessary details at this.Shift circuit 421 is identical with 431 structure, is example with shift circuit 421, and shift circuit 421 comprises phase inverter I21, I22, I24, I25, three-phase inverter T21 ~ T24 and Sheffer stroke gate NG2.Each three-phase inverter of present embodiment all has input end, first control end, second control end, reaches output terminal, and each phase inverter all has input end and output terminal.Wherein three-phase inverter T21 is with input end receiving inputted signal IN2, with the first control end receive clock pulse signal CK, with the second control end receive clock pulse signal CKB.Input signal IN2 is from the output terminal of the three-phase inverter T13 of last class's circuit 410.Phase inverter I21 electrically connects the output terminal of three-phase inverter T21 with input end.Three-phase inverter T22 receives control signal C21 with the output terminal of input end electric connection phase inverter I21 with first control end, receives control signal C22 with second control end, electrically connects the input end of phase inverter I21 with output terminal.

Three-phase inverter T23 is with the output terminal of input end electric connection three-phase inverter T22, with the first control end receive clock pulse signal CKB, with the second control end receive clock pulse signal CK.Phase inverter I22 electrically connects the output terminal of three-phase inverter T23 with input end.Three-phase inverter T24 receives control signal C21 with the output terminal of input end electric connection phase inverter I22 with first control end, receives control signal C22 with second control end, electrically connects the input end of phase inverter I22 with output terminal.Sheffer stroke gate NG2 has first input end, second input end, reaches output terminal, receives output enable signal OE with first input end, electrically connects the output terminal of phase inverter I22 with second input end.Phase inverter I25 provides output signal OUT2 with the output terminal of input end electric connection Sheffer stroke gate NG2.

Above-mentioned clock pulse signal CKB produces through phase inverter I24 for clock pulse signal CK, so clock pulse signal CKB is the inversion signal of clock pulse signal CK.

The structure of each logical circuit is all identical in the middle of Fig. 4, is example with logical circuit 422, and logical circuit 422 comprises biconditional gate XG2 and phase inverter I23.

The biconditional gate of present embodiment all has same structure, and the biconditional gate XG2 that illustrates with Fig. 5 is an example, and XG2 has four input end A1, AB1, B1, BB1 and an output terminal Y1.Wherein the signal of input end A1 and AB1 reception is anti-phase each other, and on the other hand, the signal that input end B1 and BB1 receive is also anti-phase each other.So can determine the logic state of output terminal Y1 by the logic state of input end A1, B1.Table 2 is the truth table of biconditional gate XG2.The truth table of biconditional gate XG3 is identical with XG2, just changes input end into A2, AB2, B2, BB2 respectively, changes output terminal into Y2.

Table 2, the truth table of biconditional gate XG2

The biconditional gate XG2 of Fig. 4 electrically connects the output terminal of phase inverter I22 with input end A1, electrically connect the output terminal of three-phase inverter T23 with input end AB1, electrically connect the output terminal of phase inverter I21 with input end B1, electrically connect the output terminal of three-phase inverter T21 with input end BB1, and export control signal C21.As shown in Figure 4, the signal of four input ends of biconditional gate XG2 is all from the class's circuit 420 under the XG2.In other embodiments of the invention, can use have only A, the biconditional gate of two input ends of B, can produce voluntarily according to the signal at A, B two ends as for the signal of AB, two input ends of BB.

Logical circuit 422 also comprises phase inverter I23, in order to receive control signal C21 and to export control signal C22.Class's circuit 420 is exactly to replace clock pulse signal CK and the CKB that three-phase inverter T22 and T24 receive originally with control signal C21 and C22.

Fig. 6 be the shift register of Fig. 4 through the signal timing diagram that simulation produces, comprise signal, control signal C21, C22 and clock pulse signal CK, CKB that input end AB1, the B1 of biconditional gate XG2 are received.As shown in Figure 6, control signal C21, C22 are not each cycle that substitutes clock pulse signal CK, CKB, but only substitute the part of shift circuit 421 actual needs, so reduce the concussion frequency of signal, just can reduce power consumption.

Fig. 7 is the shift register of Fig. 4 another signal timing diagram through the simulation generation, and input signal IN1, clock pulse signal CK, output enable signal OE that first class's circuit 410 receives and output signal OUT1 ~ 3 that provided respectively by class's circuit 410,420,430 are provided.As shown in Figure 7, the shift register of Fig. 4 can provide output signal OUT1 ~ 3 identical with traditional shift register really.

Present embodiment uses logical circuit to produce control signal according to the internal signal of class's circuit, to replace the required part clock pulse signal of same class circuit operation, can avoid the instability that coupling caused of external clock pulse signal, also can avoid unnecessary high-frequency clock pulse concussion, and then reduce power consumption.Following table 3 is the power consumption analog result of traditional shift register and present embodiment, and is as shown in table 3, and present embodiment can significantly reduce circuit operation frequency, current sinking and the power consumption of shift register.The application of any shift register, for example source electrode driver of TFT LCD panel and gate drivers etc., all improvement that can use the present invention to propose.

Table 3, shift register power consumption are relatively

	Prior art	Present embodiment
	Prior art	Present embodiment	The circuit operation frequency	20kHz	60Hz
Current sinking	171uA	56uA	The circuit operation frequency	20kHz	60Hz
Current sinking	171uA	56uA	Power consumption	100％	50％

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims

1. A shift register comprising a plurality of stage circuits, each of which includes:

A shift circuit receives an input signal and provides an output signal. The output signal is derived from the input signal through logical operation and delay, and the shift circuit includes:

A first three-phase inverter has an input terminal, a first control terminal, a second control terminal, and an output terminal, the input terminal receives the input signal, and the first control terminal receives a first clock a pulse signal, the second control terminal receives a second clock pulse signal;

a first inverter having an input end and an output end, the input end is electrically connected to the output end of the first three-phase inverter;

A second three-phase inverter has an input end, a first control end, a second control end, and an output end, the input end is electrically connected to the output end of the first inverter, and the The first control terminal receives a first control signal, the second control terminal receives a second control signal, and the output terminal is electrically connected to the input terminal of the first inverter;

A third three-phase phaser having an input end, a first control end, a second control end, and an output end, the input end is electrically connected to the output end of the second three-phase phaser, to The first control terminal receives the second clock pulse signal, and the second control terminal receives the first clock pulse signal;

A second inverter has an input end and an output end, the input end is electrically connected to the output end of the third three-phase inverter, and the output signal is generated according to the output of the second inverter ;as well as

A fourth three-phase inverter has an input end, a first control end, a second control end, and an output end, the input end is electrically connected to the output end of the second inverter, and the the first control terminal receives the first control signal, the second control terminal receives the second control signal, and the output terminal is electrically connected to the input terminal of the second inverter; and

In addition to the first of the class circuits, each of the class circuits includes:

A logic circuit, which generates at least one control signal according to the internal signal of the class circuit, and replaces at least one of the corresponding clock pulse signals required for the operation of the shift circuit with the control signal, and the logic circuit includes:

An XNOR gate has a first input terminal, a second input terminal, and an output terminal, the first input terminal is electrically connected to the output terminal of the second inverter of the stage circuit, and the second the input terminal is electrically connected to the output terminal of the first inverter, and outputs the first control signal; and

A third inverter receives the first control signal and outputs the second control signal.

2. The shift register as claimed in claim 1, wherein the input signal comes from the upper stage circuit.

3. The shift register according to claim 2, wherein the input signal comes from the output terminal of the third three-phase inverter of the upper stage circuit.

4. The shift register as claimed in claim 1, wherein the second clock signal is an inversion signal of the first clock signal.

5. The shift register as claimed in claim 4, wherein the second clock signal is generated by passing the first clock signal through a fourth inverter.

6. The shift register as claimed in claim 1, wherein each of the three-phase inverters is turned off when its first control terminal is in a first state and its second control terminal is in a second state, When the first control terminal is in the second state and the second control terminal is in the first state, the inverted state of the input terminal is output.

7. The shift register as claimed in claim 6, wherein the first state is logic 1, and the second state is logic 0.

8. The shift register as claimed in claim 7, wherein each of the three-phase inverters comprises:

a first PMOS field effect transistor, electrically connected to the input terminal and a voltage source;

a second PMOS field effect transistor, electrically connected to the first control terminal, the first PMOS field effect transistor, and the output end of the three-phase inverter;

a first NMOS field effect transistor, electrically connected between the input end and a ground end; and

A second NMOS field effect transistor is electrically connected to the second control terminal, the first NMOS field effect transistor and the output terminal.

9. The shift register as claimed in claim 6, wherein the first state is logic 0, and the second state is logic 1.

10. The shift register according to claim 1, wherein the XNOR gate further comprises a third input terminal and a fourth input terminal, the third input terminal is electrically connected to the first stage circuit The output end of the three-phase inverter, the fourth input end is electrically connected to the output end of the first three-phase inverter.

11. The shift register as claimed in claim 1, further comprising:

A NAND gate has a first input terminal, a second input terminal, and an output terminal, the first input terminal receives an output enable signal, and the second input terminal is electrically connected to the second inverting phase The output terminal of the device, the output signal is generated according to the output of the NAND gate.

12. The shift register according to claim 11, further comprising:

A fifth inverter has an input end and an output end, and the input end is electrically connected to the output end of the NAND gate to output the output signal.