CN100573249C - Display device - Google Patents

Abstract

The display device has: a plurality of first scanning lines arranged in one direction on the substrate for analog display; a plurality of second scanning lines arranged in one direction on the substrate for digital display; a plurality of data signal lines, and the aforementioned Crossing in one direction; a plurality of display pixels are selected by a predetermined scan line selection signal, image signals are provided by the aforementioned data signal lines, and are arranged in a matrix on the aforementioned substrate; the first display circuit is connected via the first switch circuit connected to the aforementioned first scan line, and configured in the aforementioned display pixel, for performing the aforementioned analog display; the second display circuit, connected to the aforementioned second scan line through a second switch circuit, configured in the aforementioned display pixel, and having The holding circuit for holding the image signal provides the corresponding voltage to the pixel electrode for the digital display; the mode switching circuit performs mode switching between the analog display mode and the digital display mode according to the mode switching signal.

Description

display device

technical field

The present invention relates to a display device, in particular to a display device in which a scan line is selected by a predetermined scan line selection signal, and a plurality of display pixels supplied with image signals from data signal lines are arranged in a matrix on a substrate. Active matrix type display device.

Background technique

Embodiments of the present invention claim priority from Japanese Patent Document No. 2006-278144 filed on October 11, 2006, and Japanese Patent Document No. 2006-278149 filed on October 11, 2006, and Features of these patent documents are used in combination.

For example, in a widely used active matrix display device, such as a liquid crystal display module, a plurality of scanning lines and a plurality of data signal lines crossing the scanning lines are arranged on a glass substrate, etc. Switching circuits and display pixels are arranged at intersections of the wires and the respective data signal wires. In an active matrix display device, when a target image is not being displayed, a dummy still image or the like is displayed to reduce power consumption.

For example, in Japanese Patent Application Laid-Open No. 2001-264814, it has been disclosed that a multi-color (multi-color) display can be performed with low power consumption during standby, and a full-color (full-color) half-tone display can be performed when called. or animated display. Here, the following structure is described: the first switch component is connected to the scan line, the source is connected to the data signal line, the drain is connected to the pixel electrode, and the pixel electrode is connected to the digital memory through the second switch component, The second switch component is composed of two switch components connected in parallel, and the drain is respectively connected to the output terminal and the inverting output terminal of the digital memory, the source is connected to the pixel electrode, and the gate is connected to two control signal lines .

Also, Japanese Patent Application Laid-Open No. 2002-91366 discloses a configuration in which two types of displays, full-color moving image display and low-power-consumption still image display, are supported in one display device. Here, a circuit selection circuit composed of two TFTs having different polarities and another TFT paired with the circuit selection circuit are provided near the intersections of the gate signal line and the drain signal line of the display pixel. Circuit selection circuit. In addition, an image selection circuit composed of two other TFTs with different polarities is provided. The image selection circuit is adjacent to the circuit selection circuit and connected in series with the two TFTs. The electrodes are connected to the gate signal line, and the two TFTs are turned on (ON) at the same time according to the scan signal. Next, when the two circuit selection circuits select full-color dynamic image display, the first display circuit is formed by one of the two TFTs of the circuit selection circuit and the holding capacitor. On the other hand, it is configured that a holding circuit composed of a static memory is connected between the other of the two TFTs of the circuit selection circuit and the pixel electrode of the liquid crystal, and the signal selection circuit operates according to a signal from the holding circuit. The AC drive signal (signal A) or the counter electrode signal (signal B) is selected and supplied to the pixel electrodes of the liquid crystal 21 . Therefore, when the two circuit selection circuits select still image display, the second display circuit is constituted by the other of the two TFTs of the circuit selection circuit, the hold circuit, and the signal selection circuit.

According to the prior art described above, when analog full-color display such as half tone (half tone) display is not performed, since digital memory or static memory holds binary digital still image data for still image display, it is possible to reduce the Power consumption of image display during standby.

However, according to the prior art described above, since the same scanning lines are used for analog display and digital display, the scanning line driving circuits are also the same, so power consumption related to scanning line driving and the like is not reduced. Also, even when digital display is performed in an arbitrary display area, it is inconvenient to perform processing such as writing dummy data to the non-display area.

Contents of the invention

An advantage of the present invention is to provide a display device capable of reducing power consumption among display devices capable of analog display and digital display.

A display device according to an aspect of the present invention includes: a plurality of first scanning lines arranged in one direction on the substrate for analog display; a plurality of second scanning lines arranged in the aforementioned one direction on the substrate. direction for digital display; a plurality of data signal lines arranged in a direction intersecting with the aforementioned one direction; and a plurality of display pixels selected by a predetermined scan line selection signal for the aforementioned first scan line or the aforementioned second scan line are selected and receive image signals from the aforementioned data signal lines, and are arranged in a matrix on the aforementioned substrate. Furthermore, a first display circuit is provided, which is connected to the first scanning line via a first switch circuit operated according to the scanning line selection signal, and arranged in the display pixel, and sequentially supplies the video signal which is input sequentially. To the pixel electrodes of the aforementioned display pixels for the aforementioned analog display. In addition, a second display circuit is provided, which is connected to the second scanning line via a second switch circuit operated according to the scanning line selection signal, is arranged in the display pixel, and has a hold for holding the image signal. The circuit is used for supplying the voltage corresponding to the signal held by the holding circuit to the pixel electrode to perform the digital display. Furthermore, a mode switching circuit is further provided for switching between an analog display mode operated by the first display circuit and a digital display mode operated by the second display circuit based on a mode switching signal.

In addition, another advantage of the present invention is to provide a display device that can perform digital display in any area among display devices capable of analog display and digital display.

A display device according to another aspect of the present invention is equipped with a first scanning line driving circuit, which is a circuit for outputting a scanning line selection signal related to the first scanning line, and has an output for sequentially specifying each of the aforementioned first scanning lines. A shift register for sequentially specifying pulses for one scan line. In addition, a second scanning line driving circuit is provided, which is a circuit for outputting a scanning line selection signal related to the second scanning line, and has a decoder for selecting each desired second scanning line. circuit department.

Description of drawings

FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

Fig. 2 is a diagram showing the arrangement state of each element on the lower glass substrate according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating the configuration of a display pixel according to an embodiment of the present invention.

FIG. 4 is a diagram showing the configuration of scanning line driving circuits A and B according to the embodiment of the present invention.

FIG. 5A is a diagram showing the configuration of a scanning line driving circuit used in a conventional active matrix liquid crystal display device.

FIG. 5B is a diagram showing the configuration of the scanning line driving circuit according to the embodiment of the present invention.

6A is a diagram for explaining the operation of the scanning line driving circuits A and B when the mode switching second signal is at L potential in the embodiment of the present invention.

6B is a diagram for explaining the operation of the scanning line driving circuits A and B when the mode switching second signal is at H potential in the embodiment of the present invention.

FIG. 7 is a diagram showing the configuration of a data line driving circuit in the embodiment of the present invention.

FIG. 8 is a diagram showing the configuration of scanning line driving circuits A and B according to another embodiment.

FIG. 9 is a diagram showing the configuration of scanning line driving circuits A and B according to another embodiment.

Fig. 10 is a perspective view of a display device according to another embodiment.

Fig. 11 is a diagram showing an arrangement of various elements on a lower glass substrate according to another embodiment.

FIG. 12 is a diagram illustrating the configuration of a display pixel according to another embodiment.

FIG. 13 is a diagram showing the configuration of a scanning line driving circuit according to another embodiment.

FIG. 14 is a diagram showing the configuration of a scanning line driving circuit 1 for each scanning line in another embodiment.

FIG. 15 is a diagram showing the configuration of a scanning line driving circuit 2 according to another embodiment.

FIG. 16 is a diagram showing the configuration of a data line driving circuit according to another embodiment.

Fig. 17 is a diagram showing an arrangement state on a lower glass substrate according to still another embodiment.

FIG. 18 is a diagram illustrating divisions of display areas according to yet another embodiment.

Fig. 19 is a diagram showing the state of wiring on the lower glass substrate in the example of Fig. 18 .

Symbol Description

10. 210 display device

12, 212 upper glass substrate

14, 21, 214 LCD

16, 216 sealing material

18, 218 Light guide components

20, 220 backlight

22, 222 polarizing components

24, 224 flexible circuit substrate

26, 226 External circuit substrate

30, 230, 330, 340 Lower glass substrate

32, 232 control IC

34, 234 data line pre-charging circuit

40, 240 display area

42, 242 display pixels

43, 243 circuit part

44, 46, 48, 244, 246, 248 N-channel transistors

54, 55, 255 pixel electrode wiring

56, 256 hold circuit

50, 58, 59, 114, 250, 258, 259 Transmission barrier

60, 260 common electrode signal line

70, 270 data line drive circuit

72, 272 data signal line

74, 274 video signal line

76, 276 Select the signal line

78, 278 solve multitasker

80, 100 Scanning line drive circuit A, B

82, 282 first scan line

84, 302, 344 second scan lines

86, 286 hours signal

87, 287 enable signal line

88 Distribution circuit department

89, 289 Enable circuit department

90, 290 Shift register circuit department

92, 292 Potential displacement circuit department

94, 294 Output drive circuit department

102 Assignment signal

104 NOR circuit

106, 116 distribution circuit

241 Full-color display area + still image display area

280 Scanning line drive circuit 1

300 Scanning line drive circuit 2

306 NAND circuit

308 snubber circuit

332 Power circuit

342 still image display area

C _S 52, C _S 252 hold capacitor

C _LC 54, C _LC 254 Liquid crystal capacitor

Detailed ways

Embodiments of the present invention will be described in detail below using the drawings. In the following, as an active matrix display device, although it is explained that a COG (Chip On Glass; chip-on-glass package) with an integrated circuit chip (IC chip) mounted on a substrate equipped with a polysilicon TFT (Thin Film Transistor; thin film transistor) is used. ) technology, a liquid crystal display device that can be illuminated by a backlight, but as long as it is an active matrix type display device that can display analog display and digital display in one device, a display mechanism other than a liquid crystal device can also be used. For example, it may be an LED (Light Emission Diode; light emitting diode) array display device, a plasma display device, etc. as the case may be.

In addition, switching components other than polysilicon TFTs may be used, or COG technology may not be used. For example, an amorphous silicon (amorphous silicon) TFT may also be used. The polysilicon TFT can be a high temperature polysilicon TFT or a low temperature polysilicon TFT. Non-linear switching elements such as diode rings may also be used instead of TFTs. In addition, a configuration using a mounting technique other than the COG technique may be used. For example, a configuration may be adopted in which a control IC and the like are disposed on a circuit substrate different from the glass substrate. In addition, a configuration not using a backlight may also be used. For example, it may be a reflective display device that has a reflector and can visually confirm the display with external light.

In addition, the voltage values and the like described below are examples for explanation, and can be appropriately changed according to the application of the display device and the like.

(first embodiment)

FIG. 1 is a perspective view of a display device 10 . The display device 10 includes: a lower glass substrate 30, an upper glass substrate 12, a sealing material 16 for sealing the liquid crystal 14 between the two glass substrates, and a light guide component 18 is disposed on the lower glass substrate. The backlight 20 on the back side of 30, and the polarizer 22 arranged on the surface side of the upper glass substrate 12; the display device 10 is an active matrix liquid crystal display device that can be illuminated by the backlight. A control IC 32 using COG technology is installed on the lower glass substrate 30, and is connected to an external circuit substrate 26 through an appropriate flexible circuit substrate 24 such as FPC (Flexible Print Circuit; flexible printed circuit board).

The upper glass substrate 12 and the lower glass substrate 30 sandwich the liquid crystal 14 together, and apply a predetermined driving voltage on both sides of the liquid crystal 14 to display, and because it is opposite to the lower glass substrate 30, it is also called opposite substrate. A counter electrode (ie, a common electrode) facing the pixel electrode of the lower glass substrate 30 is provided on the upper glass substrate 12 and is applied with a common electrode potential.

The lower glass substrate 30 is a transparent substrate in which a plurality of scanning lines and a plurality of data signal lines are arranged in a grid pattern, and display pixels and polysilicon TFTs as switching components are arranged in each grid area. Here, two types of scanning lines are used as the scanning lines, and one type of scanning line is the same as that of a general active matrix liquid crystal display device. That is, when such a scanning line is used, the image signal from the data signal line is supplied to the pixel electrode of each display pixel selected by the scanning line by switching the function of the component, and according to the correspondence with the upper glass substrate 12 The liquid crystal molecules sealed between the upper glass substrate 12 and the lower glass substrate 30 are driven by a potential difference between the electrodes, thereby enabling display. Another type of scanline is used to display still images.

Thus, although two types of scanning lines are used, as described above, one type of scanning line is the same as that of a general active matrix liquid crystal display device, and is used for halftone display or moving image display. In the case of a color display device, it is used for full-color display. Another type of scan line uses a hold circuit capable of holding a binary value described later to display a still image while suppressing power consumption related to image display. In order to distinguish these two displays, the former can be called an analog display and the latter a digital display. It can also be called dynamic (dynamic) display and static display to replace the difference between analog display and digital display, or in color display, it can also be called full-color display and still image display. Hereinafter, the names of analog display and digital display are used, and when other names are more appropriate, other names are used.

In addition, in order to distinguish the two types of scan lines, one type of scan line used for analog display is called a first scan line, and the other type of scan line used for digital display is called a second scan line. When performing analog display and digital display for each display pixel, two scan lines, the first scan line and the second scan line, and one data signal line are respectively arranged for each display pixel.

FIG. 2 is a diagram showing an arrangement state of various elements on the lower glass substrate 30 . In the central part of the lower glass substrate 30, a display area 40 planarly arranged in a substantially rectangular shape is provided. Around the display area 40, there are scanning line driving circuits A, B (80) for the first scanning line 82 and the second scanning line. The scanning lines 84 are used to select respective scanning lines in sequence; the data line driving circuit 70 is used to input image signals (i.e. video signals) corresponding to each color scale to the data signal lines 72; and the data line pre-charging circuit 34 is used to Before a video signal is input to the data signal line 72, an intermediate potential of the video amplitude is input. Scanning line driving circuits A, B (80), data line driving circuit 70, and data line precharging circuit 34 are respectively connected to the control IC 32.

Scanning line driving circuits A, B (80), data line driving circuit 70, and data line precharging circuit 34 are similar to the TFTs in the display area 40, and are manufactured on the lower glass using TFTs manufactured by polysilicon transistor formation technology. on the substrate 30. That is, the lower glass substrate 30 is a SOG (System On Glass; System on Board) substrate made of active components.

Although the scanning line driving circuits A and B (80) can directly use the scanning line driving circuits used in general active matrix liquid crystal display devices, in order to reduce the power consumption related to scanning line driving, it is preferable to use differently suitable analog circuits. Display and digital display part. The details of the scanning line driving circuits A, B (80) will be described later.

The data line driving circuit 70 can directly use a data line driving circuit used in a general active matrix type liquid crystal display device. Details of the data line drive circuit 70 will be described later.

The control IC 32 has an LSI (Large Scale Integrated circuit; large scale integrated circuit) chip for controlling the functions of the scanning line driving circuit A, B (80), the data line driving circuit 70, the data line precharging circuit 34, etc., and through The COG technology mounts a wiring pattern provided on the lower glass substrate 30 . This wiring pattern extends to the scanning line driving circuits A, B (80), the data line driving circuit 70, the data line precharging circuit 34, etc., and extends to the end of the lower glass substrate 30, here, as shown in FIG. To illustrate, connect to the flexible circuit substrate 24 .

The display area 40 is an area for arranging a plurality of display pixels 42 in a matrix. In the display area 40, a plurality of first scanning lines 82 and a plurality of second scanning lines 84 from the scanning line driving circuits A and B (80) are arranged along one direction of the planar arrangement of the lower glass substrate 30, while The plurality of data signal lines 72 of the data line driving circuit 70 are arranged along a direction intersecting a direction of a planar arrangement of the lower glass substrate 30 (for example, a direction perpendicular to a direction of a planar arrangement of the lower glass substrate 30 ). configuration. In the example of FIG. 2 , the first scanning lines 82 and the second scanning lines 84 are arranged along the horizontal direction of the paper, and the data signal lines 72 are arranged along the vertical direction of the paper. The first scanning line 82 and the second scanning line 84 are configured as a pair, and the display area 40 is divided into a plurality of grid-shaped areas by the pair of scanning lines and data signal lines 72, and each grid-shaped area is respectively Display pixels 42 are provided. Here, in the case of a color display device, sub-pixels (sub-pixels) can be used for each of R, G, and B, but the sub-pixels will be described below as display pixels 42 .

FIG. 3 is a diagram for explaining the configuration of the display pixel 42 . Hereinafter, description will be given using symbols in FIGS. 1 and 2 . Here, one pixel at the upper left in the paper surface of the display area 40 of FIG. 2 is representatively displayed. That is, in order to distinguish a plurality of display pixels 42, the position of the grid-shaped region divided by the first scanning line 82, the second scanning line 84, and the data signal line 72 is set as the upper left on the paper in FIG. When the origin, the right direction is defined as the X direction, the downward direction is defined as the Y direction, and X, Y are used for display, then the display pixel 42 in FIG. Similarly, in order to distinguish a plurality of first scanning lines 82, a plurality of second scanning lines 84, and a plurality of data signal lines 72, the upper left of FIG. When increasing, the first scan line 82 , the second scan line 84 , and the data signal line 72 corresponding to the display pixel 42 in FIG. 3 correspond to the first number respectively. In FIG. 3 , to illustrate the above, the first scan line 82 is marked as GATE-1A, the second scan line 84 is marked as GATE-1B, and the data signal line 72 is marked as DATA-1.

In FIG. 3 , the liquid crystal 14 used for display is marked as a liquid crystal capacitor C _LC ( 54 ). The liquid crystal capacitance C _LC ( 54 ) is the capacitance between the pixel electrode wiring 54 and the common electrode signal line 60 as a counter electrode. Here, the common electrode signal line 60 is marked SC.

First, each signal line and the like in FIG. 3 will be described. VDD (36) and VSS (38) are power supply voltage lines and ground lines of the control IC 32. For example, VDD=+5V, VSS=0V, etc. are set.

As described above, the common electrode signal line 60 is a signal line for transmitting the common electrode signal SC applied to the common electrode provided on the counter electrode of the upper glass substrate 12 . The common electrode signal SC is a signal using a rectangular wave for AC driving of the liquid crystal 14 . For example, a square wave signal varying from 0V to +4V can be used.

Vb ( 64 ) and Vw ( 66 ) are signal lines for AC driving the liquid crystal 14 during digital display. Vw (66) is a signal line for transmitting the potential at which the liquid crystal 14 becomes a white display when this is applied to the pixel electrode wiring 55, and is for transmitting the same signal as the common electrode signal in the common electrode signal line 60. signal line. Vb (64) is a signal line for transmitting the potential at which the liquid crystal 14 becomes a black display when this is applied to the pixel electrode wiring 55, and is a signal line for transmitting the inversion of the common electrode signal in the common electrode signal line 60. signal signal line.

MODE ( 62 ) and XMODE ( 63 ) are signal lines that convey two mode switching signals for switching between the analog display mode and the digital display mode for the display pixel 42 . In order to distinguish the two mode switching signals, the signal in MODE (62) can be called the first mode switching signal, and the signal in XMODE (63) can be called the second mode switching signal. The mode switching first signal among the MODE (62) and the mode switching second signal among the XMODE (63) are mutually opposite signals, when the mode switching first signal among the MODE (62) is H potential, XMODE (63) When the mode switching second signal in the mode is L potential, it can be used as an analog display mode, and when the mode switching first signal in MODE (62) is L potential, and the mode switching second signal in XMODE (63) is H potential , can be used as a digital display mode.

The mode switching first signal in MODE ( 62 ) and the mode switching second signal in XMODE ( 63 ) have opposite polarities as described above, and have different amplitudes and waveforms that are asymmetrical to each other. This point is opposite to turning on (ON)/off (OFF) the N-channel transistor 48 and transmitting the analog video signal to the pixel electrode wiring 55 by the H potential of MODE (62), while the H of XMODE (63) The potential is simply switched between two potential standards in Vb(64) or Vw(66), so it is different. For example, for the switching between the analog display mode and the digital display mode, the mode switching first signal in MODE (62) can be set to H potential=+9V, L potential=0V, and the mode switching second signal in XMODE (63) can be set to The signal was set to L potential=-4V and H potential=+4V.

Next, various elements for constituting the display pixel 42 in FIG. 3 will be described. The N-channel transistor 44 is a component that operates according to the scan line selection signal of the first scan line 82 . In addition, the N-channel transistor 46 is a component that operates according to the scan line selection signal of the second scan line 84 . In order to distinguish these two components, the N-channel transistor 44 may be referred to as a first switch circuit, and the N-channel transistor 46 may be referred to as a second switch circuit.

An N-channel transistor 48 is also connected between the N-channel transistor 44 as the first switch circuit and the pixel electrode wiring 55 . The N-channel transistor 48 is a component that operates according to the mode switching first signal in MODE ( 62 ), and the N-channel transistor 48 can be called a third switch circuit. Then, when both the N-channel transistor 44 as the first switch circuit and the N-channel transistor 48 as the third switch circuit are turned on (that is, the first scanning line 82 is selected by the scanning line selection signal, and the second scanning line is selected by the mode switching When the analog display mode is selected via a signal), the image signal data (ie, video signal data) of the data signal line 72 is transmitted to the pixel electrode wiring 55 and written into the liquid crystal 14 .

Here, as for the display pixel 42, if a circuit for sequentially supplying image signals successively input from the data signal line 72 to the pixel electrode wiring 55 of the display pixel 42 for analog display is taken as the first display circuit, it is narrowly defined as the first display circuit. The liquid crystal capacitor C _LC 54 and the holding capacitor C _S 52 are equivalent to the first display circuit, and broadly speaking, the first display circuit may also include the N-channel transistor 44 and the N-channel transistor 48 .

To the output side of the N-channel transistor 46 which is the second switch circuit, a hold circuit 56 which can hold data statically by connecting two inverter wires in a loop is connected. The holding circuit 56 is a circuit having a function of statically holding the video signal data when the video signal data is written, and is a static memory whose data holding hardly consumes power.

Furthermore, two sets of transmission gates 58, 59 provided between the respective output terminals of the two inverters constituting the holding circuit 56 have Vb (64 ) signal or Vw (66) signal to provide the function of the transmission gate 50. Since the front end of the transfer gate 50 is the pixel electrode wiring 55, the transfer gates 58 and 59 have a potential to be supplied to the pixel electrode wiring 55 to be Vb (64), which is selected based on the data stored in the holding circuit 56. Signal potential, or the function of the pixel electrode potential selection switch set to the signal potential of Vw (66).

Next, the transmission gate 50 is a circuit that operates according to the inverse signal of the mode switching second signal of XMODE (63) and the mode switching first signal of MODE (62), and the transmission gate 50 can also be called a fourth switching circuit. The transfer gate 50 of the fourth switching circuit has a function of supplying a signal of Vb ( 64 ) or a signal of Vw ( 66 ) output as two sets of transfer gates 58 , 59 to the pixel electrode wiring 55 . That is, when XMODE ( 63 ) is at H potential and MODE ( 62 ) is at L potential, a signal of Vb ( 64 ) or a signal of Vw ( 66 ) is supplied to the pixel electrode wiring 55 according to the signal held by the holding circuit 56 . As described above, since the signal of Vw (66) is the same signal as the SC of the common electrode signal line 60, and the signal of Vb (64) is an inverted signal of SC, the signal held by the holding circuit 56 can be The liquid crystal 14 between the pixel electrode wiring 55 and the common electrode signal line 60 is AC-driven. That is, the liquid crystal 14 can display a binary still image corresponding to the signal held by the hold circuit 56 .

Here, the display pixel 42 has a holding circuit 56 for holding an image signal, and a circuit for supplying a voltage corresponding to the signal held by the holding circuit 56 to the pixel electrode wiring 55 for digital display is referred to as a second circuit. When displaying a circuit, in a narrow sense, the holding circuit 56 is equivalent to the second display circuit, and in a broad sense, the second display circuit may also include an N-channel transistor 46, a holding circuit 56, transmission gates 58, 59, and transmission gates. 50. In FIG. 3 , a circuit portion 43 surrounded by a dotted line corresponds to this second display circuit in a broad sense. In addition, in the display pixel 42 , except for the circuit portion 43 surrounded by a dotted line, the other circuit portions correspond to the above-mentioned first display circuit in a broad sense.

In addition, the N-channel transistor 48 operates according to the mode switching first signal in MODE (62), and the transfer gate 50 operates according to the mode switching second signal in XMODE (63). The function of the digital display mode, so these circuit parts can be collectively referred to as the mode switching circuit.

In this way, for each display pixel 42 of the display device 10, the first scanning line 82 and the second scanning line 84 can be selected according to a predetermined scanning line selection signal, and the image signal from the data signal line 72 can be received, and the second scanning line can be switched according to the mode. A signal and a mode switching second signal are used to select the analog display mode or the digital display mode, make the first display circuit or the second display circuit operate, and perform analog display or digital display.

Returning to FIG. 2 again, the scanning line driving circuits A and B (80) will be described. Scanning line drive circuits A, B (80) are circuits that have a function of generating a scanning line selection signal. Specifically, the selection between the first scan line 82 and the second scan line 84 is performed, and a time-by-time sequence for selecting between the multiple first scan lines 82 and the multiple second scan lines 84 is generated. The circuit of the scan line selection signal.

In FIG. 2, the scanning line driving circuits A and B (80) are shown as only one chip, but they may be constituted by a plurality of chips. When configured with a plurality of chips, the plurality of chips may be arranged along any polygon of the display area 40 . For example, the scanning line driver circuits A and B (80) may be two chips, and the display area 40 is sandwiched between one chip and the other chip on the opposite side.

Therefore, for the sake of distinction, the circuit used to generate the signal for selecting a specific scan line in the plurality of first scan lines 82 is called the first scan line driver circuit, and the circuit used to generate a signal for selecting a specific scan line in the plurality of second scan lines 84 is called a first scan line driver circuit. When the circuit for scanning line signals is referred to as a second scanning line driving circuit, the scanning line driving circuits A and B (80) are circuits that combine the configuration and function of the first scanning line driving circuit and the second scanning line driving circuit. Specifically, the first scanning line driving circuit and the second scanning line driving circuit are configured such that common elements are used as common parts and unique elements are respectively provided.

FIG. 4 is a diagram showing the configuration of scanning line driving circuits A and B (80). Scanning line driving circuits A and B (80) generate signals for time-by-time selection of each first scanning line 82 and each second scanning line 84 according to a time-by-time signal 86 composed of a start signal and a frequency signal circuit. Scanning line driving circuits A and B ( 80 ) include: a shift register circuit unit 90 , a distribution circuit unit 88 , a level shift circuit unit 92 , and an output driving circuit unit 94 .

The shift register circuit unit 90 is a circuit having a function of sequentially shifting the clocked signal 86 which is sequentially input on a clock-by-clock basis, and outputting sequential designation pulses for designating display pixels in units of scanning lines. The number of shift register circuit sections 90 is set to be the same as the number arranged along the scanning direction of the plurality of display pixels 42 . In other words, when one first scanning line 82 and one second scanning line 84 are arranged for one display pixel 42, the number of first scanning lines=the number of second scanning lines=the number of shift register circuit parts 90 . That is, since one shift register circuit is used for the first scanning line 82 and the second scanning line 84 , the shift register circuit unit 90 is used in a shared manner. Thereby, the scale of the scanning line driving circuits A and B (80) can be suppressed. The shift register circuit unit 90 can operate with a voltage of, for example, 0V to +5V.

The distribution circuit unit 88 is arranged after the shift register circuit unit 90 and has a function of distributing the output of each shift register circuit unit 90 to the first scanning line 82 or the second scanning line 84 according to the distribution signal. The distribution signal may be a signal for selecting any one of the first scanning line 82 and the second scanning line 84 . For example, a special signal for analog display or a special signal for digital display may be supplied from the control IC 32.

The distribution signal may use a mode switching first signal or a mode switching second signal. In FIG. 4 , in addition to the enable signal of the enable signal line 87 , the mode switching first signal of the MODE ( 62 ) signal is also used. As described above, since the mode switching first signal is a signal for selecting the analog display mode at the H potential and the digital display mode at the L potential, it can be distributed to the first scanning line 82 at the H potential and distributed at the L potential. to the second scan line 84 . A mode switch second signal of XMODE (63) may also be used instead of the mode switch first signal. As such, since the mode switching first signal or the mode switching second signal is used, no special allocation signal needs to be generated.

The potential shift circuit unit 92 is a circuit having a function of converting the potential and amplitude of the distributed signal into a potential and amplitude suitable for the scanning line selection signal. The level shift circuit section 92 can be constructed using well-known signal level shift circuit technology. The output driver circuit section 94 is a buffer circuit for supplying sufficient current for driving the scanning lines. The potential shift circuit unit 92 and the output driving circuit unit 94 are provided for each first scanning line 82 and each second scanning line 84 , respectively. In other words, (the number of first scanning lines 82 + the number of second scanning lines 84 ) = the number of potential shift circuit sections 92 = the number of output driver circuit sections 94 . That is, the potential shift circuit unit 92 and the output driving circuit unit 94 are circuits for the first scan line 82 and the second scan line 84 , and are provided separately without being shared. The output potential of the output drive circuit unit 94 varies depending on the application of the display device 10 , but can be set, for example, from 0V to −5V, or from 0V to +8V, or from 0V to +9V.

The output potential of the output drive circuit section 94 (ie, the potential of the scanning line selection signal) can be set to the same potential as the potential for the first scanning line 82 and the potential for the second scanning line 84 . Thereby, the potential shift circuit part 92 can be made common, and the output drive circuit part 94 can be made common.

In addition, depending on circumstances, the output potential of the output driver circuit unit 94 may be set to a potential different from the potential used for the first scanning line 82 and the potential used for the second scanning line 84 . For example, when used for the first scan line 82, it is preferable to consider the capacitive coupling (coupling) with the common electrode during analog display, and set the amplitude to be higher than that of the second scan line 84 when used for static digital display. The potential is large. When changing the point of view, the signal amplitude of the second scanning line 84 for digital display can be set smaller than the signal amplitude of the first scanning line 82 for analog display, and the reduced part can suppress the consumption of scanning line driving. electricity. For example, the scan line selection signal for the first scan line 82 may have an amplitude of -4V to +9V, and the scan line selection signal for the second scan line 84 may have an amplitude of 0V to +5V.

5A and FIG. 5B show the structure of the scanning line driving circuit, which is a diagram comparing the scanning line driving circuit used in a general active matrix liquid crystal display device and the scanning line driving circuit described in FIG. 4 . FIG. 5A shows the composition of the scanning line driving circuit used in the existing active matrix liquid crystal display device. Each scanning line uses a shift register circuit section (SR UNIT) 90, which is determined by the enable signal. Controlled enable circuit unit (ENB UNIT) 89, potential shift circuit unit (LS UNIT) 92, and output drive circuit unit (BUF UNIT) 94. The shift register circuit unit 90 , the level shift circuit unit 92 , and the output driver circuit unit 94 are the same as those described in FIG. 4 .

In contrast, FIG. 5B is a diagram showing the configuration of the scanning line drive circuits A, B (80) described in FIG. 4 , for the first scanning line (GATE 1A, etc.) The shift register circuit section (SR UNIT) 90 is shared and used, and the output of the shift register circuit section 90 is distributed to the distribution circuit section 88 by applying the MODE signal to the enable circuit section. The first scan line 82 and the second scan line 84 . Here, the distribution circuit part 88 makes the enable signal valid according to the signal of MODE, thereby exerting the function of distributing the output of the shared shift register circuit part 90 to the potential shift circuit part and the output of the first scanning line. Functions of the driver circuit unit, the potential shift circuit unit for the second scanning line, and the output driver circuit unit.

Therefore, in FIG. 5A of the prior art, although the numbers of the shift register 90, the enable circuit unit 89, the potential shift circuit unit 92, and the output driver circuit unit 94 need to reach the number of scanning lines respectively, according to the figure 4, as shown in FIG. 5B, since the shift register circuit part 90 is shared with the first scanning line and the second scanning line, the number of shift register circuit parts 90 only needs to be the total number of scanning lines. Half will do. Thereby, the overall size of the scanning line driving circuits A and B can be suppressed.

6A and 6B are diagrams for explaining the functions of the scanning line driving circuits A and B. As shown in FIG. 6A is a diagram showing how each first scanning line (GATE 1A, etc.) and each second scanning line (GATE 1B, etc.) are selected when the mode switching second signal in XMODE is L potential. 6B is a diagram showing how each first scanning line (GATE 1A, etc.) and each second scanning line (GATE 1B, etc.) are selected when the mode switching second signal in XMODE is H potential. As shown in FIG. 6A, when the mode switching second signal in XMODE is L potential, each first scanning line (GATE 1A, etc.) is selected time by time. In contrast, when the mode switching second signal in XMODE is H potential, as shown in FIG. 6B , each second scanning line (GATE 1B, etc.) is selected time-by-time.

Returning to FIG. 2 again, as described above, the data line drive circuit 70 is a circuit having a function of inputting image signals (ie, video signals) corresponding to each gradation to the data signal line 72 . Here, a general data line drive circuit for an active matrix type liquid crystal display device can be used as it is.

FIG. 7 is a diagram showing the configuration of the data line driving circuit 70 . The data line driving circuit 70 mainly includes a plurality of demultiplexers (demultiplexers) 78 , and connects an externally supplied video signal line 74 and an externally supplied selection signal line 76 . Furthermore, the data line driving circuit 70 has a function of dividing the video signal into three components of R, G, and B according to the selection signal, and outputting them as sub-pixels for color display to the data signal lines 72 of the display pixels.

Next, the operation of the display device 10 configured as described above will be described. During normal operation of the display device 10, full-color analog display is performed. At this time, the mode switching is set to the analog display mode by the control IC 32, the mode switching first signal in MODE (62) is set to H, the mode switching second signal in XMODE (63) is set to L, and Provided to each display pixel 42 and scanning line driving circuits A, B (80). In the scanning line driving circuits A and B ( 80 ), the distribution circuit unit 88 outputs a scanning line selection signal to select the first scanning line 82 side and select the first scanning line 82 of each display pixel 42 . Thus, in each display pixel 42, the N-channel transistor 44 is turned on (ON), and the mode selection circuit turns on the N-channel transistor 48 to operate the first display circuit to perform analog display. At this time, the N-channel transistor 46 on the digital display side is turned off (OFF), and since the mode switching second signal in XMODE (63) is L, the second display circuit side becomes completely switched from the first display circuit side. away state.

When the display device 10 becomes the standby state, the mode switching is set to a digital display mode by the control IC 32, the mode switching first signal in MODE (62) is set to L, and the mode switching second signal in XMODE (63) is set to L. The signal is set to H, and is supplied to each display pixel 42 and scanning line driving circuits A, B ( 80 ). In the scanning line driving circuits A and B ( 80 ), the distribution circuit unit 88 outputs a scanning line selection signal to select the second scanning line 84 side and select the second scanning line 84 of each display pixel 42 . Accordingly, in each display pixel 42 , the N-channel transistor 46 is turned on, and the video signal is held as binary data by the holding circuit 56 . Next, the mode selection circuit sets the transmission gate 50 into a conductive state, and operates the second display circuit to perform digital display. At this moment, the N-channel transistor 44 on the analog circuit side becomes an off state, and because the mode switching first signal in MODE (62) is L, so the first display circuit side becomes completely cut off from the second display circuit side. state.

Accordingly, an analog display mode and a digital display mode can be performed in one display device 10, and power consumption related to display during standby can be reduced. In addition, since the scanning line driving circuits A and B (80) share the shift register circuit portion 90 through the first scanning line 82 and the second scanning line 84, even if two types of scanning lines are used, it is possible to suppress its compositional scale. In addition, the amplitude of the scan line selection signal can be set differently through the first scan line 82 and the second scan line 84 , and at this time, the power consumption related to the drive of the scan line can also be reduced.

(second embodiment)

As described above, in the scanning line driving circuits A and B ( 80 ), the distribution circuit 88 is a circuit disposed between the shift register circuit unit 90 and the potential shift circuit unit 92 . In addition, in the scanning line driving circuits A and B, the distribution circuit unit may be provided after the output driving circuit unit. FIG. 8 is a diagram showing the configuration of scanning line driving circuits A and B (100) having such a configuration. Here, elements common to those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The scanning line driving circuits A and B (100) share the shift register circuit unit 90, the potential shift circuit unit 92, and the output driving circuit unit 94 as the first scanning line and the second scanning line, and Two outputs are provided in the output driver circuit section 94 . Then, for these two outputs, distribute to the first scan line (GATE 1A, etc.) and the second scan line by using a pair of distribution signals 102 with opposite polarities and including a distribution circuit 106 including a NOR (inverted OR) circuit. (GATE 1B, etc.). The distribution signal can use a dedicated signal, or a MODE or XMODE signal. In addition, the connection between the shift register circuit section 90 and the level shift circuit section 92 is controlled by the enable signal line 87 .

In this way, the shared portion between the first scanning line and the second scanning line can be enlarged, and the overall scale of the scanning line driving circuits A and B (100) can be further reduced.

(third embodiment)

The NOR circuit of FIG. 8 can be replaced with other circuits having a signal distribution function. FIG. 9 is a diagram showing the configuration of the scanning line driving circuits A, B (110) including the distribution circuit section 116 using the transfer gate 114. As shown in FIG. Components that are the same as in FIG. 4 and FIG. 8 are given the same reference numerals, and detailed description thereof will be omitted. Compared with the configuration of FIG. 8, only the NOR circuit 104 is replaced with the transfer gate 114. According to this configuration, the shared portion between the first scanning line and the second scanning line can also be enlarged, and the scanning line driving circuit can be suppressed. A, B (110) The size of the overall scale.

(fourth embodiment)

Next, among the display devices capable of analog display and digital display, the configuration and the like of a display device capable of digital display in an arbitrary area will be described.

FIG. 10 is a perspective view of a display device 210 capable of digital display in any area. The display device 210 includes: a lower glass substrate 230, an upper glass substrate 212, a sealing material 216 for sealing the liquid crystal 214 between the two glass substrates, and a light guide assembly on the back side of the lower glass substrate 230. The backlight 220 arranged at 218, and the polarizer 222 arranged on the surface side of the upper glass substrate 212; the display device 210 is an active matrix liquid crystal display device that can be illuminated by the backlight. The control IC 32 is mounted on the lower glass substrate 230 using COG technology, and is connected to the external circuit substrate 226 through an appropriate flexible circuit substrate 224 such as FPC.

The upper glass substrate 212 and the lower glass substrate 230 sandwich the liquid crystal 214 together, and apply a predetermined driving voltage on both sides of the liquid crystal 214 to display, and because it is opposite to the lower glass substrate 230, it is also called opposite substrate. The upper glass substrate 212 is provided with a counter electrode (ie, a common electrode) opposite to the pixel electrode of the lower glass substrate 230 , and is applied with a common electrode potential.

The lower glass substrate 230 is a transparent substrate in which a plurality of scan lines and a plurality of data signal lines are arranged in a grid pattern, and display pixels and polysilicon TFTs as switching components are arranged in each grid area. Here, two types of scanning lines are used as the scanning lines, and one type of scanning line is the same as that of a general active matrix liquid crystal display device. That is, when such a scanning line is used, the image signal from the data signal line is supplied to the pixel electrode of each display pixel selected by the scanning line by switching the function of the component, and according to the correspondence with the upper glass substrate 212 The liquid crystal molecules sealed between the upper glass substrate 212 and the lower glass substrate 230 are driven by a potential difference between the electrodes, thereby enabling display. Another type of scanline is used to display still images.

Thus, although two types of scanning lines are used, as described above, one type of scanning line is the same as that of a general active matrix liquid crystal display device, and is used for halftone display or moving image display. In the case of a color display device, it is used for full-color display. Another type of scan line uses a hold circuit capable of holding a binary value described later, and displays a still image while suppressing power consumption related to image display. In order to distinguish these two displays, the former can be called an analog display and the latter a digital display. It can also be called dynamic display and static display to replace the difference between analog display and digital display. In color display, it can also be called full-color display and still image display. Hereinafter, the names of analog display and digital display are used, and when other names are more appropriate, other names are used.

In addition, in order to distinguish the two types of scan lines, one type of scan line used for analog display is called a first scan line, and the other type of scan line used for digital display is called a second scan line. When analog display and digital display are performed for each display pixel, two scan lines, the first scan line and the second scan line, and one data signal line are respectively arranged for each display pixel.

FIG. 11 is a diagram showing an arrangement state of various elements on the lower glass substrate 230 . In the central part of the lower glass substrate 230 is provided a display area 240 planarly arranged in a substantially rectangular shape, and around the display area 240 are arranged a scanning line driving circuit 1 (280) and a scanning line driving circuit 2 (300). The first scan line 282 and the second scan line 302 select respective scan lines in sequence; the data line drive circuit 270 is used to input image signals (ie video signals) equivalent to each color scale to the data signal line 272; and the data line The pre-charging circuit 234 is used for inputting the middle potential of the video amplitude before inputting the video signal to the data signal line 272 . The scanning line driving circuit 1 (280), the scanning line driving circuit 2 (300), the data line driving circuit 270, and the data line pre-charging circuit 234 are respectively connected to the control IC 232.

Scanning line driving circuit 1 (280), scanning line driving circuit 2 (300), data line driving circuit 270, and data line precharging circuit 234 use TFTs manufactured by polysilicon transistor formation technology in the same way as TFTs in the display area 240. It is fabricated on the lower glass substrate 230 . That is, the lower glass substrate 230 is an SOG substrate made of active components.

Although the scanning line driving circuit 1 (280) and the scanning line driving circuit 2 (300) can directly use the scanning line driving circuit used in the general active matrix type liquid crystal display device, in order to reduce the power consumption related to the scanning line driving, it is relatively It is better to use parts suitable for analog display and digital display differently. Here, as shown in FIG. 11 , the scanning line driving circuit 1 ( 280 ) for analog display will be used as a driving circuit using a conventional shift register for sequentially selecting the first scanning line 282 . The scanning line driving circuit 2 (300) for digital display is used as a driving circuit using a decoder capable of randomly selecting the second scanning line 302. The details of the scanning line driving circuit 1 (280) and the scanner driving circuit 2 (300) will be described later.

The data line driving circuit 270 can directly use a data line driving circuit used in a general active matrix type liquid crystal display device. Details of the data line drive circuit 270 will be described later.

The control IC 232 has an LSI chip for controlling the functions of the scanning line driving circuit 1 (280), the scanning line driving circuit 2 (300), the data line driving circuit 270, the data line precharging circuit 234, etc., and is installed by COG technology A wiring pattern provided on the lower glass substrate 230 . The wiring pattern extends to the scanning line driving circuit 1 (280), the scanning line driving circuit 2 (300), the data line driving circuit 270, the data line precharging circuit 234, etc., and extends to the end of the lower glass substrate 230, Here, as illustrated in FIG. 10 , the connection is made to the flexible circuit substrate 224 .

The display area 240 is an area for arranging a plurality of display pixels 242 in a matrix. In the display area 240, a plurality of first scanning lines 282 from the scanning line driving circuit 1 (280) and a plurality of second scanning lines 302 from the scanning line driving circuit 2 (300) are arranged along the plane of the lower glass substrate 230 and a plurality of data signal lines 272 from the data line driving circuit 270 are arranged along a direction intersecting with a direction of a planar arrangement of the lower glass substrate 230 (for example, a direction of a planar arrangement of the lower glass substrate 230 Orthogonal direction) and configure. In the example of FIG. 11 , the first scanning lines 282 and the second scanning lines 302 are arranged along the horizontal direction of the paper, and the data signal lines 272 are arranged along the vertical direction of the paper. The first scanning line 282 and the second scanning line 302 are configured as a pair, and the display area 240 is divided into a plurality of grid-shaped areas by the pair of scanning lines and data signal lines 272, and each grid-shaped area is respectively Display pixels 242 are provided. Here, in the case of a color display device, sub-pixels can be used for each of R, G, and B, but the sub-pixels will be described below as display pixels 242 .

FIG. 12 is a diagram for explaining the configuration of the display pixel 242 . Hereinafter, description will be made using symbols in FIG. 10 and FIG. 11 . Here, one pixel at the upper left corner in the paper surface of the display area 240 in FIG. 11 is representatively displayed. That is, in order to distinguish a plurality of display pixels 242, the position of the grid-shaped region divided by the first scanning line 282, the second scanning line 302, and the data signal line 272 is set as the upper left on the paper in FIG. 11 When the origin, the right direction is defined as the X direction, the downward direction is defined as the Y direction, and X, Y are used for display, then the display pixel 242 in FIG. Similarly, in order to distinguish the plurality of first scanning lines 282, the plurality of second scanning lines 302, and the plurality of data signal lines 272, the upper left of FIG. When increasing, the first scanning line 282 , the second scanning line 302 , and the data signal line 272 corresponding to the display pixel 242 in FIG. 12 correspond to the first number respectively. In FIG. 12 , to illustrate the above situation, the first scan line 282 is marked as GATE-1A, the second scan line 302 is marked as GATE-1B, and the data signal line 272 is marked as DATA-1.

In FIG. 12 , the liquid crystal 214 used for display is marked as a liquid crystal capacitor C _LC ( 254 ). The liquid crystal capacitance C _LC ( 254 ) is the capacitance between the pixel electrode wiring 255 and the common electrode signal line 260 as a counter electrode. Here, the common electrode signal line 260 is marked SC.

First, each signal line and the like in FIG. 12 will be described. VDD (236) and VSS (238) are power supply voltage lines and ground lines of the control IC 232. For example, VDD=+5V, VSS=0V, etc. are set.

As described above, the common electrode signal line 260 is a signal line for transmitting the common electrode signal SC applied to the common electrode provided on the counter electrode of the upper glass substrate 212 . The common electrode signal SC is a signal using a rectangular wave for AC driving of the liquid crystal 214 . For example, a square wave signal varying from 0V to +4V may be used.

Vb ( 264 ) and Vw ( 266 ) are signal lines for AC driving the liquid crystal 214 during digital display. Vw (266) is a signal line for transmitting the potential at which the liquid crystal 214 becomes a white display when this is applied to the pixel electrode wiring 255, and is a signal for transmitting the same signal as the common electrode signal in the common electrode signal line 260. signal line. Vb (264) is a signal line for conveying the potential at which the liquid crystal 214 becomes black display when this is applied to the pixel electrode wiring 255, and is a signal line for conveying the inversion of the common electrode signal in the common electrode signal line 260. signal signal line.

MODE ( 262 ) and XMODE ( 263 ) are signal lines conveying two mode switching signals for switching between the analog display mode and the digital display mode for the display pixel 242 . In order to distinguish the two mode switching signals, the signal in MODE (262) can be called the first mode switching signal, and the signal in XMODE (263) can be called the second mode switching signal. The mode switching first signal in MODE (262) and the mode switching second signal in XMODE (263) are mutually inverse signals, when the mode switching first signal in MODE (262) is H potential, XMODE (263) When the mode switching second signal in the mode is L potential, it can be used as an analog display mode, and when the mode switching first signal in MODE (262) is L potential, and the mode switching second signal in XMODE (263) is H potential , can be used as a digital display mode.

The mode switching first signal in MODE ( 262 ) and the mode switching second signal in XMODE ( 263 ) have opposite polarities as described above, but have different amplitudes and waveforms that are asymmetrical to each other. This point is opposite to turning on (ON)/off (OFF) the N-channel transistor 248 and transmitting the analog video signal to the pixel electrode wiring 255 by the H potential of MODE (262), while the H of XMODE (263) The potential is different because it simply switches the two potential standards in Vb (264) or Vw (266). For example, for switching between the analog display mode and the digital display mode, the mode switching first signal in MODE (262) can be set to H potential=+9V, L potential=0V, and the mode switching second signal in XMODE (263) can be set to The signal was set to L potential=-4V and H potential=+4V.

Next, each element constituting the display pixel 242 in FIG. 12 will be described. The N-channel transistor 244 is a component that operates according to the scan line selection signal of the first scan line 282 . In addition, the N-channel transistor 246 is a component that operates according to the scan line selection signal of the second scan line 302 . In order to distinguish these two components, the N-channel transistor 244 may be referred to as a first switch circuit, and the N-channel transistor 246 may be referred to as a second switch circuit.

An N-channel transistor 248 is also connected between the N-channel transistor 244 as the first switch circuit and the pixel electrode wiring 255 . The N-channel transistor 248 is a component that operates according to the mode switching first signal in MODE ( 262 ), and the N-channel transistor 248 can be called a third switch circuit. Then, when both the N-channel transistor 244 as the first switch circuit and the N-channel transistor 248 as the third switch circuit are turned on (that is, the first scanning line 282 is selected by the scanning line selection signal, and the second scanning line is selected by the mode switching When the analog display mode is selected via a signal), image signal data (ie, video signal data) of the data signal line 272 is transmitted to the pixel electrode wiring 255 and written into the liquid crystal 214 .

Here, for the display pixel 242, if a circuit for sequentially supplying video signals successively input from the data signal line 272 to the pixel electrode wiring 255 of the display pixel 242 for analog display is taken as the first display circuit, it is defined in a narrow sense as the first display circuit. It is said that the liquid crystal capacitor C _LC 254 and the auxiliary capacitor C _S 252 are equivalent to the first display circuit, and broadly speaking, the first display circuit may also include the N-channel transistor 244 and the N-channel transistor 248 .

To the output side of the N-channel transistor 246 that is the second switch circuit, a hold circuit 256 that can hold data statically by connecting two inverter wires in a loop is connected. The holding circuit 256 is a circuit having a function of statically holding the video signal data when the video signal data is written, and is a static memory whose data holding consumes little power.

Furthermore, the two sets of transfer gates 258, 259 provided between the respective output terminals of the two inverters constituting the holding circuit 256 have the signal of Vb(264) or The Vw ( 266 ) signal provides the function to transfer gate 250 . Since the front end of the transfer gate 250 is the pixel electrode wiring 255, the transfer gates 258 and 259 have signal potentials for selecting the potential supplied to the pixel electrode wiring 255 to Vb (264) based on the data stored in the holding circuit 256. Or set the signal potential of Vw (266) as the function of the pixel electrode potential selection switch.

Next, the transmission gate 250 is a circuit that operates according to the inverse signal of the mode switching second signal of XMODE (263) and the mode switching first signal of MODE (262), and the transmission gate 250 can also be called a fourth switch circuit. The transfer gate 250 as the fourth switching circuit has a function of supplying the signal of Vb ( 264 ) or the signal of Vw ( 266 ) which is the output of the two sets of transfer gates 258 , 259 to the pixel electrode wiring 255 . That is, when XMODE ( 263 ) is at H potential and MODE ( 262 ) is at L potential, a signal of Vb ( 264 ) or a signal of Vw ( 266 ) is supplied to the pixel electrode wiring 255 according to the signal held by the holding circuit 256 . As described above, since the signal of Vw (266) is the same signal as the SC of the common electrode signal line 260, and the signal of Vb (264) is an inverted signal of SC, the signal held by the holding circuit 256 can be The liquid crystal 214 between the pixel electrode wiring 255 and the common electrode signal line 260 is AC-driven. That is, the liquid crystal 214 can display a binary still image corresponding to the signal held by the holding circuit 256 .

Here, the display pixel 242 has a holding circuit 256 for holding an image signal, and a circuit for supplying a voltage corresponding to the signal held by the holding circuit 256 to the pixel electrode wiring 255 for digital display is referred to as a second circuit. When displaying a circuit, in a narrow sense, the holding circuit 256 is equivalent to the second display circuit, and in a broad sense, the second display circuit may also include an N-channel transistor 246, a holding circuit 256, transmission gates 258, 259, and transmission gates. 250. In FIG. 12 , a circuit portion 43 surrounded by a dotted line corresponds to a second display circuit in a broad sense. In addition, in the display pixel 242 , except for the circuit portion 243 surrounded by a dotted line, the other circuit portions correspond to the first display circuit in the broad sense described above.

In addition, the N-channel transistor 248 operates according to the mode switching first signal in MODE (262), and the transmission gate 250 operates according to the mode switching second signal in XMODE (263), and since the display pixel 242 has the function of switching the analog display mode and The function of the digital display mode, so these circuit parts can be collectively referred to as the mode switching circuit.

In this way, for each display pixel 242 of the display device 210, the first scanning line 282 and the second scanning line 302 can be selected according to a predetermined scanning line selection signal, and the image signal from the data signal line 272 can be received, and the second scanning line can be switched according to the mode. A signal and a mode switching second signal are used to select the analog display mode or the digital display mode, make the first display circuit or the second display circuit operate, and perform analog display or digital display.

Returning to FIG. 11 again, the scanning line driving circuit 1 ( 280 ) and the scanning line driving circuit 2 ( 300 ) will be described. Both the scan line driving circuit 1 ( 280 ) and the scan line driving circuit 2 ( 300 ) have circuits for generating scan line selection signals. Specifically, the scanning line driving circuit 1 ( 280 ) generates a scanning line selection signal for the first scanning line 282 , and the scanning line driving circuit 2 ( 300 ) generates a scanning line selection signal for the second scanning line 302 . Therefore, the scanning line driving circuit 1 (280) for driving the first scanning line can be called the first scanning line driving circuit, and the scanning line driving circuit 2 (300) for driving the second scanning line can be called the second scanning line driving circuit. Scanning line driver circuit.

In FIG. 11 , the scanning line driving circuit 1 ( 280 ) and the scanning line driving circuit 2 ( 300 ) are disposed on opposite sides of each other with the display area 240 interposed therebetween. Of course, both the scanning line driving circuit 1 ( 280 ) and the scanning line driving circuit 2 ( 300 ) can also be arranged on one side of the display area 240 . In addition, one scanning line driving circuit may be arranged on one of any two sides of the display area 240, and the other scanning line driving circuit may be arranged on the other side.

As described above, the scanning line driving circuit 1 (280) for analog display has a configuration using a conventional type shift register that sequentially selects the first scanning line 282. The scanning line driving circuit 2 (300) for digital display has a configuration using a decoder that can randomly select the second scanning line 302.

FIG. 13 is a diagram showing the configuration of the scanning line driving circuit 1 (280). The scan line driving circuit 1 ( 280 ) is a circuit for generating a signal for time-by-time selection of each first scan line 282 according to a time-by-time signal 286 composed of a start signal and a frequency signal. The scanning line driving circuit 1 ( 280 ) includes a shift register circuit unit 290 , an enabling circuit unit 289 , a potential shift circuit unit 292 , and an output driving circuit unit 294 .

The shift register circuit unit 290 has a function of sequentially shifting the clock signal 286 which is sequentially input from time to time, and outputting sequential designation pulses for designating display pixels in units of scanning lines. The shift register circuit unit 290 can operate with a voltage of, for example, 0V to +5V.

The enable circuit unit 289 is arranged behind the shift register circuit unit 290, and has the function of distributing the output of each shift register circuit unit 290 to each first scanning line 282 according to the potential of the enable signal of the enable signal line 287. The function of the potential shift circuit part 292 and the output drive circuit part 294. Specifically, as shown in FIG. 13 , it can be configured using a NAND (inverse AND) circuit connected to an enable signal line.

The level shift circuit unit 292 is arranged after the enable circuit unit 289 and has a function of converting the potential and amplitude of the output signal of the enable circuit unit 289 into the potential and amplitude suitable for the scanning line selection signal. The level shifting circuit section 292 can be constructed using well-known signal level shifting circuit technology. The output driver circuit section 294 is a buffer circuit for supplying sufficient current for driving the scanning lines. The output potential of the output drive circuit unit 294 varies depending on the application of the display device 210 , but can be set to, for example, 0V to −5V, or 0V to +8V, or 0V to +9V.

FIG. 14 is a diagram showing the configuration of the scanning line driving circuit 1 (280). As shown in FIG. 14, a shift register circuit unit (SR UNIT) 290, an enable circuit unit (ENB UNIT) 289 controlled by an enable signal, and a potential shift circuit unit ( LS UNIT) 292, and an output drive circuit section (BUF UNIT) 294.

FIG. 15 is a diagram showing the configuration of the scanning line driving circuit 2 (300). The scanning line driving circuit 2 (300) is a circuit for generating a signal for selecting each second scanning line 302 according to each signal of a plurality of address signal lines 304, and as shown in FIG. The NAND circuit 306 and the buffer circuit 308 constitute. A pre-decoder circuit may also be provided before the NAND circuit 306 . Since a circuit having such a configuration is called a decoder circuit, it does not matter if the operating speed is not high compared with the scanning line driving circuit 1 (280) which must operate at a high speed using clock signals. Therefore, the power consumption of the scanning line driving circuit 2 (300) can be suppressed to be lower than the power consumption of the scanning line driving circuit 1 (280).

The potential of the scanning line selection signal of the scanning line driving circuit 1 (280) (that is, the potential of the output driving circuit section 294) and the potential of the scanning line selection signal of the scanning line driving circuit 2 (300) (that is, the potential of the buffer circuit 308) can be changed. Set differently according to the difference in motion speed. For example, as described above, the potential of the output driver circuit unit 294 can be set to 0V to +8V, and the potential of the buffer circuit unit 308 can be set to 0V to +5V. Accordingly, the power consumption of the scanning line driving circuit 2 (300) can be reduced to be lower than the power consumption of the scanning line driving circuit 1 (280). Of course, the potential of the scanning line selection signal can also be set to be the same in both the scanning line driving circuit 1 ( 280 ) and the scanning line driving circuit 2 ( 300 ).

Returning again to FIG. 11 , as described above, the data line drive circuit 270 is a circuit having a function of inputting video signals (ie, video signals) corresponding to each gradation to the data signal line 272 . Here, a general data line drive circuit for an active matrix type liquid crystal display device can be used as it is.

FIG. 16 is a diagram showing the configuration of the data line driving circuit 270 . The data line drive circuit 270 mainly includes a plurality of demultiplexers 278 and connects an externally supplied video signal line 274 and an externally supplied selection signal line 276 . Furthermore, the data line driving circuit 270 has a function of dividing the video signal into three components of R, G, and B according to the selection signal, and outputting the sub-pixels for color display to the data signal lines 272 of the display pixels.

Next, the operation of the display device 210 configured as described above will be described. In normal operation of the display device 210, full-color analog display is performed. At this time, the scanning line driving circuit 1 (280) is set to an operating state and the scanning line driving circuit 2 (300) is set to a non-operating state by the control IC 232. In addition, the mode switching is set to the analog display mode through the control IC 232, the mode switching first signal in MODE (262) is set to H, the mode switching second signal in XMODE (263) is set to L, and provided to Individual display pixels 242 . As described above, in the scanning line driving circuit 1 ( 280 ), the scanning line selection signal is output, so that the first scanning line 282 of each display pixel 242 is selected. Therefore, in each display pixel 242 , the N-channel transistor 244 is turned on, and the mode selection circuit turns on the N-channel transistor 248 , so that the first display circuit operates to perform analog display. At this time, the N-channel transistor 246 on the digital display side becomes an off state, and since the mode switching second signal in XMODE (263) is L, the second display circuit side becomes completely cut off from the first display circuit side. state.

When the display device 210 is in the standby state, the control IC 232 sets the scanning line driving circuit 2 (300) into an operating state and the scanning line driving circuit 1 (280) into an inactive state. In addition, set the mode switch to digital display mode by controlling IC 232, set the mode switch first signal in MODE (262) to L, set the mode switch second signal in XMODE (263) to H, and provide to Individual display pixels 242 . In the scan line driving circuit 2 ( 300 ), a scan line selection signal is output, so as to select the second scan line 302 of each display pixel 242 . Thus, in each display pixel 242 , the N-channel transistor 246 is turned on, and the image signal is held by the holding circuit 256 as binary data. Next, the mode selection circuit sets the transmission gate 250 into a conduction state, so that the second display circuit operates to perform digital display. At this time, the N-channel transistor 244 on the analog circuit side is turned off, and since the mode switching first signal in MODE (262) is L, the first display circuit side becomes a state where the second display circuit side is completely cut off. .

Accordingly, an analog display mode and a digital display mode can be performed on one display device 210, and power consumption related to display during standby can be reduced. In addition, since the scanning line driving circuit 2 (300) is configured as a decoder circuit, it consumes less power than the first scanning line driving circuit 1 (280), and can suppress the display device 210 as a whole. Power consumption of scan line drive. In addition, the amplitude of the scan line selection signal can be set differently through the first scan line 282 and the second scan line 302 , and at this time, power consumption related to scan line driving can also be reduced.

(fifth embodiment)

As described above, the scanning line driving circuit 2 (300) is a decoder circuit type, and the voltage system is common to that of a general logic circuit. In contrast, in the scanning line driving circuit 1 (280), the shift register The voltage systems of the circuit unit 290 , the level shift circuit unit 292 , and the output driving circuit unit 294 are relatively complicated. The scanning line driving circuit 1 (280) and the scanning line driving circuit 2 (300) may be supplied with power from the outside, but the power supply circuit may be mounted on the lower glass substrate.

17 is a diagram showing an example of mounting a power supply circuit on a lower glass substrate, that is, a power supply circuit 332 used for the scanning line driving circuit 1 ( 280 ) is mounted on a lower glass substrate 330 . In addition, the same elements as those in FIG. 11 are assigned the same reference numerals, and detailed description thereof will be omitted. The power supply circuit 332 can be used as an IC chip and installed on the wiring pattern on the lower glass substrate 330 by COG technology, or it can also be directly fabricated on the lower glass substrate 330 by using polysilicon transistor formation technology as the case may be. In addition, the power used by the scan line driving circuit 2 (300) can also be provided by the control IC 32.

(sixth embodiment)

In the above, it has been described that the first scanning line and the second scanning line are arranged as a pair in each display pixel, but some display pixels may not be in a pair. 18 and 19 are diagrams showing the structure of the lower glass substrate 340 when only the second scanning line is arranged in a part of the display pixels. Conversely, only the first scan line may be arranged on a part of the display pixels. Hereinafter, elements common to those in FIGS. 11 and 17 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 18, in the lower glass substrate 340, the display area 240 is divided into two parts, and in one part, the first scanning line 282 and the second scanning line 302 are arranged as a pair for each display pixel, And in another part, only the second scan line is configured to display pixels. Thus, as described in FIG. 11 , the former part can be made into (full-color display area+still image display area) 241, and the latter part can be made into still image display area 342 capable of displaying only still images. These areas can be made as fixed areas.

FIG. 19 is a diagram for showing the wiring state of each element on the lower glass substrate 340 when the configuration of FIG. 18 is adopted, along the lines of FIGS. 11 and 17 . As shown in FIG. 19 , in the still image display area 342 of a part of the display area 240 , the scan line selection signal is supplied only through the second scan line 344 from the scan line drive circuit 2 .

Claims (14)

1. A display device, characterized in that, possesses: A plurality of first scanning lines arranged in one direction on the substrate for analog display; A plurality of second scanning lines arranged in the aforementioned direction on the substrate for digital display; A plurality of data signal lines arranged in a direction intersecting with the aforementioned one direction; A plurality of display pixels are selected by a predetermined scan line selection signal for the first scan line or the second scan line, receive image signals from the data signal lines, and are arranged in a matrix on the substrate. ; The first display circuit is connected to the first scanning line via the first switch circuit that operates according to the scanning line selection signal, and is arranged on the display pixel, and supplies the sequentially input image signal to the display pixel sequentially. pixel electrodes for the aforementioned analog display; The second display circuit is connected to the second scanning line through the second switch circuit operated according to the scanning line selection signal, and is arranged in the display pixel, and has a holding circuit for holding the image signal, and is used for holding the image signal. supplying a voltage corresponding to the signal held by the aforementioned holding circuit to the aforementioned pixel electrode for performing the aforementioned digital display; and The mode switching circuit performs mode switching between an analog display mode operated by the first display circuit and a digital display mode operated by the second display circuit based on a mode switching signal. 2. The display device according to claim 1, further comprising: a first scanning line driving circuit, outputting a scanning line selection signal related to the aforementioned first scanning line; A second scanning line driving circuit, outputting a scanning line selection signal related to the aforementioned second scanning line; and, The first scanning line driving circuit and the second scanning line driving circuit share a shift register circuit portion that outputs sequentially specifying pulses for sequentially specifying the display pixels in units of scanning lines, and use them in a shared manner. In the distribution circuit section provided after the shared shift register circuit section, the sequentially designated pulses are distributed to the first scanning line or the second scanning line according to the distribution signal. 3. The display device according to claim 2, further comprising: A plurality of first output circuits and a plurality of second output circuits are respectively connected in parallel to each output of the aforementioned shift register circuit portion; and, A plurality of the first output circuits are set corresponding to the plurality of the first scanning lines; A plurality of the second output circuits are set corresponding to the plurality of second scanning lines; The distribution circuit section distributes the output of the first output circuit or the output of the second output circuit to the first scanning line or the second scanning line using the distribution signal. 4. The display device according to claim 3, wherein the distributing circuit portion is formed of a NOR circuit or a transfer gate. 5. The display device according to claim 2, wherein the distribution signal uses the mode switching signal. 6. The display device according to claim 1, wherein: The aforementioned mode switching signal is composed of a mode first switching signal and a mode second switching signal with different signal amplitudes and opposite polarities; The mode switching circuit operates the first display circuit on the condition that the mode switching first signal is turned on, and operates the second display circuit on the condition that the mode switching second signal is on. 7. The display device according to claim 6, wherein the aforementioned mode switching circuit comprises: The third switch circuit is arranged between the first switch circuit and the pixel electrode, and operates according to the mode switching first signal; and, The fourth switch circuit is arranged between the aforementioned holding circuit and the aforementioned pixel electrode, and operates according to the mode switching second signal, and is used for corresponding to the signal held by the aforementioned holding circuit, and is applied to the pair opposite to the pixel electrode. A signal of the same phase or an inverted phase of the counter electrode signal of the counter electrode is supplied to the aforementioned pixel electrode. 8. The display device according to claim 1, wherein signal amplitudes of the scan line selection signal for the first scan line and the scan line selection signal for the second scan line are different from each other. 9. The display device according to claim 1, further comprising: The first scanning line driving circuit is a circuit that outputs a scanning line selection signal related to the first scanning line, and has a shift register that outputs sequentially designated pulses for sequentially designating each of the first scanning lines. Electronics Division; and, The second scanning line driver circuit is a circuit that outputs a scanning line selection signal related to the second scanning line, and has a decoder circuit portion for selecting each desired second scanning line. 10. The display device according to claim 9, wherein signal amplitudes of the scan line selection signal for the first scan line and the scan line selection signal for the second scan line are different from each other. 11. The display device according to claim 10, further comprising: a power circuit section formed on the aforementioned substrate for generating power supplied to the aforementioned first scanning line driving circuit; and, The control circuit part is a control circuit part formed on the aforementioned substrate and used to control various elements on the aforementioned substrate, and is used to provide power to the aforementioned second scanning line driving circuit. 12. The display device according to claim 9, further comprising a display area dedicated to digital display, and a plurality of pixels driven only by the second scanning line driving circuit are arranged on the substrate. 13. The display device according to claim 12, characterized in that when the digital display area is displaying numbers, other display areas will not display numbers. 14. A display device, characterized in that it has: A plurality of first scanning lines arranged in one direction on the substrate for analog display; A plurality of second scanning lines arranged in the aforementioned direction on the substrate for digital display; A plurality of data signal lines arranged in a direction intersecting with the aforementioned one direction; The display pixels are selected by a predetermined scan line selection signal for the first scan line or the second scan line, receive image signals from the data signal lines, and are arranged in a matrix on the substrate; The first scanning line driving circuit is a circuit that outputs a scanning line selection signal related to the first scanning line, and has a shift register circuit that outputs sequentially specifying pulses for sequentially specifying each of the first scanning lines Department; and, The second scanning line driver circuit is a circuit that outputs a scanning line selection signal related to the second scanning line, and has a decoder circuit portion for selecting each desired second scanning line.

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