CN100570386C - Wafer-level optoelectronic testing apparatus and method - Google Patents
Wafer-level optoelectronic testing apparatus and method Download PDFInfo
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- CN100570386C CN100570386C CN 200580011617 CN200580011617A CN100570386C CN 100570386 C CN100570386 C CN 100570386C CN 200580011617 CN200580011617 CN 200580011617 CN 200580011617 A CN200580011617 A CN 200580011617A CN 100570386 C CN100570386 C CN 100570386C
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Abstract
A wafer level test apparatus for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure performs optical and electrical testing using a single opto-electronic testing element. Beam steering optics may be formed on the test element and used to facilitate coupling between the optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signal is thereafter directed into an optical waveguide formed in the top layer of the SOI structure. The optoelectronic test element also includes a plurality of electrical test pins placed in contact with a plurality of solder joint test locations on the optoelectronic device and for performing electrical test operations. The optical test signal results may be converted to an electrical representation within the SOI structure and thus returned to the test element as an electrical signal.
Description
The cross-reference of related application
The application requires in the U.S. Provisional Application No.60/551 of submission on March 8th, 2004,316 rights and interests.
Technical field
The present invention relates to the device of wafer level test, more specifically, relate to the ability of using single testing element that optics, electricity and the photoelectricity test of structrural build up each element of insulator silicon (SOI) are provided.
Background technology
In semi-conductor industry, handle big relatively silicon wafer (diameter generally several inches the order of magnitude) approximately and form many identical integrated circuits.In case wafer is handled fully, it is cut in flakes to form independent integrated circuit.In most of the cases, form hundreds of identical circuits across wafer surface.If before cutting, the performance of not testing independent circuit, " bad " chip may be further processed and encapsulate so, and this has wasted valuable time and wealth.
Wafer level test is known in semi-conductor industry, and is used to traditionally to measure and ought still be the various electrical quantitys on each integrated circuit of wafer form, is consistent with the specification of being scheduled to verify this integrated circuit.Except verifying ability up to specification, wafer level test in the integrated circuit industry has the identification technological problems, provide by/by standard, carry out data aggregation and generation/operation capability to the special test (for example, the test of client's appointment) of wafer.
Now, the increasing use of integrated electronic on single soi structure and optical device need be used for the development of the wafer level test of this electronics and optical device.This wafer level test need be tested the electric I/O of solder joint (test pad)/form, and the light I/O of form such as coupling mechanism, optical fiber.The normally used method that is used for optically-coupled is advanced SOI waveguide (for example, fall nanocone and three-dimensional awl) needs the edge of access chip (or small pieces (die)) to be coupled to waveguiding structure.The people's such as D.E.Nikonov that publish United States Patent (USP) 6,859,587 has illustrated one exemplary " edge " coupling process that is used for other lightwave circuit of testing wafer level.In this case, first optical fiber is coupled to first " edge " of lightwave circuit, and is used for probe/test light signal is introduced lightwave circuit.Second optical fiber is coupled to relative " edge " of this circuit, and is used for collecting output/test light signal.Be considered to the serious restriction of this special wafer scale optical tests method for the needs of " edge " of circuit visit.
In laid-open U.S. Patents application on July 3rd, 2003 bulletin 2003/123793 (" Johannessen ") a kind of optionally " light probe " device has been described, wherein pass through to remove the top surface part of the line material in institute's favored area to obtain visit to waveguiding structure, allow light probe to be brought to directly and contact, realize the test of planar lightwave circuit with this waveguide.Although this device has been eliminated the needs to execution " edge " contact, yet this kind device is considered to " destructive testing ", this is to carry out test because must remove a part of circuit.Significantly, when a plurality of place on line on wafer were carried out repeated test, destructive testing was not preferred selection.In addition, do not know that this kind light probe can be used for the optical waveguide of submicron-scale, find that its use for the single mode communications applications is increasing.In addition, these one type of prior art syringe all need be used the fluid (having increased about measuring repeatability and pollution problem) of coefficients match (index matching) between light probe and wafer, and only optic test is provided; Still need traditional electronics " probe card (probe card) analyze with testing wafer on electron device.
Therefore, need optics and Electronic Testing are combined to the wafer level test method of single device in the prior art.
Summary of the invention
Solve the needs that keep in the prior art by the present invention, the present invention relates to the device of wafer level test, more specifically, relate to the ability of using single testing element that optics, electricity and the photoelectricity test of structrural build up each element of insulator silicon (SOI) are provided, advantageously replenish the relevant knowledge hierarchy of conventional wafer level test with electronic unit.
According to the present invention, the photoelectricity test element is configured to comprise light and the needed parts of electrical testing.As common pending application (for example, referring to, the application No.2004/0213518 that the U.S. that announced in about 8 days in 2004 11 announces, or the sequence number of submitting on September 7th, 2004 is 10/935,146 U. S. applications) disclosed in the multiple application, the soi layer that light directly is coupled into described structure is realized by lip-deep smooth prism or optical grating construction that use is arranged in described soi structure to the direct sunshine coupling of the part of the optical waveguide (soi layer) of the submicron-scale of photoelectric chip.In photoelectricity test element of the present invention, can comprise beam steering/shaping optical device, with and be used to provide into and the effective coupling that goes out described prism/optical grating construction.A plurality of electrical testing points (probe) form on described testing element with traditional pattern, with the electrical testing of the expectation of carrying out described soi structure.
In a preferred embodiment, can between the beam steering part of described soi structure and described photoelectricity test element, apply feedback signal, adjust the position of described wave beam with the coupling element on the described relatively soi structure.
Use fiber array, polarization-maintaining fiber preferably, the input and output optical tests that can be coupled signal.Outer lens (or the integrated lens that form on fiber end face) can be used for increasing coupling efficiency.It is tuning that use is controlled input wavelength from the one or more feedback signals of described wafer, can carry out described tuningly, with the wave guide mode angle of just testing of coupling on wafer surface, therefore increased coupling efficiency.
In the argumentation below and by with reference to the accompanying drawings, of the present invention other and further change and aspect will become obvious.
Description of drawings
With reference now to accompanying drawing,,
Fig. 1 is at exemplary light electrical testing element of the present invention shown in the side view, and this photoelectricity test element is connected with soi structure to be tested, and the embodiment of Fig. 1 makes with the light prism coupling between testing element and soi structure is provided.
Fig. 2 illustrates replaceable photoelectricity test element of the present invention, and its beam steering/shaping optical device that is included in this testing element is coupled to the optical tests signal in the soi structure with help;
Fig. 3 is at replaceable photoelectricity test element of the present invention shown in the side view, and this embodiment uses the grating that forms on the soi structure surface that the input and output coupling is provided;
Fig. 4 is the vertical view of exemplary light electrical testing element of the present invention; And
Fig. 5 shows the exemplary proving installation that is used to carry out wafer level test according to of the present invention.
Embodiment
As above concise and to the point institute is carried, and being used for based on one of maximum challenge of the development of the optical tests element of SOI optical texture is, need light beam coupling be advanced in the very thin waveguide of just testing reliably in mode repeatably.Light enter the required angle of thin waveguide be known as the wavelength of duct thickness and light signal majorant (that is, control with needing enter soi structure the optical mode angle to excite the character modules in the waveguide).An aspect of of the present present invention is can be at the wavelength of a scope " tuning " test signal, thereby can repeatably realize acceptable coupling reliably on the basis.Because technique change can change the thickness of the ducting layer of different chips, and the die thickness of coupling layer (evanescent couplinglayer) of related declining, therefore be considered to important breakthrough in the wafer level test of optoelectronic components according to the ability of monitoring of the present invention and " tuning " test wavelength.
Fig. 1 uses photoelectricity test element 10 formed according to the present invention that the side view of the exemplary means of wafer-level opto-electronic test is provided for being used to.Testing element 10 forms and supports at least one input light probe 11, is the optical fiber that comprises lensed endface (lensed endface) 13 in the case.Should be appreciated that,, can use the array of such lens fiber that a plurality of different optical tests signals are provided as specifically illustrating among following Fig. 3.Return with reference to figure 1, input light probe 11 accurately aligns, and be fixed in the testing element 10, thereby probe 11 with the beam-riding that enters to the wafer of just testing, be depicted as on the soi structure 20.A plurality of Electronic Testing probe points 16 are shown, are also included within on the testing element 10, be used for soi structure 20 on a plurality of electric contacts (for example, pad) 34 electric coupling.Should be appreciated that,, on independent basis, carry out detection and test the soi structure that each separates by " stepping and the repetition " method that moves wafer relative to test probe usually for " wafer " test.Return with reference to figure 1, the last silicon face layer 26 (hereinafter referred to as " soi layer 26 ") that soi structure 20 comprises silicon substrate 22, silicon dioxide insulating layer 24 and relative thin (general sub-micron thick) is shown.In the specific embodiment of Fig. 1, the declining of the relative thin coupling layer 28 that dies (comprises the material with refraction coefficient littler than the refraction coefficient of silicon, for example silicon dioxide and silicon nitride) be arranged on the selected portion of soi layer 26, and be used for the coupling that auxiliary lightwave signal advances and go out soi layer 26.As shown in Figure 1, input light prism 30 and output light prism 32 are arranged in to decline and die on the selected portion of coupling layer 28, and the light between testing element 10 and the soi structure 20 of being used to be coupled.
In a preferred embodiment of the invention, prism coupler comprises silicon structure (for example, forming) on the silicon substrate that separates, for good and all be fixed on the soi structure 20 then, and the optically-coupled (and further test) that is used for providing the finished product device architecture.The one side of this embodiment of the present invention is, uses this permanent coupled structure also to use the part of the light probe that acts on the photoelectricity test element.Replacedly, one or more prism structures can form as the integrated component on the photoelectricity test element 10.
Then,, contact, carry out wafer level test by making institute's favored area on photoelectricity test element 10 and the wafer (being the soi structure 20 of " selected " shown in Figure 1) according to the present invention.The optical tests wave beam is injected waveguide in the soi structure 20 with predetermined angle.Be coupled into the luminous power of the signal of SOI waveguide by monitoring, the wavelength of (for example, being the variation of compensation duct thickness and/or the variation of testing element structure) tunable input test signal is with the coupling of optimization optical tests signal in the SOI waveguide.In case realize satisfied input test signal power, carry out a series of light and electrical testing, its result feeds back to analytical equipment.Use tradition " stepping and repetition " mechanism, wafer moves relative to testing element 10, thereby the soi structure of each separation is studied.If a certain soi structure is not by one or more tests (light and/or), the that part of of wafer (for example can be labeled as " bad " so, use this structure of magnetic ink mark), and when this wafer is cut into the small pieces of a plurality of separation, abandon it simply.In addition, the software figure that can produce and keep wafer is to be used for reference in the future, and the software figure of this wafer defines the test result of each independent small pieces.As mentioned above, the remarkable advantage of testing element of the present invention is, obtains all wafers level electricity, light and photoelectricity test data by using identical testing element, therefore greatly reduces time and the expense relevant with the wafer level test process.
Fig. 2 illustrates the alternative embodiment of photoelectricity test element 10, and it is included in the beam steering/shaping optical device in the testing element 10 in the case, and the free space light signal is coupled into and is coupled out testing element.The dynamic adjustment of the beam direction that allows between testing element 10 and the soi structure 20 the comprising of beam steering/shaping optical device, focusing etc., it uses the measuring light power result who is received on soi structure 20 to carry out described adjustment.In the device of the embodiment of Fig. 2, input optical tests signal is propagated by a cross section of polarization-maintaining fiber 40, and it is coupled into the beam steering optical device 12 on the testing element 10 then.Polarization-maintaining fiber 42 similar cross sections can be used for being coupled out the test response signal of outgoing.According to the present invention, can be used for adjusting the feature of each catoptron in beam steering/shaping optical device 12 and/or 14, lens etc. from the analysis of the characteristic of the output signal of polarization-maintaining fiber 42, so that the acceptable degree of coupling of optical tests signal to be provided.For allowing the I/O measuring fiber to be positioned at preferred direction (promptly comprising of beam steering/shaping optical device, optical fiber can be arranged on the plane identical with testing element 10, and provide " level emission " to install, or replacedly, optical fiber can be perpendicular to the floor plan of testing element 10, and " Vertical Launch " device is provided).
As the replacement of polarization-maintaining fiber, can use the optical fiber (or general waveguide) of multiple other type.For example, standard single-mode fiber, multimode optical fiber, lensed optical fiber etc. can use all.Each detecting device (in the chip or outside the chip) and detector array can be used for replacing output optical fibre. Beam steering element 12 and 14 can further comprise for example element of polarization beam apparatus and half-wave plate, and this half-wave plate is used to provide Polarization Control and rotation.Alternatively, factor (off-element) parts that black out can be used for providing the Polarization Control of expectation.About light source itself, can use various devices.For example can use tunable laser (or tunable laser array), " tuning " wavelength is to provide optimized coupling efficiency and/or test in different system wavelength.In addition, can use vertical cavity surface emitting LED (VCSEL) array.Other device also is possible, and all being considered to drops in the spirit and scope of the present invention.
Fig. 3 comprises the vertical view of the device of Fig. 2, in the case, the polarization state of the optical tests signal that use applied with control at the factor that the blacks out polarization control component 60 of the input of photoelectricity test element 10 is shown.Be apparent that in this view first group of electrical testing probe points 16-1 arranges along first side of testing element 10, and second group of electrical testing probe points 16-2 arranges that along the opposite side of testing element 10 its pad 34 with soi structure 20 is related.Also show input test optical fiber 40 (and output optical fibre a 42) array that separates in this view.Known as semiconductor applications, when carrying out wafer level test, testing element is taken to carefully with wafer to be contacted, thereby the end of a plurality of test points (test point 16 in this example) just contacts related pad (pad 34 in these accompanying drawings), thereby does not disturb the physical characteristics of wafer.A plurality of test pads of test probe points 16 are used for providing electric input test signal to soi structure 20, and remaining test probe points 16 is used for coupling output electric test signal.One exemplary means of photo structure and " monolithic electronics " has been shown among Fig. 3, and it is included in the soi structure 20, and owing to use photoelectricity test element 10 formed according to the present invention, therefore simultaneously tested.
Light in the chip/electricity (O/E) detecting device 62 (preferably being integrated in the soi structure 20) or mixed electrical optical element can be used for monitoring the light probe signal and produced to beam steering/shaping optical device 12 and/feedback signal of light source, with " tuning " test wavelength, improve and be coupled, reorientate one or more beam steering element etc.The electrical output signal of selected O/E detecting device also can be directed into one or more electric welding contacts 34 in O/E detecting device 62, and offers selected test probe points in the test probe points 16 as electricity output test signal.An aspect of of the present present invention is, owing to convert " opticator " test signal to electrical representation, can eliminate the needs for light output probe.The ability of the feedback that the ability on single testing element is considered to have promoted greatly to provide so in real time with optics and electrical testing unit construction.
As mentioned above, one group of grating can replace prism coupler, is used to provide coupling.Fig. 4 illustrates exemplary embodiment of the present invention, and wherein a pair of grating 50 and 52 is used to replace prism coupler 30,32 so that optically-coupled to be provided.In embodiment shown in Figure 4, input grating 50 forms in the input coupling regime of soi structure 20.Use such optical grating construction at length to discuss in the common unsettled sequence number of applicant is 10/935,146 application with the ability of the effective coupling in the sub-micron layer that is provided to soi layer 26 for example, it is quoted and is incorporated herein for your guidance above.In fact, input grating 50 can be directly forms in soi layer 26, can form in the part of coupling layer 28 declining to die, or in the embodiment that presents " overloading (poly-loaded) " waveguiding structure, forms in the polysilicon layer of stack.
On general, use according to coupling of the present invention/uncoupling prism or grating allows photoelectricity test element 10 to be arranged on any suitable position of SOI wafer, and carry out " non-intrusion type " optical tests (for example compare with the Johannessen reference of prior art, it need remove a part of overlayer and possible ducting layer to realize optically-coupled).In addition,, therefore realize wafer level test easily, and " edge " (or the small pieces of each separation) that do not need to visit wafer are carried out optical tests according to the present invention owing to directly the optical tests signal is coupled to the surperficial soi layer of photoelectric circuit.In a word, can with mode like the conventional wafer level electricity integrated circuit test class, carry out photoelectricity test with testing element of the present invention at wafer level.
For the optical tests of a complete set is provided, necessary is, the wafer in the test can move and/or rotates with respect to testing element, and some move and are used to test originally on one's body alignment situation of SOI wafer in the case.Fig. 5 illustrates the exemplary SOI wafer 200 (soi structure 20 that comprises aforesaid a plurality of separation) that is installed on the multiaxis platform (stage) 100, wherein platform 100 allows the x-y translation motion of wafer 200 with respect to photoelectricity test element 10, and rotatablely move (θ) between wafer 200 and the testing element 10, it is indicated by arrow in Fig. 5.During the initial setting of proving installation, the main angle that rotatablely moves to proofread and correct testing element 10 relative SOI wafers 200 of using is unjustified.During stepping and repetitive process, wafer 200 with respect to testing element 10 " on "/D score motion allows aliging again of testing element and each soi structure 20.That is, platform 100 reduces to leave probe, moves to next die location, raises then to contact with testing element 10 once more.By comprising vision system and known image processing algorithm, but the robotization whole test process.
At Fig. 5 whole testing device 120 is shown also, it comprises bus interface 122, is used for computer control 124 is connected to picture system 126 and instrument 128, and it is used to carry out/control the light and the electrical testing of the various expectations on the soi structure in the SOI wafer 200.What be also connected to bus 122 is electrical interface 130 and optical interface 132, and it is used for providing electricity and light input test signal to testing element 10, and the response signal of self-test element 10.
As shown, each input control signal (position and (some) the optical tests wavelength that comprises testing element 10, beam steering element) and input test signal (light and) along bus 122 by and be applied to photoelectricity test element 10 or multiaxis platform 100.Also 122 transmission longitudinally and being stored in suitable diagnosis/test memory cells in the computer control 124 of the test signal of returning (light and).Based on the test result of reality and the value that is stored in the association in the computer control 124 " can accept ", use special testing algorithm can assess each soi structure, the structure by some test is not marked as " unacceptable ".For example, the surperficial available line of unacceptable parts is on one's body visual indicator originally, magnetic ink for example, and mark, thus when wafer cuts into separate part, can abandon the circuit of " by ".
The response signal value of the essence of each test, input signal, expectation etc. does not think with theme of the present invention substantial connection is arranged, and theme of the present invention is intended to the formation and the use of monochromatic light electrical testing element, to carry out the basic all wafers level test of photoelectricity wafer.In addition, to be considered to only be exemplary for above-mentioned specific embodiments of the invention.Under situation about not breaking away from by the scope of the present invention that claim limited that provides hereinafter, those skilled in the art can carry out the change of many forms and details.
Claims (26)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US55131604P | 2004-03-08 | 2004-03-08 | |
| US60/551,316 | 2004-03-08 | ||
| US11/075,430 | 2005-03-08 |
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| CN1965240A CN1965240A (en) | 2007-05-16 |
| CN100570386C true CN100570386C (en) | 2009-12-16 |
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| CN 200580011617 Expired - Fee Related CN100570386C (en) | 2004-03-08 | 2005-03-08 | Wafer-level optoelectronic testing apparatus and method |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI362717B (en) * | 2005-10-18 | 2012-04-21 | Gsi Group Corp | Methods for alignment utilizing an optical reference |
| JP5811273B2 (en) * | 2012-03-30 | 2015-11-11 | 富士通株式会社 | Optical element, optical transmitter element, optical receiver element, hybrid laser, optical transmitter |
| US10027116B2 (en) * | 2014-09-11 | 2018-07-17 | Cpg Technologies, Llc | Adaptation of polyphase waveguide probes |
| JP6726295B2 (en) * | 2016-10-27 | 2020-07-22 | 三井化学東セロ株式会社 | Electronic device manufacturing method, electronic device manufacturing adhesive film, and electronic component testing device |
| JP7107094B2 (en) | 2018-08-23 | 2022-07-27 | 富士通オプティカルコンポーネンツ株式会社 | Optical device and optical transceiver module |
| US11243230B2 (en) * | 2019-12-30 | 2022-02-08 | Juniper Networks, Inc. | Compact opto-electric probe |
| CN113848213A (en) * | 2020-06-28 | 2021-12-28 | 宁波飞芯电子科技有限公司 | Wafer test system and method |
| CN113960441B (en) * | 2020-07-21 | 2025-07-15 | 中兴光电子技术有限公司 | Silicon photonic chip automated testing system, method, electronic device and storage medium |
| CN117203536B (en) * | 2021-04-16 | 2024-06-07 | 业纳光学系统有限公司 | Wafer level testing method for photoelectric chip |
| CN117538984B (en) * | 2024-01-09 | 2024-08-16 | 赛丽科技(苏州)有限公司 | Integrated photonic chip, array and testing method thereof |
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| CN1189244A (en) * | 1995-06-30 | 1998-07-29 | 西门子微电子公司 | Monolithic linear optocoupler fabrication method |
| GB2332775A (en) * | 1997-12-23 | 1999-06-30 | Lsi Logic Corp | Testing optical/electronic integrated circuits |
| US6577148B1 (en) * | 1994-08-31 | 2003-06-10 | Motorola, Inc. | Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer |
| US6686993B1 (en) * | 2001-03-05 | 2004-02-03 | Analog Devices, Inc. | Probe card for testing optical micro electromechanical system devices at wafer level |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6577148B1 (en) * | 1994-08-31 | 2003-06-10 | Motorola, Inc. | Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer |
| CN1189244A (en) * | 1995-06-30 | 1998-07-29 | 西门子微电子公司 | Monolithic linear optocoupler fabrication method |
| GB2332775A (en) * | 1997-12-23 | 1999-06-30 | Lsi Logic Corp | Testing optical/electronic integrated circuits |
| US6686993B1 (en) * | 2001-03-05 | 2004-02-03 | Analog Devices, Inc. | Probe card for testing optical micro electromechanical system devices at wafer level |
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