CN100568916C - Display controller of picture frame base phase locking and method thereof - Google Patents

Abstract

A display controller and method for a picture frame based phase lock in a display system. The display controller is used for displaying a plurality of image frames in a video signal and comprises a frame-based phase-locked loop and a synchronous signal generator, wherein the frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal and generates an output clock signal by utilizing the frame-based phase-locked loop. The synchronous signal generator receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enabling signal. The frame-based phase-locked loop includes a fast phase detector, a phase frequency detector, and an active pixel area generator. The effective pixel area generator receives an input vertical synchronous signal to generate a reference signal related to the effective pixel area, and the frame-based phase-locked loop locks the display enabling signal to the reference signal.

Description

Frame-based phase-locked display controller and method

【Technical field】

The present invention relates to a display controller and its method, in particular to a frame-based phase-locked display controller and its method.

【Background technique】

1 shows a block diagram of an existing television (television, TV) system, including a television controller 100, a dynamic random access memory (dynamic random access memory, DRAM) 120 and a cathode ray tube (cathode ray tube, CRT) 140, The television controller 100 is used to receive various video signal sources 110, including the display modes of the International Television Standards Committee (National Television Standards Committee, NTSC), Phase Alternation Line (PAL), and super extended graphics arrays (super extended graphics) array, SXGA)/extended graphics array (Extended Graphics Array, XGA)/video graphics array (video graphics array, VGA) video signal. The DRAM 120 must first store the frame data (frame data) produced by the video signal source, and then utilize the TV controller 110 to display the frame data stored in the DRAM to the CRT 140 on the screen. The cathode ray tube 140 displays video signals according to vertical synchronous (vertical synchronous, VSYNC) and horizontal synchronous (horizontal synchronous, HSYNC) signals (not shown) generated by the television controller 100 .

However, the DRAM 120 increases the manufacturing cost of the display system; moreover, the cathode ray tube 140 cannot dynamically change the vertical synchronization signal and the horizontal synchronization signal, and the vertical synchronization signal and the horizontal synchronization signal can only be within a specific range according to the manufacturer's specifications. Generally speaking, the variation range of the vertical synchronous signal cannot exceed 5%, and the horizontal synchronous signal cannot exceed 2%, otherwise the cathode ray tube 140 will be damaged or the display screen will be distorted. The vertical synchronous signal frequencies of NTSC and PAL display modes are 60Hz (hertz) and 50Hz respectively, while SXVGA/XGA/VGA video signals support vertical synchronous signal frequencies ranging from 60Hz to 85Hz.

In the prior art, the TV controller 100 temporarily stores the frame data in the DRAM to isolate the input frame data and the output frame data from each other. Therefore, the output video signal composed of the output frame data can only be stably displayed by the control of the vertical synchronization and horizontal synchronization signals with almost fixed frequency. When different video signal sources are input into the TV controller 100 or when the display mode is changed, the TV controller 100 may cause the video signal displayed on the cathode ray tube to be distorted due to the drastic change of the vertical synchronizing signal or the horizontal synchronizing signal, Even cause damage to the cathode ray tube 140 .

FIG. 2 shows a block diagram of the conventional TV controller in FIG. 1 , including an output phase-locked loop (PLL) 200 and a horizontal and vertical (HV) signal generator 220 . The output PLL 200 receives a fixed input clock signal 210 and then outputs an output clock signal (Output_CLK), and the HV signal generator generates vertical sync and horizontal sync signals according to the output clock signal. Traditional display controllers process image frames in units of pixels. Those familiar with the art would consider CRT television to be impractical without DRAM 120, because without DRAM 120, when the input television signal source changes, the output vertical sync signal It must change drastically, thus causing the destruction of the cathode ray tube or distortion of the video display. However, the damage to the cathode ray tube and the distortion of the signal are unacceptable to the manufacturer of the display system, and it is very dangerous when the cathode ray tube TV is damaged.

As mentioned above, for the controller of a cathode ray tube or a liquid crystal display device, the traditional phase-locked loop receives a fixed input clock signal, and cannot provide a variety of video signal switching requirements without dynamic random access memory. , and the DRAM increases the manufacturing cost of the display system.

【Content of invention】

The main purpose of the present invention is to provide a frame-based phase-locked display controller and its method, to detect the phase difference between the reference signal and the display enable (display enable, DE) signal, to reduce different types of TV The cost of external memory in the system.

Another object of the present invention is to provide a frame-based phase-locked display controller and method to adjust the frequency and phase of the output vertical and horizontal synchronous signals on a frame basis to respond to changes in different display modes under a predetermined video signal source Or the phase difference caused by the change of different video signal sources.

To achieve the above-mentioned purpose, the present invention proposes a frame-based display controller for displaying several image frames in a video signal, including a frame-based phase-locked loop and a synchronous signal generator. The frame-based phase-locked loop is used for receiving the oscillating signal and the input vertical synchronization signal, and generating an output clock signal based on the image frame. The synchronous signal generator is connected to the aforementioned phase-locked loop to receive the aforementioned output clock signal and generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enabling signal. The frame-based phase-locked loop mainly includes a first phase-locked loop, a frequency synthesizer, a second phase-locked loop, a fast phase detector, a phase-frequency detector and an effective pixel region generator. The active pixel area generator receives an input vertical synchronization signal to generate a reference signal associated with the active pixel area. The frame-based phase-locked loop forms a phase-locked state between the display enabling signal and the reference signal according to the image frame.

The invention provides a frame-based phase-locking method, which mainly includes the following steps: generating an output clock signal according to an oscillating signal; receiving an input vertical synchronization signal; generating a reference signal associated with an effective pixel area according to the input vertical synchronization signal; The clock signal generates an output horizontal synchronous signal, an output vertical synchronous signal, and an output display enable signal; and then performs the steps of phase-locked loop according to several image frames.

Preferably, by detecting the phase difference between the reference signal and the display enable signal, and converting the phase difference into an up/down count signal; synthesizing an output clock signal based on the up/down count signal and an oscillation signal; according to the aforementioned phase The aforementioned output horizontal synchronization signal and the aforementioned output vertical synchronization signal are differentially adjusted. In the step of performing the phase-locked loop, the display enabling signal and the reference signal are adaptively phase-locked according to the image frame. The output vertical sync signal is correlated to the input vertical sync signal by a small amplitude relationship.

In a specific embodiment, the output vertical synchronization signal is adaptively approached to the input vertical synchronization signal in response to a display mode change or a video signal source change, and the relationship and reference between the display enable signal and the output vertical synchronization signal The relationship between the signal and the incoming vertical sync signal is programmable. When the distance between the output vertical synchronous signal and the input vertical synchronous signal exceeds the total capacity of several linear buffers in the display controller, the output vertical synchronous signal approaches the input vertical synchronous signal adaptively. Simultaneously, when the distance between the output vertical sync signal and the input vertical sync exceeds the total capacity of the line buffer, the stable signal is deasserted to temporarily disable the display controller display output.

The step of generating the output clock signal is to clamp the frequency of the output clock signal, and each assertion of the output horizontal sync signal is related to a complete scan line. The step of generating the output horizontal synchronous signal includes the following steps: counting the horizontal count value to generate the output horizontal synchronous signal; and counting the vertical count value to generate the output vertical synchronous signal. The adaptive adjustment step is to correct the horizontal count value and the vertical count value, and quickly adjust the horizontal sync signal and the vertical sync signal in response to the phase difference.

The present invention effectively reduces the cost of using an external memory storage device in a cathode ray tube television system by adjusting the phase difference between a reference signal and a display enabling signal according to different types of video signal sources or changes in display modes.

【Description of drawings】

Figure 1 is a block diagram of a prior art television system.

FIG. 2 shows a block diagram of the conventional TV controller in FIG. 1 .

FIG. 3 is a block diagram of the basic architecture of a low-cost display controller with a frame-based PLL according to an embodiment of the present invention.

FIG. 4 is a detailed architectural block diagram of the display controller with frame-based PLL shown in FIG. 3 according to the present invention.

FIG. 5 is a timing waveform diagram related to the input vertical synchronization signal and the adjustment of the vertical synchronization signal according to an embodiment of the invention.

FIG. 6 is a flow chart of performing frame-based phase locking according to an embodiment of the present invention.

FIG. 7 is a flow chart of performing frame-based phase locking in another embodiment of the present invention.

【Detailed ways】

The present invention provides a frame-based phase-locked display controller and method, using a fast phase detector and a phase frequency detector to detect the phase difference between a reference signal and a display enable (DE) signal to save time The cost of using external memory (such as dynamic random access memory) in different types of television systems, including cathode ray tube televisions and LCD televisions. The frame-based phase-locked loop adjusts the frequency of the vertical and horizontal synchronization signals according to the phase difference and uses the compensation synchronization signal generator to respond to the change of the display mode of the predetermined video signal or the switching of different video signal sources (CRT TV or LCD TV ). In addition, the effective pixel area generator detects the input vertical synchronous signal of the television to generate a reference signal associated with the effective pixel area of the video signal source, so that the output vertical synchronous signal generated by the synchronous signal generator catches up with the input vertical synchronous signal . It should be noted that the video signal can be, for example, SXGA, XGA, VGA, HDTV, NTSC, PAL standard specifications and any other kind of television signal.

FIG. 3 shows a novel architectural block diagram of a low-cost display controller with a frame-based PLL 300 according to an embodiment of the present invention to save the cost of DRAM. An input vertical synchronous signal (input vertical synchronous signal, IVSYNC) 302 is isolated from an output vertical synchronous signal (VSYNC) 304 by using a frame-based PLL 300 . The frame-based phase-locked loop 300 clamps the frequency of the output clock signal (Output_CLK) 306, so the vertical sync signal 304 maintains a weak (weak) correlation with the input vertical sync signal 302; the sync signal generator 320 generates a vertical sync signal according to the output clock signal 306 Synchronization signal (VSYNC) 304 and horizontal synchronization signal (HSYNC) 308 . The output clock signal 306 can be appropriately frequency-clamped according to the setting of the manufacturer to avoid damage to the display, especially to avoid damage to the cathode ray tube. The display enable (DE) signal 310 of the synchronous signal generator 320 is also fed back to the FIG. Frame-based phase-locked loop 300 . In this specific embodiment, the frequency of the output clock signal 306 is appropriately changed without changing the phase of the vertical synchronization signal too drastically, so the frame-based PLL 300 can effectively save dynamic random access memory components, and Effectively protects the TV from being damaged by the vertical sync signal 304, the vertical sync signal 304 and the horizontal sync signal 308 can be adaptively adjusted to respond to the incoming vertical sync signal, such as a vertical sync signal change, under the manufacturer's specifications The range is within 5% and the horizontal sync signal is within 2%.

Fig. 4 is a detailed structural block diagram of the display controller with the frame-based phase-locked loop 300 shown in Fig. 3 according to the present invention, the display controller with the frame-based phase-locked loop 300 is used to display several image images in the video signal The frame mainly includes an effective pixel area generator 400 , a fast phase detector 440 , a frequency synthesizer 410 , a synchronization signal generator 320 and a phase frequency detector (phase frequency detector, PFD) 450 . In this embodiment, the phase frequency detector 450 is disposed on the feedback path and coupled between the synchronization signal generator 320 and the frequency synthesizer 410 .

The effective pixel area generator 400 generates a reference signal 444 associated with the effective pixel area of the video signal according to the detected input vertical synchronous signal 302. Those skilled in the art should understand that there is a difference between the reference signal 444 and the input vertical synchronous signal 302. The relevance of the can be adjusted programmatically. The phase frequency detector 450 is connected to the effective pixel region generator 400 for detecting the phase difference between the reference signal 444 and the display enable signal 310 and converting the phase difference into an up/down count signal. The frequency synthesizer 410 performs frequency synthesis according to the up/down count signal from the phase frequency detector 450 and the output signal of the first phase-locked loop 405 .

The synchronous signal generator 320 is respectively connected to the fast phase detector 440, the phase frequency detector 450 and the second phase-locked loop 420 of the frame-based phase-locked loop 300, so that according to the output clock signal of the frame-based phase-locked loop 300 306 generates horizontal sync signal 308 , vertical sync signal 304 and display enable signal 310 . The display enable signal 310 is fed back to the fast phase detector 440 to track the reference signal 444 of the active pixel area generator 400, which indicates the active output pixel area of the display system. The sync signal generator 320 feeds the display enable signal to the fast phase detector 440 and the phase frequency detector 450 . Those skilled in the art should understand that the relationship between the display enable signal 310 and the vertical synchronization signal 304 can be adjusted programmatically, and is essentially related to display specifications. Therefore, when the video signal source or the display mode changes, the vertical synchronous signal 304 generated by the synchronous signal generator 320 is weakly correlated with the input vertical signal 302 of the effective pixel region generator 400 .

In a preferred embodiment of the present invention, the sync signal generator 320 mainly includes a horizontal counter 446 and a vertical counter 448 . The horizontal counter 446 counts the first default value of the high level of each output horizontal synchronous signal, and the vertical counter 446 counts the second default value of the high level of each output vertical synchronous signal, and the count value can represent the duration of the signal. The relationship between the display enabling signal 310 and the vertical synchronizing signal 304 can be adjusted programmatically to substantially meet the display specifications of a CRT television.

The fast phase detector 440 is connected to the effective pixel area generator 400, the phase frequency detector 450 and the synchronous signal generator 320, and the fast phase detector 440 detects the phase difference between the reference signal 444 and the display enabling signal 310 , to generate a control signal 442 and a compensation signal 452 . The fast phase detector 440 compensates the synchronous signal generator 320 through the compensation signal 452, and adjusts the phase difference between the input vertical synchronous signal 302 and the vertical synchronous signal 304, so as to rapidly input the vertical synchronous signal 302 and the vertical synchronous signal according to the reference signal 444 304 phase locking; for example, when the phase difference between the input vertical synchronous signal 302 and the vertical synchronous signal 304 exceeds a predetermined value, the fast phase detector 440 sends a signal to the synchronous signal generator so that each picture frame compensates ten Horizontal sync line; preferably, when the fast phase detector 440 uses the compensation signal 452 to compensate the sync signal generator 320 , the fast phase detector 440 disables the phase frequency detector 450 via the control signal 442 .

Further, the first phase-locked loop 405 connected to the frequency synthesizer 410 is used to receive the oscillation signal from the oscillator, the second phase-locked loop 420 is arranged between the frequency synthesizer 410 and the synchronous signal generator 320, the first The phase-locked loop 405 generates an output frequency lower than the output clock signal 306 of the frame-based phase-locked loop 300, which can improve the anti-electromagnetic interference capability of the display system.

When the frequency of the output clock signal 306 exceeds a predetermined change value, the effective pixel area generator 400 can isolate the input vertical synchronous signal 302 and the vertical synchronous signal 304 to protect the cathode ray tube; The loop 300 can be free-run without the effective pixel area generator 400, for example, a cathode ray tube can ignore the input vertical synchronization signal 302 and display a blue picture.

Continuing to refer to FIG. 4 , the phase frequency detector 450 detects the phase difference between the input vertical sync signal 304 and the vertical sync signal 302 , and is disposed on the feedback path of the sync signal generator 320 . The phase frequency detector 450 adjusts the frequency and phase of the output clock signal 306 to adjust the vertical sync signal 304 , the horizontal sync signal 308 and the display enable signal 310 . The frame-based phase-locked loop 300 adaptively adjusts the frequency and phase of the vertical synchronization signal 304 and the horizontal synchronization signal 308 by compensating the synchronization signal generator to respond to switching or switching of different video signal sources output to a cathode ray tube or an LCD TV. Phase difference caused by display mode change of the same video signal source.

When the display mode of the display system changes, the phase difference between the vertical synchronous signal 304 and the input vertical synchronous signal 302, such as the phase difference of 100 scan lines of the horizontal synchronous signal 308, cannot be allowed by the traditional TV controller without dynamic The random access memory changes 100 scan lines of the horizontal sync signal 308, whereas in the present invention, the phase frequency detector 450 tracks the phase changes exponentially. The fast phase detector 440 enables or disables the phase frequency detector 450 through a control signal 442 , and the compensation signal 452 generated by the fast phase detector 440 is sent to the sync signal generator 320 to compensate the horizontal sync signal 308 .

When the vertical sync signal 304 exceeds a predetermined phase difference threshold (threshold), the fast phase detector 440 sends a signal to the sync signal generator 320 to digitally compensate several horizontal sync signal scanning lines for each frame, for example There are 10 scanning lines; preferably, when the fast phase detector 440 is adjusting the synchronization signal generator 320 , the fast phase detector 440 disables the phase frequency detector 450 through the control signal 442 . Therefore, when the display mode is changed, the stabilization time required by the frame-based PLL 300 can be greatly reduced to meet the display specification of the display system.

In a specific embodiment, when the display mode of the cathode ray tube is changed to operate in the SXGA display mode with 1280*1024 resolution at 60Hz, the cathode ray tube displays 60 frames per second and each frame contains 1024 scan line. The sync signal generator 320 generates the horizontal sync signal 308 and the vertical sync signal 304 according to the horizontal counter 446 and the vertical counter 448 respectively. Preferably, when the phase difference exceeds the display specification, the fast phase detector 440 sends a signal to the synchronous signal generator 320 to compensate the horizontal synchronous counter 446, for example, modify the count value in the horizontal counter 446 for horizontal scanning Line compensation, and the associated line buffers (not shown) in the display controller are thus affected.

Preferably, each assertion of the horizontal synchronization signal is associated with a complete scan line. For details, please refer to US Patent Application No. 10/908,473 filed on May 13, 2005 by the applicant.

FIG. 5 is a timing waveform diagram related to the adjustment of the input vertical sync signal 302 and the vertical sync signal 304 according to an embodiment of the invention. The input vertical sync signal 302 is directly associated with the input video signal, that is, the input frame of the video signal is associated with the input vertical signal 302 . When the display mode changes, a phase difference of n scanning lines is initially generated between the vertical synchronous signal 304 and the input vertical synchronous signal 302, and the stable signal is deasserted (deassert) and the frame output is disabled; the vertical synchronous signal 304 goes through The incoming vertical sync signal 302 is adaptively caught up after several horizontal sync signal assertions. For example, after more than 40 periods of the input vertical sync signal, the phase difference between the input vertical sync signal 302 and the vertical sync signal 304 is narrowed without damaging the CRT or causing image distortion. After the vertical sync signal 304 catches up with the input vertical sync signal 302, the stable signal is asserted to enable the output frame. Preferably, when the phase difference between the input vertical sync signal 302 and the vertical sync signal 304 exceeds the total capacity of the linear buffer, the stable signal is deasserted to temporarily disable the display output of the display controller, so that the user You will not see any picture distortion.

Therefore, the vertical sync signal 304 remains weakly correlated with the input vertical sync signal 302 . After the vertical sync signal 304 approaches the input vertical sync signal 302 , the vertical sync signal 304 does not need to be completely aligned with the input vertical sync signal 302 . The above embodiment shows that the display enable signal 310 is close to the reference signal 444 , and the display enable signal 310 does not need to be completely aligned with the reference signal 444 . Preferably, the display enable signal 310 catches up with the reference signal 444 within the range of the number of linear buffers integrated in the low cost display controller, asserting the stable signal causes the CRT to display the picture normally; for example, if Five linear buffers are integrated in the low-cost display controller. When the display enable signal 310 catches up with the reference signal 444 within the range of the five linear buffers, the stable signal is asserted so that the cathode ray tube can display images normally, and avoid Displays the problem of underrun or overrun of frame data in the system. In other words, during the adjustment process, the vertical sync signal 304 is quickly adjusted using the horizontal counter 446 and the vertical counter 448 so that the vertical sync signal 304 and the input vertical sync signal 302 maintain a slight correlation. More importantly, the fast phase detector 440 and the phase frequency detector 450 perform frame-based phase locking on the vertical sync signal 304 and the input vertical sync signal 302 with high performance and adaptively.

FIG. 6 is a flowchart of frame-based phase locking according to an embodiment of the present invention. Firstly, in step S600, a reference signal is generated by detecting the input vertical synchronous signal of the input video signal, and the reference signal is related to the input vertical synchronous signal. Then in step S602, a phase frequency detector is used to detect the phase difference between the reference signal and the display enable signal, and convert the phase difference into an up/down count signal. Then in step S604, the output clock signal is synthesized according to the frequency of the up/down count signal.

Then, in step S606, the horizontal synchronization signal, the vertical synchronization signal and the display enable signal are adaptively adjusted in response to the phase difference between the input vertical synchronization signal and the vertical synchronization signal. In this embodiment, the horizontal synchronization signal, the vertical synchronization signal and the display enable signal are generated according to the aforementioned output clock signal. The display enabling signal used for displaying the effective output pixel area is sent to the fast phase detector, so that the display enabling signal is close to the reference signal of the effective pixel area generator. The fast phase detector detects the phase difference between the reference signal and the display enable signal to generate a control signal and a compensation signal; the control signal selectively enables the phase detector according to a predetermined threshold value to control the upper The output of the /down count signal, and the compensation signal compensates the synchronous signal generator according to the phase difference between the input vertical synchronous signal and the vertical synchronous signal, so as to adjust the horizontal synchronous signal, the vertical synchronous signal and the display enabling signal adaptively, so that the vertical The sync signal quickly approaches the input vertical sync signal according to the reference signal. Preferably, when the fast phase detector sends a compensating signal to compensate the synchronous signal generator, the control signal of the fast phase detector disables the phase frequency detector to stop operation. Preferably, the horizontal count value and the vertical count value are counted according to the output clock signal, and the horizontal synchronization signal, the vertical synchronization signal and the display enable signal are adaptively adjusted in response to the phase difference between the input vertical synchronization signal and the vertical synchronization signal .

Please refer to FIG. 7 , which is a flow chart of executing frame-based phase locking according to another embodiment of the present invention. First in step S700, an output clock signal is generated according to the oscillating signal; in step S702, an input vertical synchronization signal is received; in step S704, a reference signal related to the effective pixel area is generated according to the input vertical synchronization signal; in step S706, according to The output clock signal generates an output horizontal synchronization signal, an output vertical synchronization signal, and an output display enable signal; finally in step S708, a phase-locked loop is performed based on a plurality of image frames.

More specifically, the phase difference between the reference signal and the display enable signal is detected and converted into an up/down count signal, and the output clock signal is synthesized to respond to the up/down count signal and the oscillation signal frequency, according to the phase difference adaptability The horizontal synchronization signal and the vertical synchronization signal are adjusted accordingly. In the aforementioned steps of executing the phase-locked loop, the display enable signal is adaptively phase-locked to the reference signal according to several image frames, so that the output vertical synchronization signal is different from the input vertical synchronization signal. There is a slight correlation between them.

The output vertical sync signal is adaptively approximated to the input vertical sync signal in response to a change in display mode or a change in video signal source. Preferably, the relationship between the display enable signal and the output vertical synchronization signal and the relationship between the reference signal and the input vertical synchronization signal are programmable. When the distance between the output vertical synchronization signal and the input vertical synchronization signal exceeds the total capacity of several linear buffers in the display controller, the vertical synchronization signal approaches the input vertical synchronization signal adaptively. Preferably, the stable signal is deasserted to temporarily disable the display controller display output when the distance between the output vertical sync signal and the input vertical sync signal exceeds the total capacity of the line buffer.

The step of generating the output clock signal clamps the frequency of the output clock signal, and each assertion of the output horizontal sync signal is associated with a complete scan line. The step of generating the output horizontal synchronous signal includes the following steps: counting a horizontal count value to generate the output horizontal synchronous signal; counting a vertical count value to generate the output vertical synchronous signal. The adaptive adjustment step modifies the horizontal count value and the vertical count value, and quickly adjusts the horizontal sync signal and the vertical sync signal in response to the phase difference.

In general, the present invention discloses a frame-based phase-locked display controller to display several image frames in a video signal. The display controller includes a frame-based phase-locked loop and a synchronous signal generator, and the frame-based lock The phase loop receives an oscillating signal and an input vertical synchronous signal to generate a frame-based output clock signal, and the synchronous signal generator is connected to the frame-based phase-locked loop to receive the output clock signal to generate an output horizontal synchronous signal, output Vertical synchronization signal and display enable signal.

Preferably, the frame-based phase-locked loop includes a first phase-locked loop, a frequency synthesizer, a second phase-locked loop, a fast phase detector, a phase-frequency detector and an effective pixel area generator. The active pixel area generator receives an input vertical synchronization signal to generate a reference signal associated with the active pixel area. The frame-based PLL adaptively phase-locks the display enable signal to the reference signal based on the image frame.

The invention adaptively adjusts the phase difference between the input vertical synchronous signal and the output vertical synchronous signal to respond to the change of different video signal sources or display modes, and can save the cost of using external memory in the cathode ray tube television.

Claims (30)

1. frame-based phase-locked display controller is used for showing some image frames of a vision signal, and aforementioned phase-locked display controller comprises frame-based phase-locked loop and is connected in the sync generator of this frame-based phase-locked loop; It is characterized in that: aforementioned frame-based phase-locked loop is for based on the picture frame pattern, and it is in order to receive an oscillator signal and an input vertical synchronizing signal, to produce a clock signal based on aforementioned image frame; Aforementioned frame-based phase-locked loop more comprises an active pixel region generator, the reference signal that aforementioned frame-based phase-locked loop utilizes an aforementioned active pixel region generator and an input vertical synchronizing signal that receives to be associated with an effective pixel area with generation; Aforementioned sync generator receives aforementioned clock signal, shows enable signal to produce an output horizontal-drive signal, an output vertical synchronizing signal and an output; Aforementioned frame-based phase-locked loop is in order to receive from the described output enable signal of aforementioned sync generator with from the reference signal of active pixel region generator, and obtain aforementioned enable signal and above-mentioned reference phase difference between signals, so that aforementioned frame-based phase-locked loop utilizes aforementioned phase difference and aforementioned image frame that aforementioned demonstration enable signal adaptability is phase-locked to the above-mentioned reference signal.

2. display controller as claimed in claim 1 is characterized in that: the aforementioned output vertical synchronizing signal of aforementioned sync generator is to concern a little with one to be associated in aforementioned input vertical synchronizing signal.

3. display controller as claimed in claim 1 is characterized in that: aforementioned output vertical synchronizing signal is the aforementioned input vertical synchronizing signal of convergence adaptively, with the variation in response to a display mode.

4. display controller as claimed in claim 1 is characterized in that: when aforementioned video signal conversion during to another vision signal, aforementioned output vertical synchronizing signal is the aforementioned input vertical synchronizing signal of convergence adaptively.

5. display controller as claimed in claim 1, it is characterized in that: when the phase difference between aforementioned output vertical synchronizing signal and the aforementioned input vertical synchronizing signal surpassed the total capacity of the some line style buffers in the aforementioned display controller, aforementioned output vertical synchronizing signal leveled off to aforementioned input vertical synchronizing signal adaptively.

6. display controller as claimed in claim 1 is characterized in that: aforementioned frame-based phase-locked loop more comprises:

One phase frequency detector is used to detect the phase difference between above-mentioned reference signal and the aforementioned demonstration enable signal, and aforementioned phase difference is converted on one/following count signal;

One first phase-locked loop is used to receive aforementioned oscillator signal;

One frequency synthesizer is connected in aforementioned first phase-locked loop, is used to receive aforementioned/following count signal; And

One second phase-locked loop is connected in aforementioned frequency synthesizer, to produce aforementioned clock signal.

7. display controller as claimed in claim 6 is characterized in that: the frequency of the aforementioned clock signal of the aforementioned second phase-locked loop strangulation.

8. as display controller as described in the claim 6, it is characterized in that: aforementioned frame-based phase-locked loop more comprises a fast phase detector, with the aforementioned phase difference between detecting above-mentioned reference signal and the aforementioned demonstration enable signal, adjust aforementioned sync generator to produce a compensating signal.

9. display controller as claimed in claim 8 is characterized in that: when aforementioned fast phase detector is adjusted aforementioned sync generator, utilize the aforementioned phase frequency detector of a control signal forbidden energy.

10. display controller as claimed in claim 8 is characterized in that: aforementioned vision signal meets a standard specification that is selected from super extension drawing array (SXGA) vision signal, extends the group that drawing array (XGA) vision signal, visual graphic array (VGA) vision signal, hd-tv (HDTV) vision signal, international television standard committee (NTSC) display mode and phase cross-over line (PAL) display mode form.

11. display controller as claimed in claim 8 is characterized in that: the pass between aforementioned demonstration enable signal and the aforementioned output vertical synchronizing signal is a programmable.

12. display controller as claimed in claim 8 is characterized in that: aforementioned demonstration enable signal is in order to show aforementioned effective pixel area.

13. display controller as claimed in claim 8 is characterized in that: each of aforementioned output horizontal-drive signal is asserted and is relevant to a complete scan line.

14. display controller as claimed in claim 8 is characterized in that: aforementioned sync generator comprises:

One horizontal counter is used to count a level value to produce aforementioned output horizontal-drive signal; And

One vertical counter is used to count a vertical value to produce aforementioned output vertical synchronizing signal.

15. display controller as claimed in claim 14 is characterized in that: aforementioned sync generator is according to aforementioned compensating signal correction aforementioned levels value and aforementioned vertical value.

16. display controller as claimed in claim 1 is characterized in that: aforementioned display controller is to show aforementioned image frame on the display unit of a cathode ray tube.

17. a frame-based phase-lock technique that is used for the some image frames of a vision signal comprises the steps:

Produce a clock signal according to an oscillator signal;

Receive an input vertical synchronizing signal;

Produce a reference signal related according to aforementioned input vertical synchronizing signal with an effective pixel area;

Produce an output horizontal-drive signal, an output vertical synchronizing signal and an output according to aforementioned clock signal and show enable signal; And

According to aforementioned enable signal and above-mentioned reference phase difference between signals and aforementioned some image frames, that aforementioned demonstration enable signal and above-mentioned reference signal adaptive is phase-locked.

18. frame-based phase-lock technique as claimed in claim 17 is characterized in that: the phase-locked step of this adaptability comprises:

Phase difference between detecting above-mentioned reference signal and the aforementioned demonstration enable signal, and aforementioned phase difference converted on one/following count signal; And

According on aforementioned/the synthetic aforementioned clock signal of following count signal and aforementioned oscillator signal.

19. frame-based phase-lock technique as claimed in claim 18 more comprises: the Hou of the phase-locked step of this adaptability, according to the step of aforementioned output horizontal-drive signal of aforementioned phase difference accommodation and aforementioned output vertical synchronizing signal.

20. frame-based phase-lock technique as claimed in claim 17 is characterized in that: aforementioned output vertical synchronizing signal is to concern a little with one to be associated in aforementioned input vertical synchronizing signal.

21. frame-based phase-lock technique as claimed in claim 17 is characterized in that: aforementioned output vertical synchronizing signal levels off to aforementioned input vertical synchronizing signal adaptively, to change in response to a display mode or a video signal source changes.

22. frame-based phase-lock technique as claimed in claim 17 is characterized in that: the pass between aforementioned demonstration enable signal and the aforementioned output vertical synchronizing signal is a programmable.

23. frame-based phase-lock technique as claimed in claim 17 is characterized in that: the pass between above-mentioned reference signal and the aforementioned input vertical synchronizing signal is a programmable.

24. frame-based phase-lock technique as claimed in claim 17 is characterized in that: the frequency of the aforementioned clock signal of step strangulation of aforementioned generation clock signal.

25. frame-based phase-lock technique as claimed in claim 17 is characterized in that: each of aforementioned output horizontal-drive signal is asserted and is relevant to a complete scan line.

26. frame-based phase-lock technique as claimed in claim 17, it is characterized in that: when the phase difference between the vertical synchronizing signal surpassed the total capacity of the some line style buffers in the display controller when aforementioned output vertical synchronizing signal and input, aforementioned output vertical synchronizing signal leveled off to aforementioned input vertical synchronizing signal adaptively.

27. frame-based phase-lock technique as claimed in claim 26, it is characterized in that: when the phase difference between aforementioned output vertical synchronizing signal and the aforementioned input vertical synchronizing signal surpassed the total capacity of the some line style buffers in the display controller, releasing was asserted a stabilization signal and is temporarily made aforementioned display controller can't demonstrate aforementioned image frame.

28. frame-based phase-lock technique as claimed in claim 19 is characterized in that: aforementioned phase difference surpasses a predetermined valve limit value.

29. frame-based phase-lock technique as claimed in claim 19 is characterized in that: produce the output horizontal-drive signal and comprise the steps: with the output vertical synchronizing signal

Count a leveler numerical value to produce the output horizontal-drive signal; And

Count a vertimeter numerical value to produce the output vertical synchronizing signal.

30. frame-based phase-lock technique as claimed in claim 29, it is characterized in that: the step correction aforementioned levels count value and the aforementioned vertimeter numerical value of aforementioned accommodation output horizontal-drive signal and aforementioned output vertical synchronizing signal, with aforementioned output horizontal-drive signal of rapid adjustment and aforementioned output vertical synchronizing signal, with in response to aforementioned phase difference.

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