CN100568382C - FIFO memory - Google Patents

Abstract

The invention provides a first-in first-out memory, comprising: a buffer unit including a plurality of cells for storing data; and the output control circuit reads the data stored in the buffer unit according to a reading pointer and a reading byte number. The output control circuit includes: a selection signal generating module for generating a plurality of selection signals according to the reading pointer and the reading byte number; and a data output module, reading the data of the corresponding cell from the buffer unit according to the plurality of selection signals and the reading pointer, and outputting the data as the output data of the first-in first-out memory. The first-in first-out memory greatly reduces the load of a reading pointer and a writing pointer, avoids using a complex driving circuit, thereby reducing the complexity of a control circuit and the number of transmission gates, and has relatively smaller area and higher data transmission speed.

Description

FIFO memory

technical field

The present invention relates to a first-in-first-out memory, in particular to a high-speed first-in-first-out memory (First In First Out, FIFO).

Background technique

FIG. 1 shows a first-in-first-out memory (First In First Out, FIFO) with four inputs and four outputs in the prior art. The FIFO memory 100 can be applied to transmit data between a central processing unit (Central Processing Unit, CPU) and a North Bridge (North Bridge). The FIFO memory 100 has four multiplexers (Mux) 111, 112, 113, 114, 141, 142, 143, and 144, registers 121, 122, 123, and 124, and sixteen multiplexers 131, 132 , 133 and 134. Among them, the registers 121 , 122 , 123 and 124 are first-in first-out registers capable of storing 16 sets of 32-bit data.

The input data Data0 , Data1 , Data2 and Data3 are stored in the corresponding positions of the temporary registers 121 , 122 , 123 and 124 through the four-way multiplexers 111 , 112 , 113 and 114 . Sixteen-way multiplexers 131 , 132 , 133 and 134 receive temporary data from registers 121 , 122 , 123 and 124 and output to four-way multiplexers 141 , 142 , 143 and 144 .

As can be seen from Fig. 1, since the four-way multiplexer 111, 112, 113 and 114 must have the driving ability to drive the temporary registers 121, 122, 123 and 124 that store 16 groups of 32 bits, that is, it must pass the write pointer Push selects the storage units used to store data Data0-Data3 from 64 32-bit storage units, which makes the load of writing pointer Push very heavy. Therefore, the four-way multiplexers 111, 112, 113, and 114 need larger drivers, thereby increasing the circuit complexity and the number of transmission gates of the four-way multiplexers 111, 112, 113, and 114, and because the number of transmission gates is large, Data transfers are also slower. Similarly, at the output end of the FIFO memory 100, the data stored in the temporary registers 121-124 need to pass through two stages of multiplexers, that is, sixteen-way multiplexers 131-134 and four-way multiplexers 141-144 In order to output in a first-in first-out manner, the complexity of the circuit increases and the data transmission speed decreases.

Contents of the invention

The object of the present invention is to provide a high-speed first-in-first-out memory.

The present invention provides a first-in-first-out memory, comprising: a buffer unit, including a plurality of cells for storing data; an input control circuit, according to a write pointer and a write byte number, to store received data input into the buffer unit; and an output control circuit for reading the data stored in the buffer unit according to a read pointer and a read byte number. The input control circuit includes: a cell selection module, which activates the cells to be used to store data according to the write pointer and the number of bytes to be written; and a sorting module, which activates the cell according to the write pointer Store the received data into the activated cell. The output control circuit includes: a selection signal generation module, which generates a plurality of selection signals according to the read pointer and the number of read bytes; and a data output module, which reads from the buffer unit according to the plurality of selection signals multiple data with consecutive storage addresses, and select and output the output data of the first-in-first-out memory from the multiple data with consecutive storage addresses according to the read pointer.

The first-in-first-out memory described in the present invention uses a shift register to generate a cell corresponding to the data to be stored or output, thus greatly reducing the load on the read pointer and write pointer, and avoiding the use of complex drive circuits, thereby Reduced control circuit complexity and the number of transmission gates. Due to the small number of transmission gates, the FIFO memory of the present invention has relatively small area and high data transmission speed.

Description of drawings

The above and other objects and features of the present invention will become more apparent through the following description in conjunction with the accompanying drawings exemplarily showing an example, wherein:

FIG. 1 is a schematic diagram of a prior art four-input four-output FIFO memory;

2 is a schematic diagram of a first-in-first-out memory according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an input control circuit of the FIFO memory shown in FIG. 2;

FIG. 4 is a schematic diagram of an output control circuit of the first-in-first-out memory shown in FIG. 2;

FIG. 5 is a detailed schematic diagram of the output control circuit of the FIFO memory shown in FIG. 4;

6a-6c are detailed schematic diagrams of the selection logic shown in FIG. 5 .

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

As shown in FIG. 2 , a first-in-first-out memory (First In First Out, FIFO) 200 according to an embodiment of the present invention includes: a control unit 20, a buffer unit 23, an input control circuit 21, and an output control circuit 22. Assume that the first-in-first-out memory 200 in this embodiment can support a maximum of 4 data writes with a length of 32 bits per cycle, and a maximum of 4 data outputs with a length of 32 bits. In this embodiment, the control unit 20 is configured to output a write pointer Push and a write byte number Push_valid of the buffer unit 23 to the input control circuit 21 according to the received transmission request request, and a read pointer Pop and a read Get the byte number Pop_valid to the output control circuit 22 . In this embodiment, the control unit 20 is disposed in the FIFO memory 200 , but it is not limited thereto. As known to those skilled in the art, the write pointer Push points to the storage address of the next cell of the buffer unit 23 that can store data, and the read pointer Pop is used to point to the storage of the next cell of the buffer unit 23 that can be read. address. Assume that both the number of bytes written, Push_valid, and the number of bytes read, Pop_valid, include 4 bits, which are used to indicate the length of data to be written and the length of data to be read. For example, if the number of written bytes Push_valid is 4'b0001, then a length of 1DW (ie 32bit) data is stored in the buffer unit 23; if the number of written bytes Push_valid is 4'b0011, then two The data of 1DW is stored in buffer unit 23; if the number of written bytes Push_valid is 4'b0111, then three 1DW data are stored in buffer unit 23; if the number of written bytes Push_valid is 4'b1111, then four 1DW of data is stored in the buffer unit 23 . The transfer request received by the control unit 20 may be a read or write request from the CPU.

The input control circuit 21 stores the received data datain0 - datain3 into corresponding cells of the FIFO buffer unit 23 according to the write pointer Push and the write byte number Push_valid. Further, the input control circuit 21 includes a cell selection module 216 and a sorting module 210 . The cell selection module 216 generates at most four cell enable signals act_1 - act_4 according to the write pointer Push and the write byte number Push_valid to activate the cells in the FIFO buffer unit 23 to be used for storing data. The sorting module 210 stores the received data datain0-datain3 into the cells activated by the cell enable signals act1-act4 in a first-in-first-out manner according to the write pointer Push, thereby completing the data storage operation.

The output control circuit 22 reads and outputs the data dataout0 - dataout3 from the FIFO buffer unit 23 according to the read pointer Pop and the read byte number Pop_valid. In this embodiment, the output control circuit 22 includes a data output module 224 and a selection signal generation module 225 . The selection signal generation module 225 is composed of a multiplexer 220 and a shift register group 221 . The multiplexer 220 generates a read row shift signal R_shift according to the received read pointer Pop and the read byte number Pop_valid. The shift register group 221 outputs a plurality of selection signals, namely RPtr_0˜RPtr_a, under the control of the read row shift signal R_shift. The data output module 224 selects and outputs the data of the corresponding cell from the first-in-first-out buffer unit 23 according to multiple selection signals RPtr_0-RPtr_a, and further selects and outputs four data dataout0-dataout3 as the first-in-first-out memory 200 according to the read pointer Pop output.

The following will describe how the input control circuit 21 stores the received data into the buffer unit 23 according to the write pointer Push and the write byte count Push_valid in this embodiment in conjunction with FIG. 3 . Assume that the input control circuit 21 needs to put four pieces of data datain0 - datain3 with a length of 1DW into the buffer unit 23 in a first-in first-out manner.

As shown in FIG. 3 , the buffer unit 23 in this embodiment is composed of four first-in first-out sub-storage blocks bank1-bank4, and each sub-storage block bank1-bank4 has a data width of 1DW and a depth of 96. That is to say, each sub-storage block bank1-bank4 includes 96 cells with a width of 1DW, namely cells cell1_0-cell1_95, cells cell2_0-cell2_95, cells cell3_0-cell3_95 and cells cell4_0-cell4_95. Therefore, the buffer unit 23 in this embodiment can also be regarded as a memory with 96 rows×4 columns and totally 384 cells with a width of 1DW. The addresses of the cells 1_n to 4_n in the nth (n=0, 1...95) row of the sub-storage blocks bank1 to bank4 are continuous, and the cell 1_n+1 and the cell 1_n+1 in the n+1th row are The addresses of the cells 4_n in n rows are consecutive, so the data received by the FIFO memory 200 is stored in the cells of the sub-memory blocks bank1 - bank4 in a serpentine manner through the input control circuit 21 . For the convenience of understanding, datan_n will be used to represent the data stored in the cell celln_n in the description and drawings of this embodiment. For example, the data stored in the cell cell1_30 is data1_30.

The input control circuit 21 includes multiplexers 210 , 211 , a first shift register 212 , a second shift register 213 , a cell preselection module 214 and a clock control module 215 . The multiplexer 210 outputs the received data datain0-datain3 to the corresponding sub-storage blocks bank1-bank4 according to the corresponding relationship shown in Table 1 according to the lower two bits of the write pointer Push, namely Push[1:0]. Among them, the sub-storage block bank1 is used to store the data whose lower two bits of the address are "00", the sub-storage block bank2 is used to store the data whose lower two bits of the address are "01", and the sub-storage block bank3 is used to store the lower two bits of the address. The data whose two bits are "10" and the sub-storage block bank4 are used to store the data whose lower two bits are "11".

Table 1

Push[1:0] datain0 datain1 datain2 datain3 00 bank1 bank2 bank3 bank4 01 bank2 bank3 bank4 bank1

10 bank3 bank4 bank1 bank2 11 bank4 bank1 bank2 bank3

For example, if the write pointer Push=8'b010100101, the data datain0 will be stored in the sub-storage block bank2, the data datain1 will be stored in the sub-storage block bank3, the data datain2 will be stored in the sub-storage block bank4, and the data datain3 will be stored in the sub-storage block Block bank1. In other words, in this embodiment, the input control circuit 21 can determine the corresponding relationship between the data datain0-datain3 and the sub-storage blocks bank1-bank4 through the multiplexer 210, that is, determine which column of the buffer unit 23 the received data will be respectively stored in. .

The multiplexer 211 generates a write row shift signal W_shift according to the write byte number Push_valid[3:0] and the write pointer Push[1:0] to control the first shift register 212, the second shift register Shift of register 213. The first shift register 212 includes 96 bits, which are sequentially shifted under the control of the write row shift signal W_shift, and output a first row selection signal wptr_0[95:0], whose 96 bits correspond to the sub memory block bank1 respectively 96 cells of ~bank4, and only one bit is "1". The second shift register 213 also includes 96 bits, and outputs a second row selection signal wptr_1[95:0] under the control of the write-in row shift signal W_shift, and its 96 bits correspond to sub-storage blocks bank1-bank4 respectively. 96 cells, and only one bit is "1". In particular, the initial value of the first row selection signal wptr_0 is wptr_0[0], that is, bit0 is "1", corresponding to the cell in the first row of the buffer unit 23, and the initial value of the second row selection signal wptr_1 is wptr_1[1], that is, bit1 is “1”, corresponds to the cell in the second row of the buffer unit 23 . The multiplexer 211 judges whether the data to be received can be completely stored in the current first and second row selections according to the received write pointer Push[1:0] and the number of written bytes Push_valid[3:0] In the cells corresponding to the signals wptr_0 and wptr_1, if not possible, the row shift signal W_shift is output, so that the first shift register 212 and the second shift register 213 are shifted to pass the first and second row selection signals wptr_0 , wptr_1 preselects two rows (8) of cells. For example, after the first data is stored, if the write row shift signal W_shift received by the first shift register 212 and the second shift register 213 is enabled, the first shift register 212 outputs the first One row selection signal is changed from wptr_0[0] to wptr_0[1], and the second shift register 213 outputs the second row selection signal from wptr_1[1] to wptr_1[2], that is, the second row and Row 3 cell.

The cell preselection module 214 is then based on the write pointer Push[1:0], the number of written bytes Push_valid[3:0] and the first row selection signal wptr_0[n] and the second row selection signal wptr_1[n+1] , according to the correspondence shown in Table 2-Table 5, output the cell pointers addr_1-addr_4 of the corresponding sub-storage blocks bank1-bank4, so as to further select the cell to be used to store data from the pre-selected two rows of cells.

Table 2: (Push_valid=4'b1111)

Push[1:0] addr_1 addr_2 addr_3 addr_4 00 wptr_0[n] wptr_0[n] wptr_0[n] wptr_0[n] 01 wptr_1[n+1] wptr_0[n] wptr_0[n] wptr_0[n] 10 wptr_1[n+1] wptr_1[n+1] wptr_0[n] wptr_0[n] 11 wptr_1[n+1] wptr_1[n+1] wptr_1[n+1] wptr_0[n]

Table 3: (Push_valid=4'b0111)

Push[1:0] addr_1 addr_2 addr_3 addr_4 00 wptr_0[n] wptr_0[n] wptr_0[n] 0 01 0 wptr_0[n] wptr_0[n] wptr_0[n] 10 wptr_1[n+1] 0 wptr_0[n] wptr_0[n] 11 wptr_1[n+1] wptr_1[n+1] 0 wptr_0[n]

Table 4: (Push_valid=4'b0011)

Push[1:0] addr_1 addr_2 addr_3 addr_4 00 wptr_0[n] wptr_0[n] 0 0 01 0 wptr_0[n] wptr_0[n] 0 10 0 0 wptr_0[n] wptr_0[n] 11 wptr_1[n+1] 0 0 wptr_0[n]

Table 5: (Push_valid=4'b0001)

Push[1:0] addr_1 addr_2 addr_3 addr_4 00 wptr_0[n] 0 0 0 01 0 wptr_0[n] 0 0 10 0 0 wptr_0[n] 0 11 0 0 0 wptr_0[n]

For example, as shown in Table 2, assume that the cell preselection module 214 receives the write pointer Push whose lower two bits are "01", the number of written bytes Push_valid=4'b1111, the first row selection signal wptr_0[41 ] and the second row selection signal wptr_1[42], then the cell preselection module 214 outputs the cell pointer addr_1[42], addr_2[41], addr_3[41], addr_4[41], indicating that its value is "1" The bits correspond to the cell cell1_42 of the sub-storage block bank1, and the cells cell2_41, cell3_41 and cell4_41 of the sub-storage blocks bank2-bank4, and these cells will be used to store the data received in this transmission cycle (cycle).

In order to save power, the cell pointers addr_1 ˜ addr_4 output by the cell preselection module 214 are sent to the clock control module 215 . The clock control module 215 outputs four enable signals act_1~act_4 to each cell of the buffer unit 23 according to the system clock CLK, so that the cells that will be used to store data, that is, the enable signals act_1~act_4 in the sub memory blocks bank1~bank4 The cell corresponding to the bit whose act_4 value is "1" is activated (a clock signal is provided to the cell).

As can be seen from the above description, at the input end of the FIFO memory 200 in this embodiment, two rows of cells are selected from the buffer unit 23 according to the first row selection signal wptr_0 and the second row selection signal wptr_1, that is, eight consecutive addresses Cell, and then select the cell that will be used to store data from the two rows of cells through the cell preselection module 214. The clock control module 215 activates the selected cells, so that the multiplexer 210 sequentially stores the received data datain0-datain3 into the activated cells.

Apparently, compared with the prior art, the input control circuit 21 of the FIFO memory 200 in this embodiment uses a relatively simple circuit such as a shift register to generate the corresponding The enable signals act1 - act_4 of each cell of the buffer unit 23 effectively reduce the load of the write pointer Push and the write byte count Push_valid. Since there is no need to design a circuit with a large driving force in this embodiment to drive the write pointer Push to select the cell to be used to store data from the 384 cells according to the number of bytes to be written Push_valid, the present embodiment advances The data storage efficiency of the memory 200 is effectively improved.

The following will describe how the output control circuit 22 reads data from the buffer unit 23 according to the read pointer Pop and the read byte count Pop_valid in this embodiment in conjunction with FIG. 4 .

As shown in FIG. 4 , the output control circuit 22 includes a multiplexer 220 , shift registers 0 ˜ a and a data output module 224 . The shift registers 0 to a constitute the shift register group 221 . The data output module 224 includes a cell preliminary selection module 226 and a multiplexer 223 composed of processing units 2261 - 2264 .

The multiplexer 220 outputs a read row shift signal R_shift according to the lower three bits of the read pointer Pop and the read byte number Pop_valid to control shifting of the shift registers 0˜a. Shift registers 0-a respectively output a selection signal RPtr_0-RPtr_a according to the row shift signal R_shift, each selection signal RPtr_0-RPtr_a contains 48 bits, and at the same time each selection signal RPtr_0-RPtr_a has only one bit as " 1". The cell preliminary selection module 226 selects 11 cells with continuous addresses from the corresponding sub-storage blocks bank1-bank4 of the buffer unit 23 according to the selection signals RPtr_0-RPtr_a, and outputs the data stored in the selected cells to Multiplexer 223. The multiplexer 223 selects and outputs 4 data dataout0 - dataout3 from the 11 data initially selected according to the read pointer Pop, as the output of the FIFO memory 200 .

Furthermore, in order to reduce the load of the selection signals RPtr_0 - RPtr_a, the data stored in the cells of each of the sub-memory blocks bank1 - bank3 are divided into two groups when output to the corresponding processing units 2261 - 2264 . Among them, the first group of data is composed of data stored in odd-numbered row cells, and the second group of data is composed of data stored in even-numbered row cells, so each group contains 48 data, and they correspond to corresponding selection signals 48 bits of RPtr_0 to RPtr_a. For the convenience of description, the first group of data output by the sub-storage blocks bank1-bank4 are respectively marked by group1_1, group2_1, group3_1 and group4_1, and the second group of data are respectively marked by group1_2, group2_2, group3_2 and group4_2. For example, the first group of data group1_1 output by the sub-storage unit bank1 is composed of the data stored in the cells cell1_0, cell1_2, cell1_4...cell1_94, that is, the data data1_0, data1_2...data1_94 ( FIG. 6 a ), the second group of data group1_2 is composed of data stored in cells cell1_1, cell1_3, cell1_5...cell1_95, namely data data1_1, data1_3...data1_95 (FIG. 6b). In this embodiment, the processing units 2261-2263 also receive a third group of data, namely data group1_3, group2_3 and group3_3. As shown in the figure, the data output module 224 includes sequencer units 2271-2273, which are used to sequence the first group of data group1_1, group2_1 and group3_1 output by the corresponding sub-storage blocks bank1-bank3 to obtain the third group of data group1_3, group2_3 and group3_3. Furthermore, in this embodiment, the ordering units 2271-2273 are a circular right-shift shift register, which can perform a right-shift operation on the received data, so as to achieve the purpose of adjusting the order of the data. For example, assuming that the first group of data group1_1 output by the sub-storage block bank 1 is composed of data data1_0, data1_2...data1_94, and the arrangement order is data1_94, data1_92...data1_2, data1_0, after the sequence After the cyclic right shift operation of the unit 2271, the arrangement order of the data becomes data1_0, data1_94...data1_4, data1_2 (FIG. 6c). In short, taking the processing unit 2261 as an example, the third group of data group1_3 received by the processing unit 2261 is obtained by right-shifting the first group of data group1_1. The processing units 2261 - 2264 then select 11 pieces of data from the data groups group1_1 - group4_1, group1_2 - group4_2 and group1_3 - group3_3 according to the selection signals RPtr_0 - RPtr_a, and output them to the multiplexer 223 through the signals cell_out0 - cell_outa. The multiplexer 223 selects and outputs four data dataout0-dataout3 from the data cell_out0-cell_outa according to the lower three bits of the read pointer Pop as the output data of the FIFO memory 200 of this embodiment.

Please refer to FIG. 4 to FIG. 6 together. The processing units 2261-2264 each include a plurality of processing logics con0-cona for selecting 11 addresses from the corresponding sub-memory blocks bank1-bank4 according to the corresponding selection signals RPtr_0-RPtr_a Data output stored in consecutive cells. Please refer to FIGS. 6 a - 6 c , taking selection logic 0 - 2 as an example to illustrate how to select 11 cells with consecutive addresses from the buffer unit 23 by selecting logic 0 - a in this embodiment. Selection logic 0 includes 48 AND gates AN0-47 and one OR gate OR0. The AND gates AN0-47 all have two input ends, one end is connected to the first data group1_1 of the sub memory block bank1, namely data data1_0, data1_2...data1_94, and the other end is connected to the selection signal RPtr_0[47:0 ] for the corresponding bit. As known to those skilled in the art, through the AND gates AN0-47, the data corresponding to 1'b1 in the selection signal RPtr_0 will be sent to the OR gate OR0 and output as data cell_out0. The structure of selection logic 1 and selection logic 2 is the same as that of selection logic 0, except that the 48 bits of the selection signal RPtr_1 correspond to the second group of data group_2, that is, the data data1_1, data1_3...data1_95, and the 48 bits of the selection signal RPtr_2 The ones digit corresponds to the third group of data group1_3, namely data data1_2, data1_4...data1_94, data1_0. . Therefore, assuming that shift registers 0~2 output selection signals RPtr_0[20]~RPtr_2[20] respectively, the data cell_out0~cell_out2 output by selection logic 0~2 are the data stored in cells cell1_40, cell1_41 and cell1_42 respectively, that is Data data1_40, data1_41 and data1_42. In other words, the selection logic 0-2 selects three cells from the sub-bank bank1 according to the received selection signals 0-2, and outputs the data stored therein through cell_out0-cell_out2. Similar to selection logic 0-2, selection logic 3-5 respectively selects three cells from the sub-memory block bank2 according to selection signals RPtr_3-RPtr_5, and outputs the data stored therein through cell_out3-cell_out5. The selection logics 6-8 select three cells from the sub-memory block bank3 respectively according to the selection signals RPtr_6-RPtr_8, and output the stored data through cell_out6-cell_out8. The selection logic 9-a respectively selects two cells from the sub-memory block bank4 according to the selection signals RPtr_9-RPtr_a, and outputs the stored data through cell_out9-cell_outa.

It can be known from the above description that in this embodiment, the output control circuit 22 can control the corresponding selection logic 0-a to select 11 cells with consecutive addresses from the buffer unit 23 according to the selection signals 0-a, and the signals cell_out0-cell_outa will The data output in these 11 cells. For example, assuming that shift registers 0~a respectively output selection signals RPtr_0[20]~RPtr_a[20], the data cell_out0~cell_outa output by selection logic 0~a are cells cell1_40~cell4_40, cell1_41~cell4_41, cell1_42~ The data stored in cell3_42. The multiplexer 223 then selects and outputs four data dataout0-dataout3 from the data cell_out0-cell_outa according to the lower three bits of the read pointer Pop. The multiplexer 220 judges whether the data to be read has been output to the multiplexer 223 by the selection logic con0～cona according to the read pointer Pop and the number of read bytes Pop_valid, if not, then outputs the read line shift signal R_shift, so that The selection logics con0 -cona select 11 pieces of data according to the shifted selection signals RPtr_0 -RPtr_a and output them to the multiplexer 223 .

In this embodiment, the output control circuit 22 generates a set of selection signals RPtr_0 - RPtr_a through a set of shift registers, ie shift registers 0 - a, so that the selection logics con0 - cona output a set of data cell_out0 - cell_outa with continuous addresses. Therefore, compared with the prior art, the output control circuit 22 of the present invention only needs to drive the read pointer Pop to select 4 data from 11 consecutive data addresses as the output data of the FIFO memory 200, thereby greatly reducing the Reading the load of the pointer Pop effectively improves the data output efficiency of the FIFO memory 200 in this embodiment.

The above descriptions all assume that the first-in-first-out memory 200 in this embodiment can support at most 4 data writes with a length of 32 bits per cycle, and at most 4 data outputs with a length of 32 bits. However, as known to those skilled in the art, The above assumptions can be changed according to different application environments, and the structures of the input/output control circuit and the buffer unit only need to be changed simply. For example, if the buffer unit 23 is composed of 32 cells with a bit width of 32 bits, the multiplexer 220 of the output control circuit 22 can read the number of bytes Pop_valid[3:0] and the read pointer Pop[1 :0] Strictly read the row shift signal R_shift. The number of shift registers can be reduced from 11 to 8 accordingly. At this time, each sub-storage block bank1-bank4 contains 8 cells, among which the cells of odd-numbered rows are divided into one group, and the cells of even-numbered rows are divided into another group, and are respectively output to corresponding processing units 2261-2264 . The shift registers 0 - 7 respectively output selection signals RPtr_0 - RPtr_7 according to the read row shift signal R_shift, and each selection signal RPtr_0 - RPtr_7 includes 4 bits. The processing units 2261-2264 then select and output two rows from the buffer unit 23 according to the selection signals RPtr_0-RPtr_7, and a total of 8 cells with continuous addresses are used for the multiplexer 223 to select according to the read pointer Pop[1:0] The data dataout0 to dataout3 are sequentially output.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

Claims (13)

1. A first-in-first-out memory, characterized in that, comprising: A buffer unit, including a plurality of cells for storing data; An input control circuit stores received data into the buffer unit according to a write pointer and a number of bytes to be written, and the input control circuit includes: A cell selection module activates the cell to be used to store data according to the write pointer and the number of bytes to be written; and a sorting module, storing the received data into the activated cell according to the write pointer; and An output control circuit for reading the data stored in the buffer unit according to a read pointer and a read byte number, the output control circuit includes: A selection signal generation module, which generates multiple selection signals according to the read pointer and the number of read bytes; and A data output module, which reads a plurality of data with continuous storage addresses from the buffer unit according to the plurality of selection signals, and selects and outputs the data from the data with continuous storage addresses according to the read pointer. Output data from FIFO memory. 2. The FIFO memory according to claim 1, wherein the selection signal generating module of the output control circuit comprises: a first multiplexer, generating a read row shift signal according to the read pointer and the read byte number; and A shift register group outputs the multiple selection signals according to the read row shift signal. 3. The FIFO memory according to claim 2, wherein the first multiplexer judges whether the data to be read is stored in the In the cell corresponding to the selection signal, if not, output the read row shift signal, so that the shift register group outputs a shifted selection signal. 4. The FIFO memory according to claim 1, wherein the data output module of the output control circuit comprises: A cell primary selection module, respectively according to the corresponding selection signal, selects and outputs the data of the corresponding cell from the buffer unit; and A second multiplexer, receiving the data output by the primary cell selection module, and selecting a plurality of data as the output data output of the first-in-first-out memory according to the read pointer; Wherein, the storage addresses of the data output by the cell primary selection module are continuous. 5. The first-in-first-out memory according to claim 4, wherein the cell primary selection module includes a plurality of selection logics, and selects and outputs the data of the corresponding cell from the buffer unit according to the corresponding selection signal respectively . 6. The first-in-first-out memory according to claim 5, wherein the data output module further comprises a sequencing unit, coupled between the buffer unit and the selection logic, for adjusting the buffer unit The sort order of the data output to the selection logic. 7. The FIFO memory according to claim 4, wherein the number of selection signals of the output control circuit is equal to the number of selection logics. 8. The FIFO memory according to claim 1, wherein the cell selection module comprises: A third multiplexer, generating a write row shift signal according to the write pointer and the write byte number; The first shift register and the second shift register respectively output a first row selection signal and a second row selection signal according to the written row shift signal; and A cell preselection module, which generates a plurality of cell pointers according to the first row selection signal, the second row selection signal, the write pointer and the number of bytes to be written, respectively pointing to the cells to be used for storing data of cells. 9. The first-in-first-out memory according to claim 8, wherein the cell selection module further comprises a clock control module for giving corresponding The cell provides the clock signal. 10. The first-in-first-out memory according to claim 8, wherein the sorting module includes a fourth multiplexer, storing a plurality of data received by the first-in-first-out memory according to the write pointer into the cell pointed to by the cell pointer, and store the first data received by the FIFO memory into the cell corresponding to the write pointer. 11. The first-in-first-out memory according to claim 8, wherein the first row selection signal and the second row selection signal each comprise a plurality of bits, and the second row selection signal is "1" The bit is one bit higher than the bit at which the first row selection signal is "1". 12. The first-in-first-out memory according to claim 11, wherein the third multiplexer judges whether all the data to be written can be stored in the In the cell corresponding to the first row selection signal and the second row selection signal, and output the write row shift signal according to the judgment result, so that the first shift register and the second shift register shift . 13. The first-in-first-out memory according to claim 1, wherein the cells of the buffer unit comprise multiple rows and multiple columns, and the storage addresses of the cells of the same row of the buffer unit are continuous, two adjacent The storage address of the last cell of the previous row in the row is consecutive to the storage address of the first cell of the next row.

Images