CN100562863C - Interrupt processing device and method in chip - Google Patents
Interrupt processing device and method in chip Download PDFInfo
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- CN100562863C CN100562863C CNB2004101040515A CN200410104051A CN100562863C CN 100562863 C CN100562863 C CN 100562863C CN B2004101040515 A CNB2004101040515 A CN B2004101040515A CN 200410104051 A CN200410104051 A CN 200410104051A CN 100562863 C CN100562863 C CN 100562863C
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Abstract
本发明公开了一种芯片内的中断处理装置及方法，以解决现有技术在处理芯片的中断过程中会有某些中断被忽略掉的问题。该中断处理装置包括中断产生单元、中断向量存储单元和控制输出单元，中断产生单元内具有多个功能模块；功能模块将中断信号分别输入到中断向量存储单元和控制输出单元，芯片的上位机收到中断请求信号后，读取中断向量存储单元后执行读取到的中断，在执行中断的同时，若有新产生的中断，则读取中断向量存储单元，执行相应的中断，若没有新产生的中断，则退出。采用本发明进行中断处理时，所有产生的中断都能够被处理，不会出现某些中断被忽略掉的问题。
The invention discloses an interrupt processing device and method in a chip to solve the problem in the prior art that some interrupts are ignored in the process of processing chip interrupts. The interrupt processing device includes an interrupt generating unit, an interrupt vector storage unit, and a control output unit. The interrupt generating unit has multiple functional modules; the functional modules input interrupt signals to the interrupt vector storage unit and the control output unit respectively, and the host computer of the chip After receiving the interrupt request signal, read the interrupt vector storage unit and execute the read interrupt. While executing the interrupt, if there is a new interrupt, read the interrupt vector storage unit and execute the corresponding interrupt. If there is no new interrupt interrupt, exit. When the present invention is used for interrupt processing, all generated interrupts can be processed without the problem that some interrupts are ignored.
Description
Technical field
Treating apparatus that the present invention relates to interrupt and method relate in particular to the Interrupt Process device and method in a kind of chip.
Background technology
In a chip, may have many interrupt sources, and chip to distribute to the pin of interruption be limited, chip piece has only an interrupt pin usually.
As shown in Figure 1, the Interrupt Process device that is used in the prior art in the chip comprises that one interrupts importation 1, is used to import a plurality of interruptions; An interruptable controller 2 is used for from interrupting importation 1 interruption of selecting a limit priority of output being arranged; And an interrupt handler 3, be used to handle the interruption of on interruptable controller 2, selecting.
In the Interrupt Process device of Fig. 1, when a new interruption is input in the interruption importation 1, the priority of interrupt handled on the priority of interrupt of input newly and the interrupt handler 3 is compared, if the priority of interrupt of new input is not higher than the priority of interrupt of handling on the interrupt handler 3, then continue the current interruption of handling; If the priority of interrupt of new input is higher than the priority of interrupt of handling on the interrupt handler 3, then stop current ongoing interruption, interruption priority is higher by interruptable controller 2 outputs to interrupt handler 3, is handled by interrupt handler 3.
When the priority of interrupt of handling on the priority of interrupt of new generation and the interrupt handler 3 is identical, interruptable controller 2 outputs to interrupt handler 3 according to the sequencing that interrupts producing with interruption, the interruption that produces earlier will at first obtain handling, when handling this interruption, the interruption of other equal priority will be left in the basket, if when the interruption of several equal priority produces simultaneously, can only have an interruption processed, other interruption also will be left in the basket.
The shortcoming of above-mentioned interruption processing method is: when interrupting processor in handling interrupt, the interruption of the equal priority of other new generations will be left in the basket; When the interruption of several equal priority produces simultaneously, can only there be an interruption processed, other interruption will be left in the basket.Some interrupts just can not get handling like this, must handle if the interruption that neglects is a chip, will the function of chip be impacted.
Summary of the invention
The object of the present invention is to provide the Interrupt Process device and method in a kind of chip, when solving the underway disconnected processing of prior art, the problem that some interruption will be left in the basket.
For addressing the above problem, the invention provides following technical scheme:
Interrupt Process device in a kind of chip comprises:
Interrupt generating unit is used to produce look-at-me;
The interrupt vector storage unit is used to store the interrupt vector that interrupt generating unit produces;
The control output unit is used for interrupt generating unit and produces when interrupting, and sends interrupt request singal;
Have a plurality of functional modules in the interrupt generating unit, wherein the look-at-me of each functional module is imported control output unit and interrupt vector storage unit respectively.
Described interrupt vector storage unit is for reading zero clearing formula register, and the look-at-me of each functional module is input in the interior corresponding position of register.
Described control output unit is or door, or the output terminal of door is connected with the host computer of chip.
Described interrupt vector storage unit is connected with the host computer of chip.
A kind of interruption processing method comprises step:
Produce the functional module of interrupting in A, the interrupt generating unit look-at-me is input to interrupt vector storage unit and control output unit respectively;
The host computer of B, chip reads the interrupt vector storage unit by interrupt service routine, carries out the interruption that reads;
C, when interrupt service routine carry out to interrupt, if there is new interruption to produce, then repeated execution of steps A, B if there is not new interruption to produce, after interrupt service routine is finished, withdraw from.
In described step C, interrupt service routine is carried out the interruption that reads in proper order or is carried out the interruption that reads according to predefined interrupt priority level.
Because the present invention has adopted above technical scheme, so have following beneficial effect:
Interrupt Process device of the present invention can all be noted all interrupt vectors, interrupt service routine by host computer decides which interrupt vector of execution, priority of interrupt judged by interrupt service routine, also can all interrupt vectors are handled by the host computer order.When adopting the present invention to carry out Interrupt Process, the interruption of all generations can both be processed, the problem that some interruption is left in the basket can not occur.
Description of drawings
Fig. 1 is for being used for the structural representation of the Interrupt Process device in the chip in the prior art;
Fig. 2 is for being divided into chip the synoptic diagram of different stage module;
Fig. 3 is the schematic diagram of Interrupt Process device of the present invention;
Fig. 4 is the structural representation of Interrupt Process device of the present invention;
Fig. 5 is the process flow diagram of interruption processing method of the present invention.
Embodiment
As shown in Figure 2, in the chip design process, chip can be divided into a lot of one-level modules, each one-level module is made up of some secondary modules again, comprises littler module in the secondary module again.Like this entire chip is divided into a lot of levels.In the present invention, chip can be counted as a module, has a total Interrupt Process device corresponding with it, all corresponding Interrupt Process device of each module in the chip, and each Interrupt Process device all has an interrupt signal output.The look-at-me of each one-level module output is that one-level is interrupted, and with all one-level look-at-me lines or constitute the interruption output pin of total Interrupt Process device together, interrupt request singal is sent to the host computer of chip by interrupting output pin.Each one-level module is made up of many secondary modules, each one-level module all has an one-level Interrupt Process device corresponding with it, interrupt the same with one-level, secondary look-at-me line in each one-level module also all or together constitutes the interruption output pin of one-level Interrupt Process device, this interrupts output pin and is connected with the host computer of chip, its working method is identical with total Interrupt Process device, by that analogy, produces multistage Interrupt Process mode.
The structure of the Interrupt Process device of different stage is identical in the chip, and as shown in Figure 3, Interrupt Process device of the present invention comprises: an interrupt generating unit is used to produce the look-at-me of a plurality of functional modules of same rank; An interrupt vector storage unit is used to store the interrupt vector that interrupt generating unit produces; A control output unit is used for interrupt generating unit and produces when interrupting, and sends interrupt request singal; Have a plurality of functional modules in the interrupt generating unit, wherein the look-at-me of each functional module is imported control output unit and interrupt vector storage unit respectively.
As shown in Figure 4, above-mentioned interrupt vector storage unit is connected with the host computer of chip, for reading the register of zero clearing formula, in this interrupt vector register each is all corresponding with a functional module in the interrupt generating unit, and the look-at-me of each functional module is input in the interior corresponding position of interrupt vector register.Above-mentioned control output unit be one or, or the output terminal of door is connected with the host computer of chip, the look-at-me line of all functions module or together constituted the interruption output pin of this Interrupt Process device.
As shown in Figure 5, when a plurality of functional modules in the interrupt generating unit produce interruption, come the interruption of process chip according to the methods below.
In above-mentioned Interrupt Process device, when the functional module in the interrupt generating unit produce to be interrupted, the interrupt signal output line of functional module respectively high level signal is input to or door and interrupt vector register in corresponding with it that.Interrupt high level signal of output pin output and give the host computer of chip, the host computer of chip reads interrupt vector register by interrupt service routine after receiving this high level signal, all interrupt vectors are noted, when some position of finding interrupt vector register changes, can conclude that is which module produces interruption, because interrupt vector register is the design of reading zero clearing, therefore after running through all interrupt vector registers, all interrupt vector registers are zero.
Interrupt service routine can be carried out the interrupt vector that is read in proper order, also can at first define each priority of interrupt by the external software program, after the interruption service routine reads interrupt vector register, determine the interrupt service routine of current limit priority to be performed earlier by the external software program, carry out the interruption of next priority then.When carrying out the interrupt vector read, if produce new interrupt vector, then this interrupt vector can import or door and interrupt vector register corresponding position with it in, the host computer of chip can read interrupt vector register once more, carries out accordingly to interrupt; If do not produce new interrupt vector, after executing the interrupt vector that reads, just withdraw from interrupt service routine.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (6)
1, the Interrupt Process device in a kind of chip is characterized in that comprising:
Interrupt generating unit is used to produce look-at-me;
The interrupt vector storage unit is used to store the interrupt vector that interrupt generating unit produces;
The control output unit is used for interrupt generating unit and produces when interrupting, and sends interrupt request singal;
Have a plurality of functional modules in the interrupt generating unit, wherein the look-at-me of each functional module is imported control output unit and interrupt vector storage unit respectively.
2, Interrupt Process device according to claim 1 is characterized in that: described interrupt vector storage unit is for reading zero clearing formula register, and the look-at-me of each functional module is input in the interior corresponding position of register.
3, Interrupt Process device according to claim 1 is characterized in that: described control output unit is or door, or the output terminal of door is connected with the host computer of chip.
4, Interrupt Process device according to claim 1 is characterized in that: described interrupt vector storage unit is connected with the host computer of chip.
5, a kind of interior Interrupt Process device of the described chip of claim 1 that utilizes carries out interruption processing method, it is characterized in that comprising step:
Produce the functional module of interrupting in A, the interrupt generating unit look-at-me is input to interrupt vector storage unit and control output unit respectively;
The host computer of B, chip reads the interrupt vector storage unit by interrupt service routine, carries out the interruption that reads;
C, when interrupt service routine carry out to interrupt, if there is new interruption to produce, then repeated execution of steps A, B if there is not new interruption to produce, after interrupt service routine is finished, withdraw from.
6, the interruption processing method in the chip according to claim 5 is characterized in that: in described step C, interrupt service routine is carried out the interruption that reads in proper order or is carried out the interruption that reads according to predefined interrupt priority level.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101040515A CN100562863C (en) | 2004-12-31 | 2004-12-31 | Interrupt processing device and method in chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004101040515A CN100562863C (en) | 2004-12-31 | 2004-12-31 | Interrupt processing device and method in chip |
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| CN1632772A CN1632772A (en) | 2005-06-29 |
| CN100562863C true CN100562863C (en) | 2009-11-25 |
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| CN102541649B (en) * | 2010-12-27 | 2013-08-14 | 北京中电华大电子设计有限责任公司 | Interrupt controller capable of configuring interrupt program running mode |
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