CN100555635C - A kind of power groove MOS field effect tube and manufacture method thereof - Google Patents
A kind of power groove MOS field effect tube and manufacture method thereof Download PDFInfo
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- CN100555635C CN100555635C CNB2008100236269A CN200810023626A CN100555635C CN 100555635 C CN100555635 C CN 100555635C CN B2008100236269 A CNB2008100236269 A CN B2008100236269A CN 200810023626 A CN200810023626 A CN 200810023626A CN 100555635 C CN100555635 C CN 100555635C
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Abstract
一种功率沟槽式MOS场效应管及其制造方法，其特征在于对MOS场效应管有源区外围的终端保护结构进行了以下几方面改进：1、将单胞阵列的边缘单胞外围的P-阱直接作为场限环；2、将场板中的场氧化硅层作为P型杂质离子自对准注入的阻挡层直接形成场限环P-区，截止环P-区及单胞的P-阱；3、在P型掺杂之后直接进行N型掺杂，使得场限环P-区、截止环P-区和单胞阵列的P-阱三者上部均带N+区；4、在终端保护结构处，金属层连续或分段的覆盖所有场限环与场板区域上方。本发明在保证产品性能的前提下，节省了场限环光刻版，多晶硅光刻版及源区注入光刻板，将原来的七块光刻板减少到四块光刻版，从而大大降低了制造成本，可适用于大批量低成本制造功率沟槽式MOS场效应管。
A power trench type MOS field effect transistor and its manufacturing method, which is characterized in that the terminal protection structure on the periphery of the active region of the MOS field effect transistor is improved in the following aspects: 1. The periphery of the edge unit cell of the unit cell array The P - well is directly used as a field-limiting ring; 2. The field silicon oxide layer in the field plate is used as a barrier layer for the self-aligned implantation of P-type impurity ions to directly form the field-limiting ring P - region, the stop ring P - region and the unit cell P - well; 3. Do N-type doping directly after P-type doping, so that the P - region of the field-limiting ring, the P - region of the stop ring and the P - well of the unit cell array all have an N + region; 4 1. At the terminal protection structure, the metal layer covers all field limiting rings and field plate regions continuously or in sections. On the premise of ensuring product performance, the present invention saves field-limiting ring photoresist plates, polysilicon photoresist plates and source region injection photoresist plates, and reduces the original seven photoresist plates to four photoresist plates, thereby greatly reducing manufacturing costs. The cost is suitable for manufacturing power trench MOS field effect transistors in large quantities and at low cost.
Description
Technical field
The present invention relates to a kind of power groove MOS field effect tube and manufacture method thereof.This power groove MOS field effect tube can be N or P type metal-oxide-semiconductor field effect transistor, and the voltage that it can bear is at mesolow scope (20V＜voltage＜300V).
Background technology
Power groove MOS field effect tube is as a kind of novel high-power metal-oxide-semiconductor field effect transistor that grows up on plane formula metal-oxide-semiconductor field effect transistor basis, eliminated the parasitic JFET effect of plane formula metal-oxide-semiconductor field effect transistor, having characteristics such as conducting resistance reduces, saturation pressure reduces, switching speed is fast, gully density is high, chip size is little, is the main flow of mesolow high-power MOS field effect transistor development.The improvement that power groove MOS field effect tube design and manufacture method are continuing always, towards low on-resistance (Rdson), high withstand voltage, high-frequency direction develops.In recent years, along with getting involved being on the increase of businessman, the fierceness of market competition, requirement to cost control is also more and more higher, how under the situation that does not reduce device performance (as feature conducting resistance (Specific Rdson), withstand voltage, device capacitor etc.), reduce manufacturing cost and become important research direction at present.The control manufacturing cost has two main directions, and the one, reduce chip area, on onesize silicon chip, obtain more chip.Other direction is to reduce the photoetching number of times, and production cost is directly proportional with the photoetching number of times, so use the photoetching number of times of trying one's best few, can reduce production cost significantly.
Terminal protection structure is an important link of MOS field effect tube design.MOS field effect tube, need bear higher reverse voltage during work, the surface potential that is positioned between each the unit cell array in parallel of active area in the middle of the device is roughly the same, and be positioned at the unit cell at active area edge (being terminal) and the current potential of substrate surface differs greatly, thereby the surface field that often causes the outer ring unit cell is too concentrated the edge breakdown that causes device.Therefore, need increase terminal protection structure, reduce the terminal electric field density, play and improve the withstand voltage effect of metal-oxide-semiconductor field effect transistor in the outer ring of unit cell array.
For the MOS field effect tube greater than 20V, its terminal protection structure is from inside to outside formed by field limiting ring, field plate with by ring.And manufacturing field limiting ring and active area need carry out Twi-lithography.Present technical merit is made a kind of power groove MOS field effect tube (seeing shown in Figure 1), needs to use seven reticle altogether, and finishes by following technological process:
The first step, a growth silicon oxide layer on semi-conductor silicon chip;
Second step by photoetching, defined active area, and the field silicon oxide layer is carried out etching (reticle 1);
The 3rd step by photoetching, defined the field limiting ring injection zone, carried out the doping of P type and formed field limiting ring P
+District's (reticle 2);
The 4th step in semi-conductor silicon chip superficial growth hard mask oxide layer, by photoetching, defined the trench etching zone, and carried out hard mask oxide layer corrosion (photolithography plate 3)
In the 5th step, carry out the deep trench silicon etching based on hard mask oxide layer;
In the 6th step, the growth gate oxide is in gate oxide surface deposition conductive polycrystalline silicon;
The 7th step by photoetching, defined the etching polysilicon zone, carried out etching polysilicon (reticle 4);
In the 8th step, carry out the p type impurity ion in whole semi-conductor silicon chip surface and inject, and push away the P that trap forms the unit cell array
-Trap;
The 9th step by photoetching, defined the source region, carried out N type foreign ion and injected, and push away trap formation N
+District's (reticle 5);
The tenth step is in whole semi-conductor silicon chip surface deposition dielectric layer;
In the 11 step, by photoetching, define the contact hole zone, and carry out oxide layer etching (reticle 6);
In the 12 step, deposited metal by photoetching, defines etch areas, carries out metal etch (reticle 7).
This manufacture process relates to 7 photoetching altogether, especially field limiting ring is made separately, need use oxidation, push away heat treatment processes such as trap, the increase without exception of these manufacturing steps the manufacturing cycle, process complexity has increased manufacturing cost, therefore can reduce photoetching as far as possible, and thermal process is the direction that the present invention mainly considers.
Summary of the invention
The invention provides a kind of power groove MOS field effect tube and manufacture method thereof; its objective is will be under the prerequisite that guarantees not influence device performance (as feature conducting resistance (Specific Rdson), withstand voltage etc.); reduce the photoetching number of times by optimal design, thereby reduce the manufacturing cost of device terminal protection structure.
For achieving the above object; first kind of technical scheme that metal-oxide-semiconductor field effect transistor of the present invention adopts is: a kind of power groove MOS field effect tube on top plan view, is unit cell array in parallel in the middle of this device; the periphery of unit cell array is provided with terminal protection structure, and its innovation is:
On top plan view, described terminal protection structure is made up of by ring a field limiting ring, field plate and one, peripheral from the edge unit cell of unit cell array, terminal protection structure is pressed field limiting ring, field plate from inside to outside, is ended the setting of ring order, and the peripheral field limiting ring that directly connects of edge unit cell;
On the cross section, field limiting ring is positioned at the first conductive type epitaxial layer upper area of semi-conductor silicon chip, it is made of the first conduction type doped region and the second conduction type doped region, and wherein, the first conduction type doped region is positioned at the top of the second conduction type doped region;
On the cross section, field plate is made of silicon oxide layer and field plate region metal level, wherein, silicon oxide layer be divided into a silicon oxide layer and dielectric layer two-layer, the field silicon oxide layer is positioned on the first conductive type epitaxial layer surface of semi-conductor silicon chip, dielectric layer covers on the silicon oxide layer on the scene, and the field plate region metal level is positioned on the dielectric layer;
On the cross section, be positioned at the first conductive type epitaxial layer upper area of semi-conductor silicon chip by ring, it is made of the first conduction type doped region and the second conduction type doped region, wherein, the first conduction type doped region is positioned at the top of the second conduction type doped region, and metal level connects into equipotential with the first conduction type doped region and the second conduction type doped region by the ring district;
On the cross section, field limiting ring, be same manufacturings layer by ring and the unit cell array three second conduction type doped region separately, their the second conductive type impurity doping depth is identical; Field limiting ring, be same manufacturings layer by ring and the unit cell array three first conduction type doped region separately, their the first conductive type impurity doping depth is identical; Field silicon oxide layer in the field plate at field limiting ring with above zone between the ring, and as the barrier layer of the first conductive type impurity ion and second conductive type impurity ion autoregistration injection.
For achieving the above object; second kind of technical scheme that metal-oxide-semiconductor field effect transistor of the present invention adopts is: a kind of power groove MOS field effect tube on top plan view, is unit cell array in parallel in the middle of this device; the periphery of unit cell array is provided with terminal protection structure, and its innovation is:
On top plan view, described terminal protection structure is made up of by ring at least two field limiting rings, the field plate identical with field limiting ring quantity and one, peripheral from the edge unit cell of unit cell array, terminal protection structure is pressed field limiting ring, field plate, field limiting ring, field plate from inside to outside, be rule setting at last by ring, and the peripheral field limiting ring that directly connects of edge unit cell;
On the cross section, field limiting ring is positioned at the first conductive type epitaxial layer upper area of semi-conductor silicon chip, it is made of the first conduction type doped region and the second conduction type doped region, and wherein, the first conduction type doped region is positioned at the top of the second conduction type doped region;
On the cross section, field plate is made of silicon oxide layer and field plate region metal level, wherein, silicon oxide layer be divided into a silicon oxide layer and dielectric layer two-layer, the field silicon oxide layer is positioned on the first conductive type epitaxial layer surface of semi-conductor silicon chip, dielectric layer covers on the silicon oxide layer on the scene, and the field plate region metal level is positioned on the dielectric layer;
On the cross section, be positioned at the first conductive type epitaxial layer upper area of semi-conductor silicon chip by ring, it is made of the first conduction type doped region and the second conduction type doped region, wherein, the first conduction type doped region is positioned at the top of the second conduction type doped region, and metal level connects into equipotential with the first conduction type doped region and the second conduction type doped region by the ring district;
On the cross section, field limiting ring, be same manufacturings layer by ring and the unit cell array three second conduction type doped region separately, their the second conductive type impurity doping depth is identical; Field limiting ring, be same manufacturings layer by ring and the unit cell array three first conduction type doped region separately, their the first conductive type impurity doping depth is identical; Field silicon oxide layer in the field plate at field limiting ring with above zone between the ring, and as the barrier layer of the first conductive type impurity ion and second conductive type impurity ion autoregistration injection.
Related content in first kind and second kind technical scheme of above-mentioned metal-oxide-semiconductor field effect transistor is explained as follows:
1, described " edge unit cell " is meant the unit cell of unit cell array edges position.Described " from inside to outside " is meant that with the unit cell array be the direction that spread to the periphery at the center.Described " in the middle of this device " is meant the zone of device unit cell array, or is called active area, and it is relative peripheral terminal protection structure.
2, described " first conduction type " and " second conduction type " refer to the N type for N type metal-oxide-semiconductor field effect transistor first conduction type among both, and second conduction type refers to the P type; Just in time opposite for P type metal-oxide-semiconductor field effect transistor.
3, the field plate region metal level begins to till the silicon oxide layer of the field of ring top from the unit cell array periphery, the top that covers all field limiting rings and field plate continuous or segmentation.So-called segmentation covers and is meant that the field plate region metal level begins to be divided into plurality of sections till the final position from start position, and this plurality of sections field plate region metal level correspondence covers the top of all field limiting rings and field plate.
Be to realize said structure, the technical scheme that metal-oxide-semiconductor field effect transistor manufacture method of the present invention adopts is: according to above-mentioned first or the manufacture method of the described power groove MOS field effect tube of second technical scheme, its innovation is:
(1) described field limiting ring, by the ring and the unit cell array three second conduction type doped region separately, form by the same second conduction type doping process;
(2) described field limiting ring, by the ring and the unit cell array three first conduction type doped region separately, form by the same first conduction type doping process;
(3) the field silicon oxide layer in the described field plate formed before the first conductive type impurity ion and the second conductive type impurity ion inject, and the barrier layer of injecting as the terminal protection zone first conductive type impurity ion and the second conductive type impurity ion autoregistration;
(4) described field limiting ring, field plate, the dielectric layer in the zone and metal level are respectively same manufacturings layer separately by ring and unit cell array three.
Metal-oxide-semiconductor field effect transistor manufacture method of the present invention comprises following process steps:
A) provide the semi-conductor silicon chip with two relative interareas of first conduction type;
B) on first interarea, form first silicon oxide layer, silicon oxide layer on the spot;
E) optionally shelter and etching first silicon oxide layer, define active area and terminal protection zone;
D) on first interarea, form second silicon oxide layer, optionally shelter and etching second silicon oxide layer, form deep plough groove etched hard mask;
E) form deep trench in the first interarea etching with hard mask;
F) etching is removed second silicon oxide layer;
G) form the 3rd silicon oxide layer, i.e. grid silicon oxide layer in first interarea and deep trench surface;
H) form conductive polycrystalline silicon floor in the 3rd silicon oxide layer surface;
I) conductive polycrystalline silicon floor is carried out general etching, form the conductive polycrystalline silicon in the unit cell array region internal channel;
J) in having first interarea that a silicon oxide layer stops, carry out the second conductive type impurity ion and inject, and by knot form field limiting ring, by ring and the unit cell array three second conduction type doped region separately;
K) in having first interarea that a silicon oxide layer stops, carry out the first conductive type impurity ion and inject, and by knot form field limiting ring, by ring and the unit cell array three first conduction type doped region separately;
L) form the 4th silicon oxide layer, i.e. dielectric layer in first interarea;
M) optionally shelter and etching the 4th silicon oxide layer, form the contact hole of unit cell array and end the contact hole that encircles; Position below contact hole deep etching to the first conduction type doped region lower surface;
N) form metal level in the 4th silicon oxide layer surface;
O) optionally shelter and etching sheet metal.
Design concept of the present invention is described below: for power groove MOS field effect tube, must bear reverse withstand voltagely when it is used, metal-oxide-semiconductor field effect transistor can be at its edge designs terminal protection structure usually.Terminal protection structure mainly contains field plate, field limiting ring and ends ring and form, and wherein field plate and field limiting ring are used in combination and improve the surface breakdown characteristic.Field plate can suppress the low puncture that surface charge causes effectively, and field limiting ring then can slow down the PN junction puncture that the planar junction curvature effect causes.Field plate and field limiting ring be used in combination the whole withstand voltage properties that can significantly improve MOS field effect tube.And design mainly is to collect surface charge by ring, avoids causing that surperficial transoid causes electric leakage.
The inventive point of metal-oxide-semiconductor field effect transistor of the present invention and manufacture method thereof is the terminal protection structure design and makes that the optimization part of its relative prior art (seeing shown in Figure 1) embodies a concentrated expression of the following aspects:
(1) field limiting ring, be same manufacturings layer by the ring and unit cell array three's the second conduction type doped region, form simultaneously by the doping of second conductive type impurity in the mill, the degree of depth is identical.
(2) field limiting ring, be same manufacturings layer by ring and the unit cell array three first conduction type doped region separately, form simultaneously by the doping of first conductive type impurity in the mill, the degree of depth is identical.
(3) on field limiting ring and the field silicon oxide layer above the zone injects as the first conductive type impurity ion and the second conductive type impurity ion autoregistration between ring barrier layer.
(4) metal-oxide-semiconductor field effect transistor of the present invention encloses the effect that the second conduction type doped region plays field limiting ring by one of unit cell array outmost turns, simultaneously according to different withstand voltage demands, can adjust the width of the field limiting ring second conduction type doped region.
(5) metal-oxide-semiconductor field effect transistor terminal protection structure of the present invention place, metal level is continuously or above all field limiting rings of covering of segmentation and the field plate zone.
Its advantage of the relative prior art of the present invention and effect be mainly reflected in following some:
1, the present invention with field limiting ring, by the ring and unit cell array three finish in the same step of the second conduction type doped region separately, reduced photoetching number of times and injection and thermal process, shortened manufacturing time, saved cost.And the original field limiting ring second conduction type doped region is made separately, need to do a photoetching, injects and pushes away trap, could form required field limiting ring.
2, only need in the metal-oxide-semiconductor field effect transistor manufacture process of the present invention to use four photolithography plates, and can bear the reverse voltage of 20V-300V.And the groove MOS field effect tube of existing 80V shown in Figure 1 needs 7 photolithography plates usually.This shows that the present invention has optimized structure greatly, reduced the photoetching number of times, reduced manufacturing cost.
Now that manufacture method of the present invention and the contrast of existing manufacture method is as follows:
From the form of above contrast, can clearly find out following effect:
The first, manufacture method of the present invention has been saved field limiting ring reticle and corresponding technology;
The second, manufacture method of the present invention has been saved polysilicon photolithography plate and corresponding technology;
The 3rd, manufacture method of the present invention has been saved the source electrode photolithography plate and has been become and corresponding technology;
Usually, the manufacturing cost of power groove MOS field effect tube can be simplified to the photoetching number of times and calculate, increase a photoetching and increase by 10～15% cost approximately, therefore the present invention has reduced third photo etching and approximately can reduce cost about 30～40%, and this effect for the market competitiveness that improves power groove MOS field effect tube is significant.
Description of drawings
Accompanying drawing 1 is existing power groove MOS field effect tube generalized section;
Accompanying drawing 2 is the embodiment of the invention one a power groove MOS field effect tube schematic top plan view;
Accompanying drawing 3 is the embodiment of the invention one a power groove MOS field effect tube schematic cross-section;
Accompanying drawing 4～9 is that the embodiment of the invention one power groove MOS field effect tube technology is made schematic flow sheet;
Accompanying drawing 10 is the embodiment of the invention two power groove MOS field effect tube schematic cross-sections.
In the above accompanying drawing: 1, unit cell array; 2, field limiting ring; 3, field plate; 4, by ring; 5, edge unit cell; 6, field limiting ring P
-The district; 7, N
-The type epitaxial loayer; 8, grid silicon oxide layer; 9, a silicon oxide layer; 10, by ring P
-The district; 11, the P of unit cell array
-Trap; 12, N
+The type substrate; 13, deep trench conductive polycrystalline silicon; 14, dielectric layer; 15, metal level; 16 conductive polycrystalline silicons; 17, field limiting ring P
+The district.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment one: a kind of power groove MOS field effect tube and manufacture method thereof
As shown in Figure 2, on top plan view, be unit cell array 1 in parallel in the middle of this metal-oxide-semiconductor field effect transistor, the periphery of unit cell array 1 is provided with terminal protection structure, and this metal-oxide-semiconductor field effect transistor also is provided with grid (not drawing among the figure), and the position of this grid requires to determine according to encapsulation.Described terminal protection structure is made up of by ring 4 field limiting ring 2, field plate 3 and one.
As shown in Figure 3, peripheral from active area edge unit cell 5 on the cross section, terminal protection structure is pressed field limiting ring 2, field plate 3 from inside to outside, is ended ring 4 order settings, and the edge unit cell 5 peripheral field limiting rings 2 that directly connect.
By encircling 4 by top band N
+Ending of district encircles P
-District 10 constitutes, by ring P
-District 10 is positioned at the N of semi-conductor silicon chip
-On the type epitaxial loayer 7, metal level respectively will be by ring P
-District 10 and N
+The district connects into equipotential.
Semi-conductor silicon chip N
-Field limiting ring P on the type epitaxial loayer 7
-Distinguish 6, end ring P
-The P of district 10 and unit cell array
-Trap 11 is same manufacturing layer, and their p type impurity doping depth is identical.Field limiting ring P
-Distinguish 6, end ring P
-The P of district 10 and unit cell array
-Trap 11 three tops with N
+The district is same manufacturing floor, and their the N type doping impurity degree of depth is identical.Field silicon oxide layer 9 in the field plate 3 is as the barrier layer that the p type impurity ion injects and the autoregistration of N type foreign ion is injected, and this barrier layer is positioned at field limiting ring P
-The district 6 with by the ring P
-The top in zone between the district 10.
Referring to Fig. 4～shown in Figure 9, present embodiment one power groove MOS field effect tube manufacture method comprises following process steps:
A. in epitaxial wafer superficial growth field silicon oxide layer, form field silicon oxide layer 9 (see figure 4)s in terminal protection structure zone thereafter by photoetching and corrosion.
B. the hard mask growth of silicon.Wherein hard mask can adopt LPTEOS or thermal oxidation silicon dioxide to add chemical vapour deposition (CVD) silicon dioxide or thermal oxidation silicon dioxide adds silicon nitride.By photoetching and anisotropic etching be formed with the hard mask of deep trench of source region unit cell thereafter.
C. deep plough groove etched.Groove adopts anisotropic etching to form vertical sidewall (sidewall and silicon chip surface are 88 degree usually).See Fig. 5 active area unit cell array deep trench.Etching was removed hard mask after groove was finished.
D. gate oxidation/polysilicon deposit.N in the band deep trench
- Type epitaxial loayer 7 superficial growth grid silicon oxide layers 8 (see figure 6)s are then at grid silicon oxide layer 8 surface deposition conductive polycrystalline silicon floors.Existing common process is adopted in gate oxidation/polysilicon deposit.
E. polysilicon layer etching.Specifically be that conductive polycrystalline silicon floor is carried out general etching, left conductive polycrystalline silicon is formed with deep trench conductive polycrystalline silicon 13 (see figure 6)s of source region unit cell.
F. the P of unit cell array
-Trap, by the ring P
-District and field limiting ring P
-The district is injected.Specifically be to carry out the autoregistration of p type impurity ion with the field silicon oxide layer 9 in the field plate 3 as the barrier layer to inject (implanting impurity ion is a boron usually), and push away trap, formed have same depth by ring P
-District 10, field limiting ring P
-The P of district 6 and unit cell array
-Trap 11 (see figure 7)s.
G.N type source layer injects (N
+Inject), annealing.Specifically be to carry out the autoregistration of N type foreign ion with the field silicon oxide layer 9 in the field plate 3 as the barrier layer to inject (ion that injects is arsenic As usually), form simultaneously after the annealing same depth by ring P
-District 10, field limiting ring P
-The P of district 6 and unit cell array
-The N on trap 11 three tops
+District's (see figure 7).
H. dielectric layer deposit.See Fig. 8, dielectric layer 14 deposits can be chosen boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) or silex glass (USG) etc.
I. hole photoetching/etching.Specifically be that hole depth is dug to N to active area, by the hole photoetching/corrosion that encircles and conductive polycrystalline silicon is drawn
+The district is with upper/lower positions, allows the hole can be directly and P
-The trap (see figure 8) that links to each other.
J. metal level deposit/photoetching/etching.Prior art is adopted in the formation of hole and metal level 15 interconnection lines, metal filledly can adopt tungsten plug technology or direct metal fill process.
The present invention has saved field limiting ring, and three layer photoetching plates are injected in polysilicon and source region, under the prerequisite that guarantees properties of product, has reduced the photoetching number of times, reduces manufacturing cost greatly, applicable to the low-cost high-power groove MOS field effect transistor of making in enormous quantities.
Embodiment two: a kind of power groove MOS field effect tube and manufacture method thereof
As shown in figure 10; the difference of present embodiment and embodiment one is: terminal protection structure is made up of by ring 4 two field limiting rings 2, two blocks of field plates 3 and one; peripheral from active area edge unit cell 5; terminal protection structure is pressed field limiting ring 2, field plate 3, field limiting ring 2, field plate 3 from inside to outside; be rule setting at last by ring 4, and the edge unit cell 5 peripheral field limiting rings 2 that directly connect.The top that covers all field limiting rings and field plate that metal on the field plate 3 is continuous (also can change the top that covers all field limiting rings and field plate of segmentation into, not draw among the figure).Other structure and manufacture method content are identical with embodiment one, no longer are repeated in this description here.
By present embodiment can directly draw terminal protection structure by three field limiting rings 2, three blocks of field plates 3 and one by ring 4 situations about forming.Also can draw terminal protection structure by three above field limiting rings 2, three blocks of above field plates 3 and one by ring 4 situations about forming.
Though above-mentioned explanation is described with N channel groove type metal-oxide-semiconductor field effect transistor, the present invention also goes for P raceway groove groove type MOS field effect transistor, wherein only needs to change P into N, and N changes P into and gets final product.
Claims (6)
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| CN101719516B (en) * | 2009-11-20 | 2011-04-06 | 苏州硅能半导体科技股份有限公司 | Low gate charge deep trench power MOS device and manufacturing method thereof |
| CN101777514B (en) * | 2010-02-03 | 2012-12-05 | 香港商莫斯飞特半导体有限公司 | A trench type semiconductor power device and its preparation method |
| CN101853854B (en) * | 2010-03-12 | 2012-11-21 | 无锡新洁能功率半导体有限公司 | Groove power MOS component with improved type terminal structure and manufacturing method thereof |
| CN102569388B (en) * | 2010-12-23 | 2014-09-10 | 无锡华润上华半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN102593171B (en) * | 2011-01-14 | 2014-09-17 | 苏州英诺迅科技有限公司 | RF (Radio Frequency) lateral diffusion P-type MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| CN103050404B (en) * | 2011-10-14 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The manufacture method of a kind of MOSFET element groove and guard ring |
| US8823096B2 (en) * | 2012-06-01 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertical power MOSFET and methods for forming the same |
| CN104143566A (en) * | 2013-05-10 | 2014-11-12 | 江西创成半导体有限责任公司 | Polysilicon Field Limiting Ring |
| CN103367330A (en) * | 2013-07-31 | 2013-10-23 | 上海宏力半导体制造有限公司 | Testing structure of power semiconductor device and manufacture method of testing structure |
| CN103746045B (en) * | 2014-02-10 | 2016-04-13 | 中国电子科技集团公司第四十四研究所 | Suppress the method for surface high-temperature inversion of P-type super-high-resistancmonocrystalline monocrystalline silicon material |
| CN105448958B (en) * | 2014-06-26 | 2019-03-15 | 无锡华润微电子有限公司 | The terminal protection ring structure and its manufacturing method of DMOS |
| CN105845614B (en) * | 2015-01-15 | 2019-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
| CN104795446B (en) * | 2015-04-17 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | Trench gate mosfet and its manufacture method |
| CN111341832B (en) * | 2018-12-19 | 2023-10-27 | 无锡华润华晶微电子有限公司 | Junction terminal structure and preparation method thereof |
| CN113889407A (en) * | 2021-09-27 | 2022-01-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench type IGBT device and trench type IGBT device |
| CN115148789A (en) * | 2022-07-21 | 2022-10-04 | 华虹半导体(无锡)有限公司 | Semiconductor structure and forming method thereof |
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