CN100550588C - Power circuit, power control circuit and power control method - Google Patents

Abstract

The invention provides a kind of power circuit, power control circuit and power control method.The DC-DC converter and the first and second by-pass switch circuit are arranged in parallel between the input pin and first and second output pins, and come work according to the combination of the required magnitude of voltage of the magnitude of voltage of described input pin and described first output pin.The start-up control circuit makes the DC-DC converter, up to the voltage of this DC-DC converter becomes process when equating with the voltage of output pin, unconditionally is operated under the decompression mode when this DC-DC converter is activated.The output voltage gradient control circuit makes the rise of output voltage slope of the rise of output voltage slope of the described first and second by-pass switch circuit and described DC-DC converter synchronous.

Description

Power supply circuit, power supply control circuit and power supply control method

technical field

The invention relates to a power supply circuit, a power supply control circuit, and a power supply control method.

Background technique

Recently, memory cards are widely used as data recording media for portable electronic devices (digital cameras, mobile phones, etc.). The operating voltage of the memory card is determined according to the operating voltage of the nonvolatile memory (flash memory, etc.) mounted on the memory card. For example, there are non-volatile memories with an operating voltage of 3.3V and non-volatile memories with an operating voltage of 1.8V. Therefore, there are also memory cards with an operating voltage of 3.3V and memory cards with an operating voltage of 1.8V.

In order to make the working voltage of the memory card irrelevant to the working voltage of the internal non-volatile memory, a DC-DC converter needs to be installed on the memory card. In addition to volatile memory, memory cards must also be equipped with logic circuits for controlling nonvolatile memory. However, it is inefficient to mount two kinds of logic circuits (a logic circuit for 3.3V and a logic circuit for 1.8V) on a memory card according to the operating voltage of a nonvolatile memory, and it is inefficient when considering When the size of the semiconductor device of the circuit is reduced by the fact that its voltage is fixed, it is ideal to mount only logic circuits for 1.8V on the memory card. However, a DC-DC converter for a logic circuit and a DC-DC converter for a nonvolatile memory need to be mounted on the memory card. Incidentally, Japanese Unexamined Patent Application No. Hei 7-21791, Japanese Unexamined Patent Application No. Hei 9-154275, Japanese Unexamined Patent Application No. Hei 9-294368, etc. disclose about DC-DC converters. Technology.

It is possible to realize that the operating voltage of the memory card is independent of the operating voltage of the internal non-volatile memory by installing a DC-DC converter on the memory, however, simply installing two or more DCs on the memory card - DC converters are very inefficient. In addition, since the memory card is inserted into/removed from the electronic device in the activated state, when the step-up DC-DC converter generates the voltage required inside the memory card, The problem is that when the memory card is inserted into the electronic equipment, the input voltage flows through to the output terminal, causing an inrush current. In addition, if the rising timing of the power supply voltage of the nonvolatile memory and the power supply voltage of the logic circuit is not taken into account, there may be a latch-up caused by a semiconductor device constituting the nonvolatile memory or the logic circuit. Risk of burning.

Contents of the invention

An object of the present invention is to make the working voltage of the memory card independent of the working voltage of the internal non-volatile memory while ensuring efficiency and safety.

In an aspect of the present invention, the power supply circuit is configured to include an input pin, a first output pin, a second output pin, a DC-DC converter, a first bypass switch circuit, a second bypass switch circuit, The start control circuit and the output slope control circuit. For example, a power supply circuit is constructed using a semiconductor device. The input pin receives a voltage of a first predetermined value or a voltage of a second predetermined value less than the first predetermined value. For the first output pin, a voltage output of the first or second predetermined value is required. For the second output pin, a voltage output of a second predetermined value is required. For example, a power supply circuit is mounted on a memory card having a nonvolatile memory and a memory control circuit that controls the nonvolatile memory. The voltage of the first output pin is used as the power supply voltage of the nonvolatile memory, and the voltage of the second output pin is used as the power supply voltage of the memory control circuit.

According to the combination of the voltage value of the input pin and the voltage value required by the first output pin, the DC-DC converter generates an output voltage from the voltage of the input pin in buck mode or boost mode, and outputs the output voltage to at least one of the first and second output pins. When the voltage is not output from the DC-DC converter to the first output pin, the first bypass switch circuit is turned on to output the voltage of the input pin to the first output pin. When the voltage is not output from the DC-DC converter to the second output pin, the second bypass switch circuit is turned on to output the voltage of the input pin to the second output pin.

During the period from when the DC-DC converter is started until the output voltage of the DC-DC converter becomes equal to the voltage of the input pin, the start-up control circuit makes the DC-DC converter operate in step-down mode, while the voltage of the input pin The combination of the voltage value and the desired voltage value of the first output pin is independent. When the first bypass switch circuit is turned on, the output slope control circuit synchronizes the rising slope of the output voltage of the first bypass switch circuit with the rising slope of the output voltage of the DC-DC converter, and when the second bypass switch circuit When turned on, the output slope control circuit synchronizes the rising slope of the output voltage of the second bypass switch circuit with the rising slope of the output voltage of the DC-DC converter.

For example, when the voltage value of the input pin is a first predetermined value and the required voltage value of the first output pin is the first predetermined value, the DC-DC converter circuit generates a second voltage from the voltage of the input pin in step-down mode. an output voltage of a predetermined value, and output the output voltage to the second output pin. When the voltage value of the input pin is a first predetermined value and the required voltage value of the first output pin is a second predetermined value, the start-up control circuit generates an output voltage of a second predetermined value from the voltage of the input pin in a step-down mode , and output the output voltage to the first and second output pins. When the voltage value of the input pin is a second predetermined value and the voltage value required by the first output pin is a first predetermined value, the start-up control circuit generates an output of the first predetermined value from the voltage of the input pin in boost mode voltage, and output the output voltage to the first output pin. When the voltage value of the input pin is a second predetermined value and the required voltage value of the first output pin is a second predetermined value, the start-up control circuit generates an output of the second predetermined value from the voltage of the input pin in boost mode voltage, and output the output voltage to the first and second output pins.

Preferably, the output slope control circuit is configured to include a first on-resistance control circuit and a second on-resistance control circuit. When the first bypass switch circuit is turned on, the first on-resistance control circuit detects the voltage difference between the voltage following the voltage of the first output pin and the voltage of the second output pin, and controls the first output pin according to the detection result. On-resistance of the bypass switch circuit. When the second bypass switch circuit is turned on, the second on-resistance control circuit detects the voltage difference between the voltage of the second output pin and the voltage following the voltage of the first output pin, and controls the second output pin according to the detection result. On-resistance of the bypass switch circuit.

In an aspect of the present invention as described above, by operating the DC-DC converter, the first and the second bypass switch circuits according to the combination of the voltage value of the input voltage and the voltage value required by the first output pin The DC-DC converter can be shared between the non-volatile memory and the memory control circuit, thus reducing the number of DC-DC converters. In addition, the inrush current when the DC-DC converter operates in boost mode can be reliably prevented by providing a start-up control circuit. Furthermore, simultaneous activation of the voltage at the first output pin and the voltage at the second output pin can be achieved by providing an output slope control circuit to operate the first and second bypass switch circuits in conjunction with the DC-DC converter. Therefore, the risk of burnout caused by the latch-up effect of the semiconductor device constituting the nonvolatile memory or the memory control circuit can be avoided. In this way, it is possible to realize that the operating voltage of the memory card is independent of the operating voltage of the internal non-volatile memory while ensuring efficiency and safety.

Description of drawings

By reading the following detailed description in conjunction with the accompanying drawings, the characteristics, principles and uses of the present invention will become more apparent. In the accompanying drawings, the same elements are denoted by the same reference numerals, wherein:

Figure 1 is a schematic diagram illustrating an embodiment of the present invention;

2 is a schematic diagram showing the configuration of a power supply circuit;

Fig. 3 is a schematic diagram illustrating the operation of a decoder;

4 is a schematic diagram showing the operation (first mode) of the power supply circuit;

5 is a schematic diagram illustrating the operation (first mode) of a buck PWM comparator and a boost PWM comparator;

FIG. 6 is a schematic diagram showing a rising characteristic (first mode) of a second output voltage;

7 is a schematic diagram showing the operation (second mode) of the power supply circuit;

8 is a schematic diagram showing the operation (third mode) of the power supply circuit;

9 is a schematic diagram illustrating the operation (third mode) of a buck PWM comparator and a boost PWM comparator;

FIG. 10 is a schematic diagram showing the rising characteristic of the first output voltage (third mode, no soft-start control);

11 is a schematic diagram showing the operation (third mode) of a buck PWM comparator and a boost PWM comparator at startup of the DC-DC converter;

Fig. 12 is a schematic diagram showing the rising characteristic of the first output voltage (third mode, with soft-start control);

13 is a schematic diagram showing the operation (fourth mode) of the power supply circuit;

Fig. 14 is a schematic diagram showing the construction of a decoder;

15 is a schematic diagram showing the configuration of an output slope control circuit; and

Fig. 16 is a schematic diagram showing how the first and second output voltages are simultaneously activated.

Detailed ways

Embodiments of the present invention will be described below with reference to the accompanying drawings. Figure 1 shows an embodiment of the invention. A memory card 1 to which the present invention is applied is configured to include a power supply circuit 2 , a nonvolatile memory 3 , and a memory card control circuit 4 . For example, the power supply circuit 2, the nonvolatile memory 3, and the memory card control circuit 4 are composed of separate semiconductor devices, and are connected to each other on a printed circuit board. The power supply circuit 2 generates a first output voltage Vo1 (3.3V or 1.8V) and a second output voltage Vo2 (1.8V) from an input voltage Vi (3.3V or 1.8V). The nonvolatile memory 3 uses the first output voltage Vo1 of the power supply circuit 2 as a power supply voltage. The memory card control circuit 4 uses the second output voltage Vo2 of the power supply circuit 2 as a power supply voltage. However, in the memory card control circuit 4, the external interface circuit 4a (a circuit that transmits/receives address signals and data signals to/from the outside) uses the input voltage Vi as a power supply voltage, and the memory interface circuit 4b (to the external The circuit for sending/receiving address signals and data signals from/from the nonvolatile memory 3) uses the first output voltage Vo1 of the power supply circuit 2 as a power supply voltage.

FIG. 2 shows the configuration of the power supply circuit 2 . The power supply circuit 2 is configured to include a first bypass switch circuit T6, a second bypass switch circuit T7, a first smoothing capacitor C1, a second smoothing capacitor C2, and a DC-DC converter CNV. The first bypass switch circuit T6 is provided so as to output the input voltage Vi (the voltage of the input pin IN of the power supply circuit 2) as the first output voltage Vo1 (the voltage of the first output pin OUT1 of the power supply circuit 2), and the first The bypass switch circuit T6 is composed of n-type transistors. The input pin of the first bypass switch circuit T6 is connected to the first output pin OUT1 of the power supply circuit 2 . The control pin of the first bypass switch circuit T6 receives the control signal D6 provided by the decoder DEC of the control circuit CTL in the DC-DC converter CNV.

The second bypass switch circuit T7 is provided so as to output the input voltage Vi as the second output voltage Vo2 (the voltage of the second output pin OUT2 of the power supply circuit 2 ), and the second bypass switch circuit T7 is composed of p-type transistors. The input pin of the second bypass switch circuit T7 is connected to the input pin IN of the power supply circuit 2 . The output pin of the second bypass switch circuit T7 is connected to the second output pin OUT2 of the power supply circuit 2 . The control pin of the second bypass switch circuit T7 receives the control signal D7 provided by the decoder DEC of the control circuit CTL in the DC-DC converter CNV. The first filter capacitor C1 is provided to filter the first output voltage Vo1 and is connected between the first output pin OUT1 of the power supply circuit 2 and the ground. The second filter capacitor C2 is provided to filter the second output voltage Vo2 and is connected between the second output pin OUT2 of the power supply circuit 2 and the ground.

The DC-DC converter CNV operates as a step-down DC-DC converter or a step-up DC-DC converter according to a combination of the voltage value of the input voltage Vi and the voltage value of the operating voltage of the nonvolatile memory 3 (the voltage value of the first output voltage Vo1). Compression type DC-DC converter works. The DC-DC converter CNV is constructed to include a step-down main switching transistor T1, a step-down synchronous rectifier circuit T2, a choke coil L1, a step-up main switching transistor T3, step-up synchronous rectifier circuits T4 and T5, a soft-start capacitor CS, A switch circuit SWM, and a control circuit CTL.

The step-down main switching transistor T1 is composed of an n-type transistor. The input pin of the step-down main switching transistor T1 is connected to the input pin IN of the power supply circuit 2 . The output pin of the step-down main switching transistor T1 is connected to one pin of the choke coil L1. The control pin of the step-down main switching transistor T1 receives the control signal D1 provided by the decoder DEC of the control circuit CTL. The step-down synchronous rectifier circuit T2 is composed of n-type transistors. The input pin of the buck synchronous rectifier circuit T2 is connected to ground. An output pin of the step-down synchronous rectifier circuit T2 is connected to one pin of the choke coil L1. The control pin of the step-down synchronous rectifier circuit T2 receives the control signal D2 provided by the decoder DEC of the control circuit CTL.

The boost main switching transistor T3 is composed of an n-type transistor. The input pin of the boost main switching transistor T3 is connected to the other pin of the choke coil L1. The output pin of the boost main switching transistor T3 is connected to ground. The control pin of the boost main switching transistor T3 receives the control signal D3 provided by the decoder DEC of the control circuit CTL. The step-up synchronous rectifier circuit T4 is composed of n-type transistors. The input pin of the step-up synchronous rectifier circuit T4 is connected to the other pin of the choke coil L1. The output pin of the step-up synchronous rectifier circuit T4 is connected to the first output pin OUT1 of the power supply circuit 2 . The control pin of the boost synchronous rectifier circuit T4 receives the control signal D4 provided by the decoder DEC of the control circuit CTL. The step-up synchronous rectifier circuit T5 is composed of n-type transistors. The input pin of the step-up synchronous rectifier circuit T5 is connected to the other pin of the choke coil L1. The output pin of the step-up synchronous rectifier circuit T5 is connected to the second output pin OUT2 of the power supply circuit 2 . The control pin of the boost synchronous rectifier circuit T5 receives the control signal D5 provided by the decoder DEC of the control circuit CTL.

One pin of the soft-start capacitor CS is connected to a second non-inverting input pin among first and second non-inverting input pins of the error amplifier ERA1 in the control circuit CTL. The other leg of the soft-start capacitor CS is connected to ground. With the startup of the DC-DC converter CNV, the soft-start capacitor CS is gradually charged through a constant current circuit (not shown), and, with the termination of the DC-DC converter CNV, through a discharge resistor (not shown) gradually being discharged.

A switch circuit SWM is provided to generate a memory voltage request signal MEM indicating which of 3.3V and 1.8V is required as the operating voltage of the nonvolatile memory 3 . When 3.3V is requested as the operating voltage of the nonvolatile memory 3, the switch circuit SWM enters an off state to set the memory voltage request signal MEM to a high level. When 1.8V is requested as the operating voltage of the nonvolatile memory 3, the switch circuit SWM enters a conduction state to set the memory voltage request signal MEM to a low level.

The control circuit CTL is configured to include resistors R1 to R6, switch circuits SW1 and SW2, voltage generators E1 to E4, error amplifier ERA1, triangle wave oscillator OSC, step-down PWM comparator PWM1, step-up PWM comparator PWM2, and Decoder DEC. One pin of the resistor R1 is connected to the first output pin OUT1 of the power supply circuit 2 . The other leg of resistor R1 is connected to one leg of resistor R2. The other leg of resistor R2 is connected to ground. One pin of the resistor R3 is connected to the second output pin OUT2 of the power supply circuit 2 . The other leg of resistor R3 is connected to one leg of resistor R4. The other leg of resistor R4 is connected to ground. The voltage generator E1 generates a reference voltage Ve1. The voltage generator E2 generates a reference voltage Ve2.

When the control signal SWD1 provided by the decoder DEC indicates a high level, the switch circuit SW1 connects the connection node of the resistors R1 and R2 to the inverting input pin of the error amplifier ERA1, and when the control signal SWD1 indicates a low level, The switch circuit SW1 connects the connection node of the resistors R3 and R4 to the inverting input pin of the error amplifier ERA1. When the control signal SWD2 provided by the decoder DEC indicates a high level, the switch circuit SW2 connects the output pin of the voltage generator E1 to the first non-inverting input pin of the error amplifier ERA1, and when the control signal SWD2 indicates a low level Normally, the switch circuit SW2 connects the output pin of the voltage generator E2 to the first non-inverting input pin of the error amplifier ERA1.

The error amplifier ERA1 receives at the inverting input pin the voltage supplied through the switching circuit SW1, at the first non-inverting input pin the voltage supplied through the switching circuit SW2, and at the second non-inverting input pin through the soft-start capacitor CS provides the voltage. The error amplifier ERA1 generates an output signal DF1 by amplifying the voltage difference between the voltage at the inverting input pin and the lower of the voltage at the first non-inverting input pin and the voltage at the second non-inverting input pin. The triangular wave oscillator OSC generates a triangular wave signal TW having a predetermined period. The voltage generator E3 generates the output signal DF2 by subtracting the bias voltage Ve3 from the voltage of the output signal DF1 of the error amplifier ERA1. Incidentally, the bias voltage Ve3 is set to the same voltage value as the wave height value of the triangular wave signal TW supplied from the triangular wave oscillator OSC.

The step-down PWM comparator PWM1 receives the output signal DF1 of the error amplifier ERA1 at the inverting input pin, and receives the triangular wave signal TW provided by the triangular wave oscillator OSC at the non-inverting input pin. When the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the voltage of the triangular wave signal TW, the step-down PWM comparator PWM1 sets the output signal Q1 to a high level and the output signal /Q1 to a low level. When the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW, the step-down PWM comparator PWM1 sets the output signal Q1 to a low level and the output signal /Q1 to a high level.

The boost PWM comparator PWM2 receives the output signal DF2 of the voltage generator E3 at the inverting input pin, and receives the triangular wave signal TW provided by the triangular wave oscillator OSC at the non-inverting input pin. When the voltage of the output signal DF2 of the voltage generator E3 is higher than the voltage of the triangular wave signal TW, the boost PWM comparator PWM2 sets the output signal Q2 to a high level and the output signal /Q2 to a low level. When the voltage of the output signal DF2 of the voltage generator E3 is lower than the voltage of the triangular wave signal TW, the boost PWM comparator PWM2 sets the output signal Q2 to low level and the output signal /Q2 to high level.

One pin of the resistor R5 is connected to the input pin IN of the power supply circuit 2 . The other leg of resistor R5 is connected to one leg of resistor R6. The other leg of resistor R6 is connected to ground. The voltage generator E4 generates a reference voltage Ve4. A voltage comparator CMP is provided to determine whether the input voltage Vi is 3.3V or 1.8V. The voltage comparator CMP receives the voltage at the junction node of resistors R5 and R6 at the inverting input pin (the voltage at which the input voltage Vi is divided by resistors R5 and R6), and at the non-inverting input pin the voltage generator E4 provides The reference voltage Ve4. When the voltage of the connection node of the resistors R5 and R6 is higher than the reference voltage Ve4, the voltage comparator CMP sets the output signal JDG to a high level, and when the voltage of the connection node of the resistors R5 and R6 is lower than the reference voltage Ve4 , the output signal JDG is set to a low level. The decoder DEC is based on the output signal JDG of the voltage comparator CMP, the memory voltage request signal MEM, the output signals Q1 and /Q1 of the buck PWM comparator PWM1, and the output signals Q2 and /Q2 of the boost PWM comparator PWM2. Signals SWD1, SWD2, and D1 to D7.

Figure 3 shows the operation of the decoder DEC. When the output signal JDG of the voltage comparator CMP is set to a high level and the memory voltage request signal MEM generated by the switch circuit SWM is set to a high level (when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the non- The operating voltage of the volatile memory 3), the decoder DEC sets the control signals D6 and D7 to a high level and sets the control signals SWD1, SWD2, and D4 to a low level. In addition, the decoder DEC outputs output signals Q2 and /Q2 of the step-up PWM comparator PWM2 as control signals D3 and D5, and outputs output signals Q1 and /Q1 of the step-down PWM comparator PWM1 as control signals D1 and D2.

When the output signal JDG of the voltage comparator CMP is set to high level and the memory voltage request signal MEM generated by the switch circuit SWM is set to low level (when 3.3V is supplied as input voltage Vi and 1.8V is requested as non- The operating voltage of the volatile memory 3), the decoder DEC sets the control signals SWD2 and D6 to a low level and sets the control signals SWD1 and D7 to a high level. In addition, the decoder DEC outputs the output signal Q2 of the boost PWM comparator PWM2 as the control signal D3, and outputs the output signal /Q2 of the boost PWM comparator PWM2 as the control signals D4 and D5, and outputs the output signal of the step-down PWM comparator PWM1 The output signals Q1 and /Q1 are used as control signals D1 and D2.

When the output signal JDG of the voltage comparator CMP is set to low level and the memory voltage request signal MEM generated by the switch circuit SWM is set to high level (when 1.8V is supplied as input voltage Vi and 1.8V is requested as non- The operating voltage of the volatile memory 3), the decoder DEC sets the control signals D5, D6 and D7 to low level and sets the control signals SWD1, SWD2 to high level. In addition, the decoder DEC outputs the output signals Q2 and /Q2 of the step-up PWM comparator PWM2 as control signals D3 and D4, and outputs the output signals Q1 and /Q1 of the step-down PWM comparator PWM1 as control signals D1 and D2.

When the output signal JDG of the voltage comparator CMP is set to low level and the memory voltage request signal MEM generated by the switch circuit SWM is set to low level (when 1.8V is supplied as the input voltage Vi and the nonvolatile memory 3 When the working voltage needs to be 1.8V), the decoder DEC sets the control signals SWD2 and D6 to low level and sets the control signals SWD1 and D7 to high level. In addition, the decoder DEC outputs the output signal Q2 of the boost PWM comparator PWM2 as the control signal D3 and outputs the output signal /Q2 of the boost PWM comparator PWM2 as the control signals D4 and D5, and outputs the output signal of the step-down PWM comparator PWM1 Output signals Q1 and /Q1 serve as control signals D1 and D2.

Here, the operation of the power supply circuit 2 will be described respectively in four cases: (first mode), 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3; (second mode) ), 3.3V is provided as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3; (third mode), 1.8V is provided as the input voltage Vi and 3.3V is requested as the nonvolatile memory 3 Operating voltage of the memory 3; (fourth mode), 1.8V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3 .

FIG. 4 shows the operation of the power supply circuit 2 (first mode). When 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the control signal D4 is set to low level and the control signal D6 is set to high level. For this reason, the step-up synchronous rectifier circuit T4 is always in the OFF state and the first bypass switch circuit T6 is always in the ON state. Therefore, the input voltage Vi is output as the first output voltage Vo1. In addition, the control signal D7 is fixed at high level. For this reason, the second bypass switch circuit T7 is always in an off state.

The control signals SWD1 and SWD2 are set to low level. Therefore, the switch circuit SW1 connects the connection node of the resistors R3 and R4 to the inverting input pin of the error amplifier ERA1, and the switch circuit SW2 connects the output pin of the voltage generator E2 to the first non-inverting input of the error amplifier ERA1 pins. Since the soft-start capacitor CS is charged by the constant current circuit during the operation of the DC-DC converter CNV, at the error amplifier ERA1, the voltage of the second non-inverting input pin is higher than the voltage of the first non-inverting input pin. Therefore, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the second output voltage Vo2 divided by the resistors R3 and R4 and the reference voltage Ve2 during the operation of the DC-DC converter CNV.

When the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the triangular wave signal TW provided by the triangular wave oscillator OSC, the step-down PWM comparator PWM1 sets the output signal /Q1 to a low level and the output signal Q1 to a high level ; When the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the triangular wave signal TW, the output signal /Q1 is set to a high level and the output signal Q1 is set to a low level. Output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2.

When the voltage of the output signal DF2 of the voltage generator E3 (the voltage obtained by subtracting the offset voltage Ve3 from the output voltage DF1 of the error amplifier ERA1) is higher than the voltage of the triangular wave signal TW supplied by the triangular wave oscillator OSC, the boost The PWM comparator PWM2 sets the output signal /Q2 to a low level and sets the output signal Q2 to a high level; when the voltage of the output signal DF2 of the voltage generator E3 is lower than the voltage of the triangular wave signal TW, the boost PWM comparator PWM2 sets the output signal /Q2 high and sets the output signal Q2 low. The output signals Q2 and /Q2 of the step-up PWM comparator PWM2 are output as control signals D3 and D5.

FIG. 5 shows the operation of buck PWM comparator PWM1 and boost PWM comparator PWM2 (first mode). When 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, since the voltage of the input pin is inverted at the boost PWM comparator PWM2 (the output signal of the voltage generator E3 The voltage of DF2) is always lower than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC), so the output signal Q2 is always set to low level and the output signal /Q2 is always set is high (0% duty cycle state). Since the output signal Q2 of the boost PWM comparator PWM2 is output as the control signal D3, the boost main switching transistor T3 is always in an off state. In addition, since the output signal /Q2 of the boost PWM comparator PWM2 is output as the control signal D5, the boost synchronous rectifier circuit T5 is always on.

On the other hand, at the step-down PWM comparator PWM1, when the voltage of the inverting input pin (the voltage of the output signal DF1 of the error amplifier ERA1) is higher than the voltage of the non-inverting input pin (the triangular wave signal provided by the triangular wave oscillator OSC TW voltage), the output signal Q1 is set to high level, and the output signal /Q1 is set to low level. Since the output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2, when the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the voltage of the triangular wave signal TW, the step-down main switching transistor T1 enters The step-down synchronous rectifier circuit T2 enters the cut-off state.

At the step-down PWM comparator PWM1, when the voltage of the inverting input pin (the voltage of the output signal DF1 of the error amplifier ERA1) is lower than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC) , the output signal Q1 is set to a low level, and the output signal /Q1 is set to a high level. Since the output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2, when the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW, the step-down main switching transistor T1 enters The off state, and the step-down synchronous rectifier circuit T2 enters the on state.

When the step-down main switching transistor T1 enters the on state, the step-down synchronous rectifier circuit T2 enters the off state, and current is supplied from the input side to the load through the choke coil L1. Since the voltage difference between the input voltage Vi and the second output voltage Vo2 is applied to both ends of the choke coil L1, the current flowing through the choke coil L1 increases with the lapse of time, and the current supplied to the load also increases with the lapse of time. increases with the passage of time. In addition, as current flows through the choke coil L1, energy is accumulated in the choke coil L1. Then, when the step-down main switching transistor T1 enters an off state, the step-down synchronous rectifier circuit T2 enters an on state and the energy accumulated in the choke coil L1 is released. Meanwhile, the second output voltage Vo2 is expressed by Expression (1) using the input voltage Vi, the on-period Ton of the step-down main switching transistor T1 , and the off-period Toff of the step-down main switching transistor T1 .

Vo2={Ton/(Ton+Toff)}×Vi...(1)

In addition, the current flowing through the choke coil L1 flows from the input side to the output side during the on period of the step-down main switching transistor T1, and is supplied by the step-down synchronous rectifier circuit T2 during the off period of the step-down main switching transistor T1. current. Therefore, the average input current Ii is expressed by Expression (2) using the output current Io, the on-period Ton of the step-down main switching transistor T1, and the off-period Toff of the step-down main switching transistor T1.

Ii={Ton/(Ton+Toff)}×Io...(2)

Therefore, when the second output voltage Vo2 varies due to the variation of the input voltage Vi, it is possible to maintain the second output voltage Vo2 by detecting the variation of the second output voltage Vo2 to control the ratio of the on-time period and the off-time period of the step-down main switching transistor T1. Second, the output voltage Vo2 remains unchanged. Similarly, when the second output voltage Vo2 changes due to load changes, the second output voltage can also be maintained by detecting the change of the second output voltage Vo2 to control the ratio of the on-time period to the off-time period of the step-down main switching transistor T1. The output voltage Vo2 does not change. In this way, in the DC-DC converter CNV of the PWM control system, the second output voltage Vo2 can be controlled by controlling the ratio of the on-time period and the off-time period of the step-down main switching transistor T1.

Incidentally, at the start of the DC-DC converter CNV, the second output voltage Vo2 is 0V, therefore, the voltage difference between the input voltage Vi and the second output voltage Vo2 becomes maximum, and if it is assumed that, in the error amplifier ERA1 , the voltage of the first non-inverting input pin is lower than the voltage of the second non-inverting input pin, and the voltage of the output signal DF1 of the error amplifier ERA1 also becomes the maximum. In this case, the pulse width (high level period) of the output signal Q1 of the step-down PWM comparator becomes maximum and the conduction period of the step-down main switching transistor T1 becomes maximum. In addition, the energy flowing through the choke coil L1 is expressed by expression (3) using the input voltage Vi, the second output voltage Vo2, the inductance L of the choke coil L1, and the on-time period Ton of the step-down main switching transistor T1. Maximum current Ipeak.

Ipeak={(Vi-Vo2)/L}×Ton...(3)

When the DC-DC converter CNV starts up, the second output voltage Vo2 is 0V, therefore, the voltage applied to the choke coil L1 becomes maximum, and the conduction period of the step-down main switching transistor T1 becomes maximum. Thus, it is known that an excessive inrush current occurs in the choke coil L1 and the step-down main switching transistor T1. This happens because the DC-DC converter CNV tries to abruptly change the second output voltage Vo2 from 0V to the nominal value (1.8V).

However, when the DC-DC converter CNV starts up, the soft-start capacitor CS is gradually charged by the constant current circuit, so that the voltage generated by the soft-start capacitor CS (the voltage of the second non-inverting input pin of the error amplifier ERA1) starts from 0V Gradually rise. Therefore, at the start of the DC-DC converter CNV, the error amplifier ERA1 generates an output signal by amplifying the voltage difference between the voltage of the second output voltage Vo2 divided by the resistors R3 and R4 and the voltage generated by the soft-start capacitor CS DF1. When the DC-DC converter CNV starts, since the second output voltage Vo2 is 0V, the voltage of the output signal DF1 of the error amplifier ERA1 becomes minimum and the pulse width of the output signal Q1 of the step-down PWM comparator PWM1 also becomes minimum . Therefore, the turn-on period of the step-down main switching transistor T1 becomes minimum and inrush current is prevented.

In addition, the voltage generated by the soft start capacitor CS is a voltage that defines the second output voltage Vo2 and gradually rises with a predetermined rising slope. Therefore, the second output voltage Vo2 also rises in proportion thereto. Thus, the rising slope of the second output voltage Vo2 is limited by the rising slope of the voltage generated by the soft-start capacitor CS. When the voltage generated by the soft start capacitor CS rises and becomes higher than the reference voltage Ve2, by amplifying the voltage difference between the second output voltage Vo2 divided by the resistors R3 and R4 and the reference voltage Ve2, the error amplifier ERA1 generates output voltage DF1. Therefore, after the voltage generated by the soft start capacitor CS reaches the reference voltage Ve2, the second output voltage Vo2 is limited by the reference voltage Ve2. By the way, at the termination moment of the DC-DC converter CNV, the soft start capacitor CS is gradually discharged through the discharge resistor and the voltage generated by the soft start capacitor CS gradually drops, and thus, the second output voltage Vo2 can be gradually reduced.

FIG. 6 shows the rising characteristic of the second output voltage Vo2 (first mode). At time t1, when the DC-DC converter CNV is started, the soft-start capacitor CS is gradually charged through the constant current circuit. For this reason, the voltage generated by the soft-start capacitor CS rises with the lapse of time. Accordingly, the second output voltage Vo2 also rises as time elapses. At time t2, when the voltage generated by the soft-start capacitor CS reaches the reference voltage Ve2, thereafter, the second output voltage Vo2 is controlled by the reference voltage Ve2 to remain constant.

FIG. 7 shows the operation of the power supply circuit 2 (second mode). When 3.3V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3, the control signal D6 is set to low level. For this reason, the first bypass switch circuit T6 is always in an off state. In addition, the control signal SWD1 is set to a high level. For this reason, the switch circuit SW1 connects the connection node of the resistors R1 and R2 to the inverting input pin of the error amplifier ERA1. The output signal /Q2 of the step-up PWM comparator PWM2 is output not only as the control signal D5 but also as the control signal D4. Since operations other than this are the same as those in the first mode of the power supply circuit 2 , repeated descriptions will be omitted here.

FIG. 8 shows the operation of the power supply circuit 2 (third mode). When 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the control signals D5 and D7 are set to low level. For this reason, the boost synchronous rectifier circuit T5 is always in the OFF state and the second bypass switch T7 is always in the ON state. Accordingly, the input voltage Vi is output as the first output voltage Vo2. In addition, the control signal D6 is set to a low level. Due to this, the first bypass switch circuit T6 is always in an off state.

The control signals SWD1 and SWD2 are set to high level. Therefore, the switch circuit SW1 connects the connection node of the resistors R1 and R2 to the inverting input pin of the error amplifier ERA1, and the switch circuit SW2 connects the output pin of the voltage generator E1 to the first non-inverting input of the error amplifier ERA1 pins. Since the soft-start capacitor CS is charged by the constant current circuit during the operation of the DC-DC converter CNV, at the error amplifier ERA1, the voltage of the second non-inverting input pin is higher than the voltage of the first non-inverting input pin. Accordingly, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the first output voltage Vo1 divided by the resistors R1 and R2 and the reference voltage Ve1.

When the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the triangular wave signal TW provided by the triangular wave oscillator OSC, the step-down PWM comparator PWM1 sets the output signal /Q1 to a low level and the output signal Q1 to a high level ; When the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW, the output signal /Q1 is set to a high level and the output signal Q1 is set to a low level. Output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2.

When the voltage of the output signal DF2 of the voltage generator E3 (the voltage obtained by subtracting the offset voltage Ve3 from the voltage of the output signal DF1 of the error amplifier ERA1) is higher than the triangular wave signal TW supplied by the triangular wave oscillator OSC, the boost The PWM comparator PWM2 sets the output signal /Q2 to a low level and sets the output signal Q2 to a high level; when the voltage of the output signal DF2 of the voltage generator E3 is lower than the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC , the boost PWM comparator PWM2 sets the output signal /Q2 to a high level and sets the output signal Q2 to a low level. Output signals Q2 and /Q2 of the step-up PWM comparator PWM2 are output as control signals D3 and D4.

FIG. 9 shows the operation of buck PWM comparator PWM1 and boost PWM comparator PWM2 (third mode). When 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, since the voltage of the input pin is inverted at the step-down PWM comparator PWM1 (the output signal DF1 of the error amplifier ERA1 The voltage) is always higher than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC), so the output signal Q1 is always set to high level and the output signal /Q1 is always set to Low level (100% duty cycle state). Since the output signal Q1 of the step-down PWM comparator PWM1 is output as the control signal D1, the step-down main switching transistor T1 is always in an on state. In addition, since the output signal /Q1 of the step-down PWM comparator PWM1 is output as the control signal D2, the step-down synchronous rectifier circuit T2 is always in an off state.

On the other hand, at the step-up PWM comparator PWM2, when the voltage of the inverting input pin (the voltage of the output signal DF2 of the voltage generator E3) is higher than the voltage of the non-inverting input pin (the triangular wave provided by the triangular wave oscillator OSC When the voltage of the signal TW), the output signal Q2 is set to a high level, and the output signal /Q2 is set to a low level. Since the output signals Q2 and /Q2 of the boost PWM comparator PWM2 are output as control signals D3 and D4, when the voltage of the output signal DF2 of the voltage generator E3 is higher than the voltage of the triangular wave signal TW, the boost main switching transistor T3 enters the conduction state, and the step-up synchronous rectifier circuit T4 enters the cut-off state.

At the step-up PWM comparator PWM2, when the voltage of the inverting input pin (the voltage of the output signal DF2 of the voltage generator E3) is lower than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC ), the output signal Q2 is set to low level, and the output signal /Q2 is set to high level. Since the output signals Q2 and /Q2 of the boost PWM comparator PWM2 are output as control signals D3 and D4, when the voltage of the output signal DF2 of the voltage generator E3 is lower than the voltage of the triangular wave signal TW, the boost main switching transistor T3 enters the cut-off state, and the step-up synchronous rectifier circuit T4 enters the conduction state.

When the boost main switching transistor T3 enters the on state, the boost synchronous rectifier circuit T4 enters the off state, and current is supplied from the input side to the choke coil L1. Since the input voltage Vi is applied to both ends of the choke coil L1, the current flowing through the choke coil L1 increases with the lapse of time, and the current supplied to the load also increases with the lapse of time. In addition, as current flows through the choke coil L1, energy is accumulated in the choke coil L1. Then, when the boost main switching transistor T3 enters the OFF state, the boost synchronous rectifier circuit T4 enters the ON state and the energy accumulated in the choke coil L1 is discharged.

During the conduction period of the boost main switching transistor T3, the current IL flowing through the choke coil L1 is given by the expression using the input voltage Vi, the inductance L of the choke coil L1, and the conduction period Ton of the boost main switching transistor T3 (4) Expressed and increased over time.

IL=(Vi/L)×Ton...(4)

In addition, during the turn-off period of the boost main switching transistor T3, the current IL flowing through the choke coil L1 is controlled by using the input voltage Vi, the first output voltage Vo1, the inductance L of the choke coil L1, and the turn-off of the boost main switching transistor T3. The expression (5) of the time period Toff is expressed, and decreases with the lapse of time.

IL={(Vo1-Vi)/L}×Toff...(5)

Since the current IL in the expression (4) is equal to the current IL in the expression (5), the first output voltage Vo1 is boosted by using the input voltage Vi, the conduction period Ton of the step-up main switching transistor T3, and Expression (6) of the off-period Toff of the main switching transistor T3 is expressed.

Vo1={(Ton+Toff)/Toff)×Vi...(6)

Therefore, when the first output voltage Vo1 varies due to the variation of the input voltage Vi, it is possible to maintain the first output voltage Vo1 by detecting the variation of the first output voltage Vo1 to control the ratio of the on-time period and the off-time period of the boost main switching transistor T3. - The output voltage Vo1 remains unchanged. Similarly, when the first output voltage Vo1 changes due to load changes, the first output voltage can also be maintained by controlling the ratio of the on-time period to the off-time period of the boost main switching transistor T3 by detecting the change in the first output voltage Vo1. The output voltage Vo1 does not change. In this way, in the DC-DC converter CNV of the PWM control system, the first output voltage Vo1 can be controlled by controlling the ratio of the on-time period and the off-time period of the boost main switching transistor T3.

Incidentally, when the DC-DC converter CNV is activated, if it is assumed that the voltage of the first non-inverting input pin at the error amplifier ERA1 is lower than the voltage of the second non-inverting input pin, the input pin of the power supply circuit 2 IN and the first output pin OUT1 are connected through the step-up synchronous rectifier circuit T4, then the input voltage Vi flows as the first output voltage Vo1, and an excessive inrush current occurs. In addition, since the input voltage Vi flows as the first output voltage Vo1, the rising characteristic of the first output voltage Vo1 will be similar to that shown in FIG. 10 . Therefore, it is impossible to control to raise the first output voltage Vo1 from 0V to a rated value (3.3V) at a predetermined time.

However, since the voltage generated by the soft-start capacitor CS is supplied to the second non-inverting input pin of the error amplifier ERA1, the DC-DC converter CNV starts up as a step-down DC-DC converter, which will be described later, and When the first output voltage Vo1 becomes equal to the input voltage Vi, it converts into a step-up DC-DC converter. Therefore, the inrush current can be prevented and the rising slope of the first output voltage Vo1 can be controlled.

FIG. 11 shows the operation of the buck PWM comparator PWM1 and the boost PWM comparator PWM2 when the DC-DC converter CNV is started (third mode). When the DC-DC converter CNV starts up, the soft-start capacitor CS is gradually charged by the constant current circuit, so that the voltage generated by the soft-start capacitor CS (the voltage of the second non-inverting input pin of the error amplifier ERA1) gradually rises from 0V. Therefore, at the start of the DC-DC converter CNV, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the voltage of the first output voltage Vo1 divided by the resistors R1 and R2 and the voltage generated by the soft-start capacitor CS .

At this time, because the voltage of the inverting input pin of the step-up PWM comparator PWM2 (the voltage of the output signal DF2 of the voltage generator E3) is always lower than the voltage of the non-inverting input pin (the triangular wave provided by the triangular wave oscillator OSC The voltage of the signal TW), so the output signal Q2 is always set to low level and the output signal /Q2 is always set to high level (0% duty cycle state). Since the output signal Q2 of the boost PWM comparator PWM2 is output as the control signal D3, the boost main switching transistor T3 is always in an off state. In addition, since the output signal /Q2 of the boost PWM comparator PWM2 is output as the control signal D5, the boost synchronous rectifier circuit T5 is always on.

On the other hand, at the step-down PWM comparator PWM1, when the voltage of the inverting input pin (the voltage of the output signal DF1 of the error amplifier ERA1) is higher than the voltage of the non-inverting input pin (the triangular wave signal provided by the triangular wave oscillator OSC TW voltage), the output signal Q1 is set to high level, and the output signal /Q1 is set to low level. Since the output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2, when the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the voltage of the triangular wave signal TW, the step-down main switching transistor T1 enters The step-down synchronous rectifier circuit T2 enters the cut-off state.

At the step-down PWM comparator PWM1, when the voltage of the inverting input pin (the voltage of the output signal DF1 of the error amplifier ERA1) is lower than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC) , the output signal Q1 is set to a low level, and the output signal /Q1 is set to a high level. Since the output signals Q1 and /Q1 of the step-down PWM comparator PWM1 are output as control signals D1 and D2, when the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW, the step-down main switching transistor T1 enters The off state, and the step-down synchronous rectifier circuit T2 enters the on state.

When the DC-DC converter CNV starts, the first output voltage Vo1 is 0V, so the voltage of the output signal DF1 of the error amplifier ERA1 becomes the minimum, and the pulse width of the output signal Q1 of the step-down PWM comparator PWM1 also becomes the minimum . Therefore, the turn-on period of the step-down main switching transistor T1 becomes minimum and inrush current is prevented. In addition, the voltage generated by the soft start capacitor CS is a voltage that defines the first output voltage Vo1 and gradually rises with a predetermined rising slope. Therefore, the first output voltage Vo1 also increases in proportion thereto. Thus, the rising slope of the first output voltage Vo1 is limited by the rising slope of the voltage generated by the soft-start capacitor CS.

When the voltage generated by the soft start capacitor CS becomes higher than the voltage at which the first output voltage Vo1 is equal to the input voltage Vi, the voltage of the output voltage DF1 of the error amplifier ERA1 becomes higher than that of the triangular wave signal TW. Because the voltage at the inverting input pin of the step-down PWM comparator PWM1 (the voltage of the output signal DF1 of the error amplifier ERA1) is always higher than the voltage supplied to the non-inverting input pin (the triangular wave signal TW provided by the triangular wave oscillator OSC voltage), so the output signal Q1 is always set to high level and the output signal /Q1 is always set to low level (100% duty cycle state). Since the output signal Q1 of the step-down PWM comparator PWM1 is output as the control signal D1, the step-down main switching transistor T1 is always in an on state. In addition, since the output signal /Q1 of the step-down PWM comparator PWM1 is output as the control signal D2, the step-down synchronous rectifier circuit T2 is always in an off state.

On the other hand, when the voltage generated by the soft-start capacitor CS becomes higher than the voltage at which the first output voltage Vo1 is equal to the input voltage Vi, the voltage of the output signal DF2 of the voltage generator E3 (by the output signal from the error amplifier ERA1 The voltage obtained by subtracting the bias voltage Ve3 from the voltage of DF1 intersects with the triangular wave signal TW. At the step-up PWM comparator PWM2, when the voltage of the inverting input pin (the voltage of the output signal DF2 of the voltage generator E3) is higher than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC ), the output signal Q2 is set to a high level, and the output signal /Q2 is set to a low level. Since the output signals Q2 and /Q2 of the boost PWM comparator PWM2 are output as control signals D3 and D4, when the voltage of the output signal DF2 of the voltage generator E3 is higher than the voltage of the triangular wave signal TW, the boost main switching transistor T3 enters the conduction state, and the step-up synchronous rectifier circuit T4 enters the cut-off state.

At the step-up PWM comparator PWM2, when the voltage of the inverting input pin (the voltage of the output signal DF2 of the voltage generator E3) is lower than the voltage of the non-inverting input pin (the voltage of the triangular wave signal TW provided by the triangular wave oscillator OSC ), the output signal Q2 is set to low level, and the output signal /Q2 is set to high level. Since the output signals Q2 and /Q2 of the boost PWM comparator PWM2 are output as control signals D3 and D4, when the voltage of the output signal DF2 of the voltage generator E3 is lower than the voltage of the triangular wave signal TW, the boost main switching transistor T3 enters the cut-off state, and the step-up synchronous rectifier circuit T4 enters the conduction state.

When the voltage generated by the soft-start capacitor CS rises and becomes higher than the reference voltage Ve1, the error amplifier ERA1 generates output voltage DF1. Therefore, when the voltage generated by the soft start capacitor CS has reached the reference voltage Ve1, the first output voltage Vo1 is limited by the reference voltage Ve1. By the way, at the termination moment of the DC-DC converter CNV, the soft start capacitor CS is gradually discharged through the discharge resistor and the voltage generated by the soft start capacitor CS gradually drops, so that the first output voltage Vo1 can be gradually reduced.

FIG. 12 shows the rising characteristic of the first output voltage Vo1 (third mode). At time t1, when the DC-DC converter CNV is started, the soft-start capacitor CS is gradually charged through the constant current circuit. Due to this, the voltage provided by the soft-start capacitor CS rises with the lapse of time. Accordingly, the first output voltage Vo1 also increases with time. During this period, the DC-DC converter CNV works as a step-down DC-DC converter.

At time t2, when the voltage generated by the soft-start capacitor CS becomes higher than the voltage at which the first output voltage Vo1 is equal to the input voltage Vi, the DC-DC converter CNV switches from a step-down DC-DC converter to a boost type DC-DC converter. The first output voltage Vo1 continues to rise as the voltage generated by the soft-start capacitor CS rises. At time t3, when the voltage generated by the soft-start capacitor CS has reached the reference voltage Ve1, thereafter, the first output voltage Vo1 is controlled by the reference voltage Ve1 to remain unchanged.

FIG. 13 shows the operation of the power supply circuit 2 (fourth mode). When 1.8V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3, the control signal D7 is fixed at a high level. Due to this, the second bypass switch circuit T7 is always in an off state. In addition, the control signal SWD2 is fixed at low level. Thus, the switch circuit SW2 connects the output pin of the voltage generator E2 to the first non-inverting input pin of the error amplifier ERA1. The output signal /Q2 of the step-up PWM comparator PWM2 is output not only as the control signal D4 but also as the control signal D5. Since the operation otherwise is the same as that in the third mode of the power supply circuit 2, a repeated description will be omitted here.

Fig. 14 shows the construction of the decoder DEC. The decoder DEC is constructed to include a resistor R7, gate circuits G1 to G5, and an output slope control circuit SC in order to realize the operation shown in FIG. 3 . One pin of the resistor R7 is connected to a power supply line of the power supply voltage Vh of the logic circuit (the voltage of the input voltage Vi is boosted by a charge pump circuit or the like). The other pin of the resistor R7 is connected to the switch circuit SWM (FIG. 2) through the signal line of the memory voltage request signal MEM. Therefore, when the switch circuit SWM is in the off state, the memory voltage request signal MEM is set to a high level, and when the switch circuit SWM is in an on state, the memory voltage request signal MEM is set to a low level.

When the output signal JDG of the voltage comparator CMP is set to a high level and the memory voltage request signal MEM is set to a high level (when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the input voltage of the nonvolatile memory 3 operating voltage), the gate circuit G1 sets the control signal SWD1 to a low level. In other cases, the gate circuit G1 sets the control signal SWD1 to a high level.

When the output signal JDG of the voltage comparator CMP is set to low level and the memory voltage request signal MEM is set to high level (when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the input voltage of the nonvolatile memory 3 operating voltage), the gate circuit G2 sets the control signal SWD2 to a high level. In other cases, the gate circuit G2 sets the control signal SWD2 to a low level.

When the output signal of the gate circuit G1 is set to low level (when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3), the gate circuit G3 sets the control signal D4 to low level. When the output signal of the gate circuit G1 is set to a high level, the gate circuit G3 outputs the output signal /Q2 of the boost PWM comparator PWM2 as the control signal D4.

When the output signal JDG of the voltage comparator CMP is set to low level and the memory voltage request signal MEM is set to high level (when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the input voltage of the nonvolatile memory 3 operating voltage), the gate circuit G4 sets the output signal to a low level. In other cases, gate G4 sets the output signal to high level.

When the output signal of the gate circuit G4 is set to low level (when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3), the gate circuit G5 sets the control signal D5 to low level. When the output signal of the gate circuit G4 is set to a high level, the gate circuit G5 outputs the output signal /Q2 of the boost PWM comparator PWM2 as the control signal D5.

When the output signal (control signal SWD1) of the gate circuit G1 is set to low level (when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory), the output slope control circuit SC Set the control signal D6 to a high level. Incidentally, as will be described later using FIG. 15, when the output signal of the gate circuit G1 is set to low level, the output slope circuit SC controls the voltage of the control signal D6 so as to realize the first output voltage Vo1 and the second output voltage Simultaneous activation of Vo2. When the output signal of the gate circuit G1 is set to a high level, the output slope control circuit SC sets the control signal D6 to a low level.

When the output signal (control signal SWD2) of the gate circuit G2 is set to high level (when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory), the output slope control circuit SC Set the control signal D7 to low level. Incidentally, as will be described later using FIG. 15, when the output signal of the gate circuit G2 is set to a high level, the output slope circuit SC controls the voltage of the control signal D7 so as to realize the first output voltage Vo1 and the second output voltage Simultaneous activation of Vo2. When the output signal of the gate circuit G2 is set to a low level, the output slope control circuit SC sets the control signal D7 to a high level.

FIG. 15 shows the configuration of the output slope control circuit SC. Fig. 16 shows the simultaneous activation of the first output voltage Vo1 and the second output voltage Vo2. The output slope control circuit SC is configured to include resistors R11 to R15, switch circuits SW11 and SW12, error amplifiers ERA11 and ERA12, and transistors T11 to T13. One pin of the resistor R11 is connected to the first output pin OUT1 of the power supply circuit 2 . The other pin of the resistor R11 is connected to one pin of the resistor R12. The other leg of resistor R12 is connected to ground.

When the output signal (control signal SWD1) of the gate circuit G1 is set to low level (3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3), the switch circuit SW11 turns the power supply circuit The second output pin OUT2 of 2 is connected to the non-inverting input pin of the error amplifier ERA11. When the output signal of the gate circuit G1 is set to a high level, the switch circuit SW11 connects the ground line to the non-inverting input pin of the error amplifier ERA11.

The error amplifier ERA11 receives the voltage of the connection node of the resistors R11 and R12 (a voltage in which the first output voltage Vo1 is divided by the resistors R11 and R12 ) at an inverting input pin, and receives a voltage supplied through the switch circuit SW11 . The error amplifier ERA11 generates an output signal by amplifying the voltage difference between the voltage of the connection node of the resistors R11 and R12 and the voltage supplied through the switch circuit SW11. The resistor R13 and the transistor T11 (n-type transistor) are connected in series between the power supply line for the power supply voltage Vh of the logic circuit and the ground line. The control pin of the transistor T11 receives the output signal of the error amplifier ERA11. The transistor T12 (p-type transistor) and the resistor R14 are connected in series between the power supply line for the power supply voltage Vh of the logic circuit and the ground line. The control pin of the transistor T12 is connected to the connection node of the resistor R13 and the transistor T11. The connection node of the transistor T12 and the resistor R14 is connected to the control pin of the first bypass switch circuit T6. In other words, the signal generated at the connection node of the transistor T12 and the resistor R14 is supplied as the control signal D6 to the control pin of the first bypass switch circuit T6.

When the output signal (control signal SWD2) of the gate circuit G2 is set to high level (1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3), the switch circuit SW12 turns the resistor The connection node of R11 and R12 is connected to the non-inverting input pin of the error amplifier ERA12. When the output signal of the gate circuit G2 is set to a low level, the switch circuit SW12 connects the ground line to the non-inverting input pin of the error amplifier ERA12.

The error amplifier ERA12 receives the second output voltage Vo2 at the inverting input pin and receives the voltage provided via the switch circuit SW12 at the non-inverting input pin. The error amplifier ERA12 generates an output signal by amplifying the voltage difference between the second output voltage Vo2 and the voltage supplied via the switch circuit SW12. The resistor R15 and the transistor T13 (n-type transistor) are connected in series between the input pin IN of the power supply circuit 2 and the ground. The control pin of the transistor T13 receives the output signal of the error amplifier ERA12. A connection node of the resistor R15 and the transistor T13 is connected to a control pin of the second bypass switch circuit T7. In other words, the signal generated at the connection node of the resistor R15 and the transistor T13 is supplied as the control signal D7 to the control pin of the second bypass switch circuit T7.

In the output slope control circuit SC having the above configuration, when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the second output voltage Vo2 is supplied to the The non-inverting input pin of the error amplifier ERA11. Accordingly, the error amplifier ERA11 generates an output signal by amplifying the voltage difference between the voltage of the first output voltage Vo1 divided by the resistors R11 and R12 and the second output voltage Vo2.

When the second output voltage Vo2 (the voltage of the non-inverting input pin of the error amplifier ERA11) does not change, if the voltage of the first output voltage Vo1 divided by the resistors R11 and R12 (the voltage of the inverting input pin of the error amplifier ERA11 ) becomes lower than the second output voltage Vo2, the voltage of the output signal of the error amplifier ERA11 rises, therefore, the voltage of the connection node of the resistor R13 and the transistor T11 drops, and as a result, the voltage of the connection node of the transistor T12 and the resistor R14 (The voltage of the control signal D6) rises. When the voltage of the control signal D6 rises, since the on-resistance of the first bypass switch circuit T6 becomes smaller, the first output voltage Vo1 rises.

When the first output voltage Vo1 rises so that the voltage of the first output voltage Vo1 divided by the resistors R11 and R12 approaches the second output voltage Vo2, the voltage of the output signal of the error amplifier ERA11 drops, and thus the connection of the resistor R13 and the transistor T11 The voltage at the node rises, and as a result, the voltage at the node connecting the transistor T12 and the resistor R14 (the voltage of the control signal D6 ) falls. When the voltage of the control signal D6 drops, the first output voltage Vo1 drops because the on-resistance of the first bypass switch circuit T6 becomes larger.

In addition, when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the ground voltage (0V) is supplied to the non-inverting input pin of the error amplifier ERA12 through the switch circuit SW12. In the error amplifier ERA12, when the voltage of the non-inverting input pin is set to 0V, the voltage of the output signal is set to 0V regardless of the voltage of the inverting input pin. Therefore, the control signal D7 is set to a high level by the drive circuit composed of the resistor R15 and the transistor T13, and the second bypass switch circuit T7 enters an off state.

In this way, when 3.3V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the first bypass switch circuit T6 functions as a linear regulator to This makes the first output voltage Vo1 unchanged relative to the second output voltage Vo2 (the voltage of the non-inverting input pin of the error amplifier ERA11 ). Therefore, when the second output voltage Vo2 gradually rises when the DC-DC converter CNV starts up, the voltage of the non-inverting input pin of the error amplifier ERA11 rises, and thus the first output voltage Vo1 also rises. As a result, as shown in FIG. 16, simultaneous activation of the first output voltage Vo1 and the second output voltage Vo2 is achieved.

When 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the ground voltage (0V) is supplied to the non-inverting input pin of the error amplifier ERA11 through the switch circuit SW11. In the error amplifier ERA11, when the voltage of the non-inverting input pin is set to 0V, the voltage of the output signal is set to 0V regardless of the voltage of the inverting input pin. Therefore, the control signal D6 is set to a low level by the drive circuit composed of the resistors R13 and R14 and the transistors T11 and T12, and the second bypass switch circuit T6 enters an off state.

Also, when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the voltage of the connection node of the resistors R11 and R12 (the first output voltage Vo1 is obtained by the resistors R11 and R12 The divided voltage) is supplied to the non-inverting input pin of the error amplifier ERA12 through the switch circuit SW12. Accordingly, the error amplifier ERA12 generates an output signal by amplifying the voltage difference between the second output voltage Vo2 and the voltage divided by the first output voltage Vo1 by R11 and R12.

When the first output voltage Vo1 is divided by the resistors R11 and R12 (the voltage of the non-inverting input pin of the error amplifier ERA12) does not change, if the second output voltage Vo2 (the voltage of the inverting input pin of the error amplifier ERA12 ) becomes lower than the voltage at which the first output voltage Vo1 is divided by the resistors R11 and R12, the voltage of the output signal of the error amplifier ERA12 rises, and therefore, the voltage of the connection node between the resistor R15 and the transistor T13 (the voltage of the control signal D7 voltage) drops. When the voltage of the control signal D7 decreases, the on-resistance of the second bypass switch circuit T7 decreases, and thus the second output voltage Vo2 increases.

When the second output voltage Vo2 rises so that the second output voltage Vo2 approaches the voltage at which the first output voltage Vo1 is divided by the resistors R11 and R12, the voltage of the output signal of the error amplifier ERA12 drops, so that the connection of the resistor R15 and the transistor T13 The voltage of the node (the voltage of the control signal D7) rises. When the voltage of the control signal D7 increases, the second output voltage Vo2 decreases because the on-resistance of the second bypass switch circuit T7 increases.

In this way, when 1.8V is supplied as the input voltage Vi and 3.3V is requested as the operating voltage of the nonvolatile memory 3, the second bypass switch circuit T7 functions as a linear voltage regulator so that the second The output voltage Vo2 is unchanged from the voltage divided by the resistors R11 and R12 (the voltage of the non-inverting input pin of the error amplifier ERA12 ) with respect to the first output voltage Vo1 . Therefore, when the first output voltage Vo1 gradually rises when the DC-DC converter CNV starts up, the voltage of the non-inverting input pin of the error amplifier ERA12 rises, and thus, the second output voltage Vo2 also rises. As a result, as shown in FIG. 16, simultaneous activation of the first output voltage Vo1 and the second output voltage Vo2 is achieved.

In the above-mentioned embodiment of the present invention, the DC-DC converter CNV, the first bypass switch circuit T6, and the second bypass switch circuit T7 can be configured according to the voltage value of the input voltage Vi and the voltage value of the first output pin OUT1. The DC-DC converter CNV is shared between the nonvolatile memory 3 and the memory card control circuit 4 by combining the required voltage value (the voltage value of the operating voltage of the nonvolatile memory 3), and thereby reducing the DC-DC converter CNV. The number of DC converters.

In addition, when the DC-DC converter CNV is operated as a step-up DC-DC converter, by making the DC-DC converter CNV, from when the DC-DC converter CNV is activated until the DC-DC converter CNV In the process until the output voltage (the first output voltage Vo1) becomes equal to the input voltage Vi, as a step-down DC-DC converter, the voltage value of the input voltage Vi and the first output pin OUT1 require Combinations of voltage values are irrelevant to reliably prevent inrush current, and make it possible to control the rising slope of the first output voltage Vo1 from 0V to 3.3V. In addition, the simultaneous operation of the voltage Vo1 of the first output pin and the voltage Vo2 of the second output pin can be achieved by combining the first bypass switch circuit T6 and the second bypass switch circuit T7 with the DC-DC converter CNV. activation. Therefore, the risk of burnout caused by the latch-up effect of the semiconductor device constituting the nonvolatile memory 3 or the memory card control circuit 4 using the first output voltage Vo1 as a power supply voltage can be avoided. The memory card control circuit 4 uses the second output voltage Vo2 as a power supply voltage. In this way, it is possible to realize that the operating voltage of the memory card 1 is independent of the operating voltage of the internal nonvolatile memory 3 while ensuring efficiency and safety.

Incidentally, in the embodiment of the present invention described above, an example was described in which the switch circuit SW1 connected the connection node of the resistors R1 and R2 to the inverting input pin of the error amplifier ERA1, in which the following case was considered, that , when 3.3V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3 (second mode), the change of the first output voltage Vo1 (the power supply voltage of the nonvolatile memory 3) becomes larger than the change in the second output voltage Vo2 (power supply voltage of the memory card control circuit 4), however, the present invention is not limited to this embodiment. For the switch circuit SW1, when 3.3V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3 and if the difference between the variation of the first output voltage Vo1 and the variation of the second output voltage Vo2 is small Hours, the connection node of resistors R3 and R4 can also be connected to the inverting input pin of the error amplifier ERA1.

Similarly, in the embodiment of the present invention described above, an example was described in which the switch circuit SW1 connects the connection node of the resistors R1 and R2 to the inverting input pin of the error amplifier ERA1, in which the following case is considered, that is, When 1.8V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3 (fourth mode), the variation of the first output voltage Vo1 (power supply voltage of the nonvolatile memory 3) becomes However, the present invention is not limited to this embodiment. For the switch circuit SW1, when 1.8V is supplied as the input voltage Vi and 1.8V is requested as the operating voltage of the nonvolatile memory 3 and if the difference between the variation of the first output voltage Vo1 and the variation of the second output voltage Vo2 is small Hours, the connection node of resistors R3 and R4 can also be connected to the inverting input pin of the error amplifier ERA1.

Claims (10)

1. A power supply circuit, comprising: an input pin receiving a voltage of a first predetermined value or a voltage of a second predetermined value less than the first predetermined value; The first output pin is used to output the voltage of the first or second predetermined value; a second output pin, configured to output a voltage of the second predetermined value; a DC-DC converter, the DC-DC converter, according to the combination of the voltage value of the input pin and the voltage value required by the first output pin, from the input pin in buck mode or boost mode generating an output voltage at a voltage of , and outputting the output voltage to at least one of said first and second output pins; A first bypass switch circuit that is turned on to output the voltage of the input pin to the first output pin when the voltage is not output from the DC-DC converter to the first output pin. the first output pin; The second bypass switch circuit is turned on to output the voltage of the input pin to the second output pin when the voltage is not output from the DC-DC converter to the second output pin. the second output pin; a startup control circuit that causes the DC-DC converter to operating in said buck mode regardless of the combination of the voltage value at said input pin and the desired voltage value at said first output pin; and an output slope control circuit, when the first bypass switch circuit is turned on, the rising slope of the output voltage of the first bypass switch circuit is synchronized with the rising slope of the output voltage of the DC-DC converter, when the When the second bypass switch circuit is turned on, the rising slope of the output voltage of the second bypass switch circuit is synchronized with the rising slope of the output voltage of the DC-DC converter, Wherein, the DC-DC converter: When the voltage value of the input pin is a first predetermined value and the voltage value required by the first output pin is the first predetermined value, in the step-down mode, from the input pin generating an output voltage of the second predetermined value and outputting the output voltage to the second output pin; When the voltage value of the input pin is the first predetermined value and the voltage value required by the first output pin is the second predetermined value, in the step-down mode from the input pin The voltage of the pin produces the output voltage of the second predetermined value, and outputs the output voltage to the first and second output pins; When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the first predetermined value, in the boost mode from the input pin pin produces an output voltage of the first predetermined value, and outputs the output voltage to the first output pin; and When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the second predetermined value, in the boost mode, from the input pin pin to generate an output voltage of the second predetermined value, and output the output voltage to the first and second output pins. 2. The power supply circuit as claimed in claim 1, wherein, The output slope control circuit includes: A first on-resistance control circuit, when the first bypass switch circuit is turned on, detects a voltage difference between a voltage following the voltage of the first output pin and a voltage of the second output pin , and controlling the on-resistance of the first bypass switch circuit according to the detection result; and The second on-resistance control circuit detects the voltage difference between the voltage of the second output pin and the voltage following the voltage of the first output pin when the second bypass switch circuit is turned on, And according to the detection result, the on-resistance of the second bypass switch circuit is controlled. 3. The power supply circuit as claimed in claim 1, wherein, The power supply circuit is mounted on a memory card having a nonvolatile memory and a memory control circuit controlling the nonvolatile memory; the voltage of the first output pin is used as a power supply voltage of the non-volatile memory; and The voltage of the second output pin is used as a power supply voltage of the memory control circuit. 4. The power supply circuit as claimed in claim 1, wherein, The power supply circuit is constructed using semiconductor devices. 5. A power control circuit used in a power circuit, the power control circuit comprising: an input pin receiving a voltage of a first predetermined value or a voltage of a second predetermined value less than the first predetermined value; The first output pin is used to output the voltage of the first or second predetermined value; a second output pin, configured to output a voltage of the second predetermined value; a DC-DC converter, the DC-DC converter, according to the combination of the voltage value of the input pin and the voltage value required by the first output pin, from the input pin in buck mode or boost mode generating an output voltage at a voltage of , and outputting the output voltage to at least one of said first and second output pins; A first bypass switch circuit that is turned on to output the voltage of the input pin to the first output pin when the voltage is not output from the DC-DC converter to the first output pin. the first output pin; and The second bypass switch circuit is turned on to output the voltage of the input pin to the second output pin when the voltage is not output from the DC-DC converter to the second output pin. The second output pin, the power control circuit includes: a startup control circuit that causes the DC-DC converter to operating in said buck mode regardless of the combination of the voltage value at said input pin and the desired voltage value at said first output pin; and an output slope control circuit, when the first bypass switch circuit is turned on, the rising slope of the output voltage of the first bypass switch circuit is synchronized with the rising slope of the output voltage of the DC-DC converter, when the When the second bypass switch circuit is turned on, the rising slope of the output voltage of the second bypass switch circuit is synchronized with the rising slope of the output voltage of the DC-DC converter, Wherein, the DC-DC converter: When the voltage value of the input pin is a first predetermined value and the voltage value required by the first output pin is the first predetermined value, in the step-down mode, from the input pin generating an output voltage of the second predetermined value and outputting the output voltage to the second output pin; When the voltage value of the input pin is the first predetermined value and the voltage value required by the first output pin is the second predetermined value, in the step-down mode from the input pin The voltage of the pin produces the output voltage of the second predetermined value, and outputs the output voltage to the first and second output pins; When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the first predetermined value, in the boost mode from the input pin pin produces an output voltage of the first predetermined value, and outputs the output voltage to the first output pin; and When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the second predetermined value, in the boost mode, from the input pin pin to generate an output voltage of the second predetermined value, and output the output voltage to the first and second output pins. . 6. The power control circuit as claimed in claim 5, wherein, The output slope control circuit includes: A first on-resistance control circuit, when the first bypass switch circuit is turned on, detects a voltage difference between a voltage following the voltage of the first output pin and a voltage of the second output pin , and controlling the on-resistance of the first bypass switch circuit according to the detection result; and The second on-resistance control circuit detects the voltage difference between the voltage of the second output pin and the voltage following the voltage of the first output pin when the second bypass switch circuit is turned on, And according to the detection result, the on-resistance of the second bypass switch circuit is controlled. 7. The power control circuit as claimed in claim 5, wherein, The power supply circuit is mounted on a memory card having a nonvolatile memory and a memory control circuit controlling the nonvolatile memory; the voltage of the first output pin is used as a power supply voltage of the non-volatile memory; and The voltage of the second output pin is used as a power supply voltage of the memory control circuit. 8. A power control method for controlling a power circuit, the power circuit comprising: an input pin receiving a voltage of a first predetermined value or a voltage of a second predetermined value less than the first predetermined value; The first output pin is used to output the voltage of the first or second predetermined value; a second output pin, configured to output a voltage of the second predetermined value; a DC-DC converter, the DC-DC converter, according to the combination of the voltage value of the input pin and the voltage value required by the first output pin, from the input pin in buck mode or boost mode generating an output voltage at a voltage of , and outputting the output voltage to at least one of said first and second output pins; A first bypass switch circuit, when the voltage is not output from the DC-DC converter to the first output pin, the first bypass switch circuit is turned on to output the voltage of the input pin to the first output pin the first output pin; and The second bypass switch circuit is turned on to output the voltage of the input pin to the second output pin when the voltage is not output from the DC-DC converter to the second output pin. the second output pin, Wherein, the DC-DC converter: When the voltage value of the input pin is a first predetermined value and the voltage value required by the first output pin is the first predetermined value, in the step-down mode, from the input pin generating an output voltage of the second predetermined value and outputting the output voltage to the second output pin; When the voltage value of the input pin is the first predetermined value and the voltage value required by the first output pin is the second predetermined value, in the step-down mode, from the input pin The voltage of the pin produces the output voltage of the second predetermined value, and outputs the output voltage to the first and second output pins; When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the first predetermined value, in the boost mode from the input pin pin produces an output voltage of the first predetermined value, and outputs the output voltage to the first output pin; and When the voltage value of the input pin is the second predetermined value and the voltage value required by the first output pin is the second predetermined value, in the boost mode, from the input pin pin voltage to generate an output voltage of the second predetermined value, and output the output voltage to the first and second output pins, The methods include: a start-up control step of causing the DC-DC converter to operating in said buck mode regardless of the combination of the voltage value at said input pin and the desired voltage value at said first output pin; and The output slope control step is to synchronize the rising slope of the output voltage of the first bypass switch circuit with the rising slope of the output voltage of the DC-DC converter when the first bypass switch circuit is turned on. When the second bypass switch circuit is turned on, the rising slope of the output voltage of the second bypass switch circuit is synchronized with the rising slope of the output voltage of the DC-DC converter. 9. The power control method as claimed in claim 8, wherein, The output slope control step comprises: A first on-resistance control step of detecting a voltage difference between a voltage following the voltage of the first output pin and a voltage of the second output pin when the first bypass switch circuit is turned on , and controlling the on-resistance of the first bypass switch circuit according to the detection result; and The second on-resistance control step is to detect the voltage difference between the voltage of the second output pin and the voltage following the voltage of the first output pin when the second bypass switch circuit is turned on, And according to the detection result, the on-resistance of the second bypass switch circuit is controlled. 10. The power control method as claimed in claim 8, wherein, The power supply circuit is mounted on a memory card having a nonvolatile memory and a memory control circuit controlling the nonvolatile memory; the voltage of the first output pin is used as a power supply voltage of the non-volatile memory; and The voltage of the second output pin is used as a power supply voltage of the memory control circuit.

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