CN100550424C - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device, comprising: a MIS type field effect transistor, comprising: a semiconductor bump protruding from a substrate plane; a gate electrode extending from the top surface to opposite side surfaces of the semiconductor bump on the semiconductor bump; a gate insulating film between the gate electrode and the semiconductor bump, and a source region and a drain region provided in the semiconductor bump; an interlayer insulating film provided over a substrate including a transistor; and a buried conductor interconnect formed by filling the trench in the interlayer insulating film with a conductor; wherein the buried conductor interconnect connects one of the source region and the drain region of the semiconductor bump with the other conductive portion under the interlayer insulating film.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device comprising an MIS type field effect transistor having a gate on a semiconductor raised portion raised from a substrate plane, and A method of producing such a semiconductor device.

Background technique

In recent years, a so-called Fin-type MISFET has been proposed as one type of MIS field effect transistor (hereinafter referred to as "MISFET"). The Fin-type MISFET has a rectangular parallelepiped semiconductor protrusion on which the gate extends from one side across the top surface to the opposite side of the semiconductor protrusion. The gate insulating film is located between the rectangular parallelepiped semiconductor raised portion and the gate, and the channel is basically formed along two opposite sides of the rectangular parallelepiped semiconductor raised portion. It is well known that such a Fin-type MISFET is beneficial to miniaturization because the channel width can be arranged in a direction perpendicular to the substrate plane, and in addition, the Fin-type MISFET is beneficial to improvement of various characteristics such as cut-off characteristics and carrier mobility. improvement, as well as reduction of short channel effects and punch-through phenomena.

As such a Fin type MISFET, Japanese Patent Publication No. 64-8670 (Patent Document 1) discloses a MOS Field Effect Transistor (MOSFET) characterized in that a semiconductor raised portion including a source region, a drain region and a channel region It has a cuboid shape with two opposite sides almost perpendicular to the plane of the wafer substrate, the cuboid raised portion has a height greater than the width, and the gate extends in a direction perpendicular to the plane of the wafer substrate.

This patent document describes two structures as an example, one is a structure in which a part of a rectangular parallelepiped convex part is a part of a silicon wafer substrate, and the other is a structure in which a part of a rectangular parallelepiped convex part is formed on an SOI (silicon insulator) substrate. The structure of a part of a monocrystalline silicon layer. The former is shown in Figure 1(a) and the latter is shown in Figure 1(b).

In the structure shown in FIG. 1( a ), a part of the silicon wafer substrate 101 is a cuboid part 103 , and the gate 105 extends from one side of the cuboid part 103 across the top to the other side. In the rectangular parallelepiped portion 103, a source region and a drain region are respectively formed on opposite sides of the gate, and a channel is formed under the insulating film 104 under the gate. The width of the channel is twice the height (h) of the cuboid portion 103 , and the length of the gate is equal to the width (L) of the gate 105 . Anisotropic etching is performed on the silicon wafer substrate 101 to form a groove, and the cuboid portion 103 is formed from the area left in the groove. A gate electrode 105 is provided on the insulating film 102 formed in the trench such that the gate electrode 105 extends over the rectangular parallelepiped portion 103 .

In the configuration shown in Figure 1(b), an SOI substrate composed of a silicon wafer substrate 111, an insulating layer 112 and a silicon single crystal layer is prepared, the silicon single crystal layer is patterned into a rectangular parallelepiped part 113, and the gate 115 is arranged on The exposed insulating layer 112 extends across the cuboid 113 . In the rectangular parallelepiped portion 113, a source region and a drain region are respectively formed on both sides of the gate, and a channel is formed under the insulating film 114 under the gate. The width of the channel is equal to the sum of the double height (a) of the cuboid portion 113 and its width (b), and the gate length is equal to the width (L) of the gate 115 .

Japanese Patent Publication No. 2002-118255 (Patent Document 2) discloses a Fin type MOSFET having a plurality of rectangular parallelepiped semiconductor protrusions (protruded semiconductor layer 213 ). Fig. 2 (b) is a sectional view taken along the line B-B in Fig. 2 (a), and Fig. 2 (c) is a sectional view taken along the line C-C in Fig. 2 (a). The Fin-type MOSFET has a plurality of raised semiconductor layers 213, which are arranged parallel to one another, and a gate electrode is provided which extends over the center of these raised semiconductor layers. The gate electrode 216 is formed from the top surface of the insulating film 214 along the side surface of the raised semiconductor portion 213 . An insulating film 218 is between each raised semiconductor layer and the gate, and a channel 215 is formed on the raised semiconductor layer below the gate. Source and drain regions 217 are formed on each raised semiconductor layer, and a region 212 under the source and drain regions 217 is provided with a high-concentration impurity layer (punch-through barrier layer). Upper interconnections 229 and 230 are provided on the interlayer insulating film 226 , and the upper interconnections are connected to the source and drain regions 217 and the gate electrode 216 through contact plugs 228 , respectively. The patent document describes that according to the above structure, the side surface of the raised semiconductor layer can be used as the channel width, and therefore, the area of the plane can be reduced compared with the conventional planar MOSFET.

If miniaturization and densification are pursued in semiconductor devices including Fin-type MISFETs, the following problems will arise concerning connections (contacts) between source/drain regions and plugs.

When contacts are formed on the source/drain regions of the rectangular parallelepiped semiconductor protrusions as shown in FIGS. reduced, so it is difficult to obtain sufficient conductivity. This problem becomes more prominent as the height of the semiconductor bump increases to obtain a larger current driving capability. In the process of forming the contact holes, alignment in the width direction is difficult, and connection failure due to misalignment may occur.

As shown in Figures 1(a) and 1(b), wide pads can be provided at the opposite ends of the semiconductor bumps, and contacts can be formed in the pads, but the densification varies with the area occupied by the pads. And proportionally worse. When lithographic etching is performed, it is difficult to make the width of the semiconductor protrusion portion uniform (the width spreads near the pad portion) due to the influence of the pad portion.

Contents of the invention

An object of the present invention is to provide a semiconductor device which includes a Fin type MISFET and has a structure which forms excellent contacts and facilitates miniaturization and densification.

The invention relates to a semiconductor device, comprising:

MIS field effect transistor comprising a semiconductor protrusion raised from the plane of the substrate; a gate on the semiconductor protrusion extending from the top to opposite sides of the semiconductor protrusion, between the gate and the semiconductor protrusion a gate insulating film, and source and drain regions disposed in the semiconductor raised portion;

an interlayer insulating film provided on the substrate including the transistor; and

Buried conductor interconnection formed by filling a trench in an interlayer insulating film with a conductor,

Wherein, the buried conductor interconnection connects one of the source and drain regions of the semiconductor raised portion with the other conductive portion under the interlayer insulating film.

The present invention relates to the above semiconductor device, wherein the buried conductor interconnection is connected to one of the source and drain regions of the semiconductor raised portion and the other conductive portion under the interlayer insulating film, and is connected to one of the source and drain regions The region has an upper surface coplanar with the interlayer insulating film and a lower surface lower than the upper surface of the semiconductor protrusion.

The present invention relates to the above semiconductor device, wherein the buried conductor interconnection is in contact with the opposite side of the semiconductor bump at a region connected to one of the source and drain regions.

The present invention relates to the above-mentioned semiconductor device, wherein the semiconductor device comprises a first transistor and a second transistor which are field effect transistors of MIS type, and a buried conductor interconnection is connected to one of the source and drain regions of the first transistor and serves as the other conductive portion of the gate or one of the source and drain regions of the second transistor.

The present invention relates to the above-mentioned semiconductor device, wherein the semiconductor device comprises a transistor as an MIS field effect transistor comprising: a plurality of semiconductor protrusions protruding from the substrate plane; a gate formed from a top surface of each semiconductor protrusion to conductors extending to opposite sides; a gate insulating film between the gate and each semiconductor protrusion, and a source and a source provided in each semiconductor protrusion drain area; and

In a transistor, a buried conductor interconnect is connected to one of the source and drain regions of one semiconductor bump and to one of the source and drain regions of the other semiconductor bump as the other conductive portion.

The present invention relates to the above-mentioned semiconductor device, wherein a plurality of semiconductor protrusions are arranged in parallel to each other.

The present invention relates to the above semiconductor device, wherein the buried conductor interconnection is connected to the upper interconnection via a plug or directly.

The present invention relates to the above semiconductor device, wherein the buried conductor interconnection is connected to one of the source and drain regions through a low-resistance layer formed of a metal or a metal compound.

The present invention relates to the above-mentioned semiconductor device, wherein the buried conductor interconnection has a portion at least in the connection region between one of the source and drain regions of the semiconductor bump and the buried conductor interconnection, the portion is parallel to the substrate The width W of the bottom plane and the direction perpendicular to the length of the channel is greater than the width W of the portion below the gate.

The present invention relates to the above semiconductor device, wherein the semiconductor device includes a first conduction type transistor and a second conduction type transistor as MIS type field effect transistors, which constitute a CMOS inverter.

the gates of the first conductivity type transistor and the second conductivity type transistor are formed by a common conductor connected to the input node, and

A buried conductor interconnect is connected to the drain regions of the transistors of the first conductivity type and the drain regions of the transistors of the second conductivity type, and to the output node.

The present invention relates to a semiconductor device comprising an SRAM cell having a pair of first and second drive transistors, a pair of first and second load transistors and a pair of first and second pass transistors, wherein,

Each transistor includes a semiconductor protrusion protruding from the substrate plane; a gate extending from the top to opposite sides of the semiconductor protrusion on the semiconductor protrusion; a gate insulation between the gate and the semiconductor protrusion film; and source and drain regions provided in each semiconductor protrusion;

the semiconductor bumps of the transistor are arranged in their longitudinal direction extending along the first direction;

The first drive transistor and the first transfer transistor have a common first semiconductor protrusion, the second drive transistor and the second transfer transistor have a common second semiconductor protrusion, and the first load transistor has a common semiconductor protrusion adjacent to the first semiconductor protrusion. a third semiconductor bump of the second load transistor having a fourth semiconductor bump adjacent to the second semiconductor bump; and

The gates of the first drive transistor and the first load transistor are formed by a common first conductor, the second drive transistor and the second load transistor are formed by a common second conductor, and the first conductor and the second conductor are arranged along their vertical lines. The second direction extending in the first direction is arranged in the longitudinal direction.

The present invention relates to the above-mentioned semiconductor device, which comprises:

providing an interlayer insulating film on the substrate including the SRAM cell;

a first buried conductor interconnection connected to the first conductor, the drain region of the second load transistor, the common source/drain region of the second drive transistor and the second pass transistor, and formed in the interlayer insulating film; and

A second buried conductor interconnection connected to the second conductor, the drain region of the first load transistor, the common source/drain region of the first drive transistor and the first pass transistor is formed in the interlayer insulating film.

The present invention relates to the above semiconductor device, wherein the first buried conductor interconnection has an upper surface coplanar with the upper surface of the interlayer insulating film, and is connected to the drain region of the second load transistor, the second drive transistor, and the second In the region of the common source/drain region of the two transfer transistors, the lower surface is lower than the upper surface of the semiconductor protrusion; and the second buried conductor interconnection has an upper surface coplanar with the upper surface of the interlayer insulating film, and a lower surface lower than the upper surface of the semiconductor protrusion in a region connected to the drain region of the first load transistor, the common source/drain region of the first drive transistor, and the first transfer transistor.

The present invention relates to the above semiconductor device, wherein the first buried conductor is interconnected in a region connected to the drain region of the second load transistor, the common source/drain region of the second drive transistor and the second pass transistor, and is connected to the semiconductor bump. and the second buried conductor is interconnected in the area connected to the drain region of the first load transistor, the common source/drain region of the first drive transistor and the first pass transistor, with the semiconductor bump The opposite sides of the parts are in contact.

The present invention relates to the above semiconductor device, wherein at least one of the transistors includes: a plurality of semiconductor protrusions protruding from the substrate plane; a gate electrode formed opposite to a conductor extending laterally; a gate insulating film between the gate electrode and each semiconductor protrusion; and source and drain regions provided in each semiconductor protrusion.

The present invention relates to a method of manufacturing a semiconductor device, said semiconductor device comprising a semiconductor device of an MIS type field effect transistor, the transistor comprising: a semiconductor raised portion raised from a substrate plane; on the semiconductor raised portion from top to semiconductor A gate extending on opposite sides of the raised portion; a gate insulating film between the gate and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion. The method includes the steps of:

Forming a MIS type field effect transistor;

forming an interlayer insulating film to bury the semiconductor protrusion;

A trench is formed in the interlayer insulating film, thereby exposing at least a part of one of the source and drain regions in the semiconductor raised portion and a part of the other conductive portion conducting with the one of the source and drain regions in the trench. at least in part; and

The trench is filled with a conductor to form a buried conductor interconnection connected to one of the source and drain regions and the other conductive part.

The present invention relates to the above method of manufacturing a semiconductor device, wherein the other conductive portion is a gate and one of source and drain regions of another transistor.

The present invention relates to the above method of manufacturing a semiconductor device, wherein,

The MIS type field effect transistor includes: a plurality of semiconductor protrusions protruding from the surface of the substrate; a gate formed by a conductor provided on the plurality of semiconductor protrusions and extending from the top to opposite sides of each semiconductor protrusion. electrode; a gate insulating film between the gate and each semiconductor protrusion; and source and drain regions provided on each semiconductor protrusion; and

In the step of forming the trench, at least a part of one of the source and drain regions provided in the interconnected semiconductor protrusions is exposed, and the trench is filled with a conductor to form a semiconductor protrusion connected to the transistor. The buried conductor interconnection between the source/drain region and the source/drain region of another semiconductor bump.

The present invention relates to the above method of manufacturing a semiconductor device, comprising the step of epitaxially growing Si on the surface of the semiconductor protrusion before forming the interlayer insulating film.

The present invention relates to the above-mentioned method of manufacturing a semiconductor device, comprising the step of forming a low-resistance layer formed of metal or metal compound on a semiconductor protrusion before forming an interlayer insulating film.

The present invention relates to the above method of manufacturing a semiconductor device, comprising the step of epitaxially growing Si on the surface of the semiconductor protrusion exposed in the trench after forming the trench.

The present invention relates to the above method of manufacturing a semiconductor device, comprising the step of forming a low-resistance layer formed of a metal or a metal compound on a semiconductor protrusion exposed in the trench after forming the trench.

According to the present invention, it is possible to provide a semiconductor bump including a Fin-type MISFET, which has a structure capable of forming excellent contacts and is favorable for miniaturization and densification.

Description of drawings

1(a) and 1(b) are explanatory views of the element structure of a conventional Fin type MISFET;

2(a) to 2(b) are explanatory views of the element structure of a conventional Fin type MISFET;

FIG. 3 is an explanatory view of a Fin type MISFET of the present invention;

4(a) to 4(e) are explanatory views of a semiconductor device according to the present invention;

5(a) to 5(d) are explanatory views of another semiconductor device according to the present invention;

6(a) and 6(b) are explanatory views of another semiconductor device according to the present invention;

7(a) and 7(b) are explanatory views of another semiconductor device according to the present invention;

8(a) and 8(b) are explanatory views of another semiconductor device according to the present invention;

9(a) and 9(b) are explanatory views of another semiconductor device according to the present invention;

10 is an explanatory view of another semiconductor device according to the present invention;

11(a) and 11(b) are explanatory views of another semiconductor device according to the present invention;

12(a) and 12(b) are explanatory views of another semiconductor device according to the present invention;

13(a) and 13(b) are explanatory views of another semiconductor device according to the present invention;

14(a) to 14(c) are explanatory views of another semiconductor device according to the present invention;

15(a) to 15(d) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

16(a) to 16(d) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

17(a) to 17(b) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

18(a) to 18(c) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

19(a) to 19(c) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

20(a) to 20(d) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

21(a) to 21(c) are explanatory views of a method of manufacturing a semiconductor device according to the present invention;

Fig. 22 (a1) and 22 (a2), 22 (b1) and 22 (b2), 22 (c1) and 22 (c2) and 22 (d1) and 22 (d2) are the manufacturing method of semiconductor device according to the present invention explanatory view of

23(a) to 23(d) are explanatory views of another Fin type MISFET according to the present invention;

24(a) to 24(d) are explanatory views of another Fin type MISFET according to the present invention; and

25(a) to 25(c) are explanatory views of another semiconductor device according to the present invention.

Detailed ways

The present invention relates to a semiconductor device including a Fin-type MISFET, which includes: a semiconductor raised portion 303; a gate 304 extending from the top to opposite sides of the semiconductor raised portion above the semiconductor raised portion 303; an insulating film 305 between the semiconductor raised portion 303 ; and a source and drain region 306 disposed in the semiconductor raised portion 303 , as shown in FIG. 3 , for example.

In the present invention, the semiconductor protrusion of the Fin-type MISFET protrudes relative to the substrate plane (ie, the flat surface of the insulator), and can be formed by a semiconductor layer provided on the underlying insulating film 302 of the semiconductor substrate 301, as shown in FIG. 3 shown. In the present invention, "substrate plane" refers to any plane parallel to the surface of the substrate. The underlying insulating film may be a carrier substrate.

The semiconductor protrusion may be formed of a part of the semiconductor substrate under the underlying insulating film, which will be described later. This structure is superior in heat release characteristics and prevention of substrate floating effect, because heat and charge generated by the driving element on the semiconductor bump can dissipate to the semiconductor substrate. The semiconductor protrusion formed by the semiconductor layer provided on the underlying insulating film 302 and the semiconductor protrusion formed as a part of the semiconductor substrate under the underlying insulating film 302 may coexist on the same semiconductor substrate. The semiconductor bump is preferably substantially in the shape of a rectangular parallelepiped, but may have a shape other than a rectangular parallelepiped as long as processing accuracy and desired device characteristics can be obtained.

As the material of the semiconductor protrusions, silicon, silicon germanium, or germanium can be used. Multilayer films of these materials can be used as desired. For the opposite side of the semiconductor protrusion, {100} plane, {110} plane and {111} plane are suitable because they have high fluidity and are easy to form a flat gate insulating film.

In the Fin type MISFET of the present invention, the gate extends from the top to the opposite side of the semiconductor protrusion on the semiconductor protrusion, and an insulating film exists between the gate and the semiconductor protrusion. In the semiconductor protrusion region under the gate, a channel is formed by applying a voltage to the gate, and generally a low-concentration impurity or no impurity is generated in the channel region, depending on a predetermined threshold voltage. When the insulating film between the respective sides (surfaces in the direction perpendicular to the plane of the substrate) of the semiconductor protrusion and the gate is a gate insulating film, channels can be formed on both sides of the semiconductor protrusion. When the insulating film between the top surface of the semiconductor protrusion and the gate is a gate insulating film as thin as the side insulating films, the channel can also be formed on the top surface of the semiconductor protrusion. By forming a thick insulating film (cover insulating film) on the top surface of the semiconductor projecting portion, it is possible to prevent the formation of a channel on the top surface of the semiconductor projecting portion. The cover insulating film on the top surface of the semiconductor protrusion may be formed of a material different from that of the side insulating film, or formed separately from the insulating film on the side.

23(a) to 23(d) and 24(a) to 24(d) show cross-sectional views of the semiconductor bump region under the gate. Reference numeral 501 denotes a semiconductor layer, reference numeral 502 denotes an underlayer insulating layer, reference numeral 503 denotes a semiconductor bump, reference numeral 504 denotes a gate electrode, reference numeral 505 denotes a gate insulating film, and reference numeral 506 denotes a cover insulating film.

A cover insulating film 506 thicker than the gate insulating film 505 may be disposed on the top surface of the semiconductor protrusion 503, as shown in FIGS. 23(a) to 23(d), or the cover insulating film 506 may not be provided, as shown in FIG. ) to 24(d), it is possible to appropriately select whether or not to provide a cover insulating film.

As shown in FIGS. 24(a) to 24(d), the corners of the semiconductor protrusions can be rounded, which can prevent electric field concentration during element operation.

In the conventional structure of Figure 23 (a), the lower end of the semiconductor bump 503 and the lower end of the gate 504 are almost coplanar, while in the structure of Figure 23 (b), the lower end of the gate 504 extends to the semiconductor bump. The bottom of the raised part 503. This structure is called "π-gate structure" because the gate has a shape similar to the Greek letter "π", and this structure can improve the controllability of the channel through the gate. According to this structure, the controllability of the potential of the lower portion of the semiconductor protrusion can be improved by the gate region lower than the lower end of the semiconductor protrusion, and the steepness of on/off (on/off) transition (subthreshold characteristics) can also be improved. , and can suppress the cut-off current. Likewise, Fig. 24(b) also shows a π-gate structure.

FIG. 23( c ) shows a structure in which the gate electrode 504 is partially turned toward the lower surface of the semiconductor bump 503 . This structure is called "Ω-gate structure" because it has a shape similar to the Greek letter "Ω". According to this structure, the controllability of the channel can be improved by the gate, and the lower surface of the semiconductor protrusion can also be used as a channel, so that the driving capability can be improved. Similarly, Fig. 24(c) also shows an Ω gate structure.

FIG. 23( d ) shows a structure in which the gate 504 turns completely around the lower surface of the semiconductor bump 503 . In this structure, the semiconductor raised portion floats from the substrate plane to the area below the gate, and this structure is called a "gate surround (GAA) structure". According to this structure, the driving capability can be improved because the lower surface of the semiconductor protrusion can also be used as a channel, and short-channel characteristics can be improved. Likewise, Fig. 24(d) also shows a GAA gate structure.

According to the present invention, the semiconductor protrusions may have the same cross-sectional shape in the region under the gate and the buried conductor interconnection, or may have different cross-sectional shapes in these regions, as will be described later.

Regarding the source and drain regions of the Fin-type MISFET of the present invention, the diffusion layer with a high-concentration impurity produced by the semiconductor protruding portion 303 region on the opposite side of the gate can be as shown in FIGS. 23(a) to 23(d). The source and drain regions 506 are shown. Source and drain regions 506 may be fully metallized to implement a Schottky source/drain structure.

The Fin type MISFET in the present invention may have a so-called multi-Fin structure in which one transistor has its plurality of semiconductor protrusions arranged in, for example, a single row parallel to each other, and is formed by interconnecting conductors provided on the plurality of semiconductor protrusions. grid. The element structure related to each semiconductor bump may be the same as the aforementioned structure. Preferably, all the semiconductor protrusions belonging to one transistor have the same width W (the width in the direction parallel to the substrate plane and the direction perpendicular to the channel length) and are regularly arranged parallel to each other to obtain Uniform component characteristics and ease of manufacture.

This multi-Fin structure has a plurality of such semiconductor protrusions, and its height, that is, the dimension of the side surface perpendicular to the substrate plane is used as the channel width, so that the area required for each channel width is reduced, It is beneficial to reduce the area of the element. This multi-Fin structure enables the channel width to be controlled by changing the number of semiconductor protrusions, so it is not necessary to change the height of the element to integrate different channel widths on a single chip, so that the irregularity of the element can be reduced. Ensure uniformity of component characteristics.

In the Fin type MISFET of the present invention, the main channel is preferably formed on the opposite sides of the semiconductor protrusion, and the width of the semiconductor protrusion in the region below the gate is preferably the width formed from the opposite sides of the semiconductor protrusion. The width at which the depletion layer is completely depleted during the job. This structure is advantageous in improving cut-off characteristics and carrier mobility and reducing substrate floating effects. For an element structure capable of forming such a configuration, the width of the semiconductor protrusion in the region below the gate is preferably equal to or less than twice the height H of the semiconductor protrusion, or equal to or less than the gate length L. In detail, the width of the semiconductor protrusion in the region below the gate electrode is advantageously set to 5nm or more, preferably 10nm or more, in terms of processing accuracy, strength, and the like, to obtain a structure in which the semiconductor From the point that the channel formed on the side of the protrusion is a dominant channel and is completely depleted, it is advantageous to set it to 60 nm or less, and it is more preferable to set it to 30 nm or less.

Specific dimensions and the like of the MISFET with semiconductor bumps are set within the following ranges, for example

Width W of semiconductor protrusions: 5 to 100 nm;

Height H of semiconductor protrusions: 20 to 200 nm;

Gate length L: 10 to 100nm;

Thickness of gate insulating film: 1 to 5 nm (for SiO ₂ );

Concentration of impurities in the channel formation region: 0 to 1×10 ¹⁹ cm ⁻³ ; and

Concentration of impurities in source/drain regions: 1×10 ¹⁹ to 1×10 ²¹ cm ⁻³ .

The height H of the semiconductor protrusion refers to the length of the semiconductor region protruding from the flat surface of the underlying insulating film in a direction perpendicular to the flat surface of the substrate. The channel formation region refers to the region of the semiconductor protrusion under the gate.

The present invention relates to a semiconductor device including the above Fin type MISFET, the characteristic configuration of which will be described below.

The semiconductor device of the present invention has: an interlayer insulating film provided on a substrate so as to bury a Fin type MISFET, and a buried conductor interconnection formed by filling a trench of the interlayer insulating film with a conductor. The buried conductor interconnection connects one of the source/drain regions of the semiconductor bump of the Fin type MISFET to another conductive portion under the interlayer insulating film.

An example of the above arrangement is shown in Figs. 4(a) to 4(e). This configuration is an example where the semiconductor device includes: a Fin type MISFET having a so-called multi-Fin structure in which one Fin type MISFET has a plurality of semiconductor bumps, and is formed by conductors provided over the plurality of semiconductor bumps. formed grid. Fig. 4 (a) is a plan view, Fig. 4 (b) is a sectional view taken along A-A' line, Fig. 4 (c) is a sectional view taken along BB' line, Fig. 4 (d) is The sectional view taken along the line CC', Fig. 4(e) is the sectional view taken along the DD' line. In the drawing, reference numeral 402 denotes an underlying insulating film, reference numeral 403 denotes a semiconductor bump, reference numeral 404 denotes a gate electrode, reference numeral 405 denotes a gate insulating film, reference numeral 406 denotes source and drain regions, and reference numeral 407 denotes a trench. A track forming region, reference numeral 408 denotes a cover insulating film, reference numeral 410 denotes a first interlayer insulating film, reference numeral 411 denotes a buried conductor interconnection, reference numeral 420 denotes a second interlayer insulating film, and reference numeral 421 denotes an interlayer insulating film. plug, reference numeral 422 represents an upper interconnection. The connection between the gate 404 and the upper interconnection is not shown in the figure, but for example, the gate 404 can be connected to the upper interconnection through a plug in a region not shown in the figure. At this time, the buried conductor interconnection formed simultaneously with the buried conductor interconnection 411 may be properly located between the plug and the gate.

In the embodiment shown in FIGS. 4(a) to 4(e), a Fin-type MISFET having a multi-Fin structure including two semiconductor protrusions 403 on an underlying insulating film 402 is formed, and the Fin-type MISFET is formed. The first interlayer insulating film 410 is buried. The first interlayer insulating film 410 has a buried conductor interconnection 411 formed by filling the trench of the first interlayer insulating film 410 with a conductor, and the source/drain regions of the two semiconductor protrusions 403 pass through the buried conductor interconnection 411. Interconnects 411 are coupled to each other. The buried conductor interconnection 411 is connected to the upper interconnection 422 via a plug 421 provided in the second interlayer insulating film 420 . Buried conductor interconnects and upper interconnects can be directly connected as shown in Figure 5(a) to (d). Fig. 5(a) is a plan view, Fig. 5(b) is a sectional view taken along AA' line, Fig. 5(c) is a sectional view taken along BB' line, Fig. 5(d) is Sectional views taken along line CC', the symbols in these figures correspond to those in Figures 4(a) to 4(e).

By arranging the buried conductor interconnection and the semiconductor protrusion on the substrate plane so that their longitudinal centerlines intersect each other, preferably orthogonal to each other, the buried conductor interconnection and the semiconductor protrusion can be The connection is made in a self-aligning manner, while preventing inconsistency with the longitudinal direction of the buried conductor interconnection. Therefore, connection failures caused by misregistration are less likely to occur, thereby improving reliability and throughput of components. When the trenches provided in the interlayer insulating film for forming buried conductor interconnections have linear openings, fine opening pattern formation is easily formed. Compared with short openings, the linear opening pattern is easier to form and makes it easier to bury conductors, which is advantageous for manufacturing. Therefore, failures in opening patterning and filling with conductors are less likely to occur, so that reliability and throughput of components can be improved.

Generally, when electrically connecting conductors in a semiconductor device, two types of conductors are available: contact conductors filled in contact holes, and interconnect conductors (eg, reference numerals 228 and 229 in FIG. 2 ) connecting the contact conductors. According to the present invention, a semiconductor bump and any other conductive portion (another semiconductor bump in FIG. 4) can be interconnected with a buried conductor interconnect that can be formed in one piece. Therefore, the number of processing steps can be reduced, and reliability and throughput can be improved.

In the present invention, connection by buried conductor interconnection has structural advantages in which the semiconductor bump to be connected protrudes from the substrate plane, or another conductive portion protrudes from the substrate plane. bumps, and by locating the lower surface of the buried conductor interconnect at a level lower than the uppermost surface of the semiconductor raised portion or the uppermost surface of another conductive portion, a satisfactory connection can be made.

In the present invention, multiple buried conductor interconnections can be provided, but their top surfaces are preferably nearly coplanar to simplify the manufacturing steps. For example, in-plane uniformity is readily ensured in steps of forming interconnect contacts to buried conductors, such as photoresist steps and etch steps. By filling the trenches in the interlayer insulating film with conductors and removing the conductors outside the trenches by chemical mechanical polishing (CMP), the top surface heights of a plurality of buried conductor interconnections can be made equal. According to the CMP step, the height of the top surface of the buried conductor interconnection and the top surface of the interlayer insulating film can be made equal. Therefore, after the interlayer insulating film is deposited on the above-mentioned interlayer insulating film, the CMP step for flattening the interlayer insulating film can be omitted, so the manufacturing steps can be simplified.

The buried conductor interconnection in the present invention is preferably in contact with the opposite side of the semiconductor raised portion 403 in the region connected to the source/drain region 406 of the semiconductor raised portion 403, as shown in Figures 4(a) to 4(e) ) and Figures 5(a) to 5(d). Therefore, the contact area between the buried conductor interconnection and the semiconductor bump is increased, and the contact resistance is reduced. In the present invention, the top surface and opposite sides of the semiconductor bump 403 are preferably in contact with the buried conductor interconnection 411, as shown in Figures 4(a) to 4(e) and Figures 5(a) to 5(d) As shown, but if sufficient contact area can be ensured on the opposite side, then the buried conductor interconnection 411 can be formed without removing the capping insulating film 408 on the semiconductor bump 403, so that the buried conductor interconnection 411 is not connected with The top surfaces of the semiconductor bumps 403 are in contact, as shown in FIGS. 6( a ) and 6 ( b ). Fig. 6 (a) is a sectional view taken along the BB' line of Fig. 4 (a), and Fig. 6 (b) is a sectional view taken along the CC' line, and the symbols in these figures are the same as those in Fig. 4 The symbols of (a) to 4(e) correspond.

In the present invention, if a sufficient contact area can be ensured between the buried conductor interconnection 411 and the source/drain region 406 of the semiconductor raised portion 403, the buried conductor interconnection 411 and the source/drain region 406 can be Partial contact, that is, the contact area on the opposite side of the semiconductor bump does not reach the lower end of the semiconductor bump (ie, the buried conductor interconnection 411 does not reach the underlying insulating film 402), as shown in Figures 4(a) to 4(e) , Figures 5(a) to 5(d) and Figures 6(a) and 6(b).

Regarding the connection region between the buried conductor interconnection 411 and the source/drain region 406 of the semiconductor raised portion 403 in the present invention, the buried conductor interconnection 411 and the source/drain region 406 can be formed from the semiconductor raised portion The region extending from the upper end to the lower end (the entire source/drain region 406 in the direction perpendicular to the substrate) is in contact with each other, as shown in FIGS. 7( a ) and 7 ( b ). Figures 7(a) and 7(b) are cross-sectional views taken along line BB' of Figure 4(a), and the symbols in these figures correspond to those in Figures 4(a) to 4(e) . In this case, the buried conductor interconnection 411 reaches the underlying insulating film 402 and further extends to a position deeper than the lower end of the semiconductor protrusion 403 (a position lower than the flat surface of the underlying insulating film 402 ). As shown in Figure 7 (a), the insulating film below the semiconductor raised portion 403 can be removed, and the conductor is buried in the position where the insulating film is removed, so that the lower surface of the semiconductor raised portion 403 can also be connected to the buried conductor. Interconnect 411 contacts.

The buried conductor interconnection 411 in the present invention can be in contact with the end surface of the semiconductor protrusion 403 in the longitudinal direction (the channel length direction), as shown in FIGS. 8( a ) and 8 ( b ). Therefore, the contact resistance between the buried conductor interconnection and the semiconductor bump can be further reduced.

In the aforementioned Figures 4(a) to 4(e), Figures 5(a) to 5(d), Figures 6(a) and 6(b), Figures 7(a) and 7(b) and Figure 8(a ) and 8(b), the semiconductor protruding portion 403 is provided on the underlying insulating film 402, but the present invention may employ a configuration in which the semiconductor protruding portion 403 is a semiconductor substrate under the underlying insulating film 402 A part of 401, as shown in Figures 9(a) and 9(b). Fig. 9 (a) is a sectional view taken along BB' line, and 9 (b) is a sectional view taken along CC' line, and the symbols in these figures are the same as those in Fig. 4 (a) to 4 (e ) correspond to the symbols in . In the structures shown in FIGS. 9(a) and 9(b), the upper surface of the semiconductor raised portion below the gate is provided with a gate insulating film 405 instead of the covering insulating film, and the insulating film on the upper surface of the semiconductor raised portion Removed except for the area under the gate. Regardless of whether the semiconductor bump is on the underlying insulating film or is a part of the semiconductor substrate, the presence or absence of the covering insulating film can be appropriately selected.

In Figures 4(a) to 4(e), Figures 5(a) to 5(d), Figures 6(a) and 6(b), Figures 7(a) and 7(b) and Figure 8(a) In the structures shown in and 8(b), a plurality of linear semiconductor protrusions are provided, but as shown in FIG. 10 (plan view), at least one side of adjacent semiconductor protrusions 403 in the channel length direction ( Figure 10 is both sides) end portions can be integrally combined. In order to ensure the uniformity of the width W of the semiconductor protrusion, there is preferably a sufficient distance between the junction of the gate 404 and the end of the semiconductor protrusion. At least the entire upper surface of the junction is connected to the buried conductor interconnection 411 , more preferably two opposite sides are connected, as shown in FIG. 10 . By providing such a connection area, the contact area interconnected with the buried conductor can be increased, and furthermore, the destruction of the semiconductor bump which is easily caused when the semiconductor bump has a high height can be prevented. The bonding portion is located in the formation area of the buried conductor interconnection, so there is no need to increase the size of the bonding portion as in conventional connection pads, thereby ensuring sufficient densification. Even when there is a sufficient distance d, an increase in resistance can be prevented if the buried conductor interconnection is connected to the semiconductor bump in the region next to the gate.

The buried conductor interconnects of the present invention can be formed from a variety of conductors. It is preferable to form such a configuration that the trenches are filled with a conductive metal such as W or a metal compound in contact with the underlying conductive film having barrier capability and adhesion. Buried conductor interconnects can have configurations in which the conductor consists of a single metal or metal compound, with the conductor itself being the underlying film. The underlying film may include a Ti film, a TiN film, a Ta film, a TaN film, a WN film, and a laminated film of two or more selected from these films.

In the present invention, the connection region between the buried conductor interconnection and the source/drain region of the semiconductor bump may have a low-resistance layer therebetween. Therefore, the resistance between the buried conductor interconnection and the semiconductor bump can be reduced. The low resistance layer may cover the entire source/drain region of the semiconductor bump, or selectively provide a connection region between the semiconductor bump and the buried conductor interconnect. The low resistance layer may be formed of a metal such as Ti or W, or at least one metal selected from Ti, Co, Ni, Pt, Pd, Mo, W, Zr, Hf, Ta, Ir, Al, V, Cr, etc. Silicon compounds are formed.

The semiconductor raised part of the present invention may have the shape of a cuboid, but may also have a structure in which in the connection region between the source/drain region of the semiconductor raised part and the buried conductor interconnection, its width W (the width parallel to the substrate plane and perpendicular to the channel length direction) is wider than the width W of the region below the gate, for example, in Figures 22(a1) and 22(a2), 22( b1) and 22(b2), 22(c1) and 22(c2) and 22(d1) and 22(d2). The region with a wider width W is preferably provided at least at the upper end region of the source/drain region of the semiconductor protrusion, so that the contact area of the connection region is increased, thereby reducing the contact resistance. The wider region may provide the entire channel length direction of the source/drain region at the upper end of the semiconductor protrusion, or selectively provide the connection area between the semiconductor protrusion and the buried conductor interconnect.

The above-mentioned embodiments all have a structure in which a Fin type MISFET has a plurality of semiconductor protrusions, and the source/drain regions of the semiconductor protrusions are coupled with buried conductor interconnections. The present invention also adopts a structure in which the semiconductor bump source/drain region of one Fin type MISFET and the gate or source/drain region of another MISFET are interconnected with buried conductors.

11(a) and 11(b) show a structure in which the source/drain region 406 of the semiconductor raised portion 403a of a Fin-type MISFET and the gate 404b of another Fin-type MISFET are interconnected with a buried conductor 411c. connect. Fig. 11(a) is a plan view, and Fig. 11(b) is a sectional view taken along A-A'. Symbols 403a and 403b in the figure represent semiconductor bumps, symbols 404a and 404b represent wires forming a gate, symbol 405b represents a gate insulating film, symbols 411a, 411b and 411c represent conductor interconnections, and other symbols are the same as those shown in FIG. 4(a) Correspond to those symbols in Fig. 4(e). According to this structure, source/drain regions and gates can be densely connected between different MISFETs.

12(a) and 12(b) show a structure in which the source/drain of the semiconductor raised portion 403a of one Fin-type MISFET and the source/drain of the semiconductor raised portion 403b of the other Fin-type MISFET are buried The conductor interconnection 411c is connected. Fig. 12(a) is a plan view, and Fig. 12(b) is a circuit diagram. In these figures, symbols 403a and 403b represent semiconductor bumps, symbol 404 represents a conductor forming a gate, symbols 411a, 411b and 411c represent buried conductor interconnections, and black circles represent plugs.

The embodiment shown in FIG. 12 is an example of a CMOS inverter including pMOS having two semiconductor protrusions 403a and nMOS having one semiconductor protrusion 403b. The gates of the pMOS and nMOS are formed by a common conductor 404 to which a plug leading to the input is connected. The drain region of the pMOS and the drain region of the nMOS are connected by a buried conductor interconnection 411c, and a plug leading to an output portion is connected to the buried conductor interconnection 411c. The buried conductor interconnect 411c also provides a connection for the drain regions of the two semiconductor bumps 403a configured in pMOS. The source regions provided in the two semiconductor bumps of the pMOS are connected with a buried conductor interconnection 411c, and a plug leading to a power supply Vdd is connected to the buried conductor interconnection 411a. The source region of the nMOS semiconductor bump 403b is connected to the buried conductor interconnection 411b, and the plug leading to the ground (GND) is connected to the buried conductor interconnection 411b.

13(a) and 13(b) and 14(a) to 14(c) show a structure in which the source/drain region of the semiconductor raised portion of the first Fin-type MISFET, the second Fin-type MISFET The source/drain region of the semiconductor raised portion and the gate of the third Fin-type MISFET are connected by buried conductor interconnection. Fig. 13(a) is a circuit diagram, Fig. 13(b) is a plan view, Fig. 14(a) is a sectional view taken along the A-A' line, and Fig. 14(b) is a sectional view taken along the BB' line Fig. 14(c) is a sectional view taken along the line CC'. In the drawing, symbols 403a, 403b, 403c, and 403d represent semiconductor bumps, symbols 404a, 404b, 404c, and 404d represent conductors forming gates, and symbols 411L1, 411L2, 411a1, 411a2, 411b, 411c, 411d1, and 411d2 represent Buried conductor interconnections, other symbols correspond to those in Figures 4(a) to 4(e). Black circles indicate plugs.

This embodiment is an example of SRAM (Static Random Access Memory), which includes a pair of drive transistors Td1 and Td2, a pair of load transistors Tp1 and Tp2, and a pair of transfer transistors Tt1 and Tt2 composed of Fin-type MISFETs, one of which The memory cell consists of a flip-flop circuit including a pair of drive transistors, a pair of load transistors, and a pair of pass transistors. The pair of drive transistors Td1 and Td2 and the pair of transfer transistors Tt1 and Tt2 are of n-channel type, and the pair of load transistors Tp1 and Tp2 are of p-channel type.

As shown in FIG. 13(a), the above-mentioned flip-flop circuit is composed of a pair of CMOS inverters, and each CMOS inverter is composed of a driving transistor and a load transistor. The gates of the drive transistor Td1 and load transistor Tp1 of one CMOS inverter are connected to the drain (storage node N2 ) of the drive transistor Td2 and load transistor Tp2 of the other CMOS inverter. The gates of the drive transistor Td2 and load transistor Tp2 of the latter CMOS inverter are connected to the drains (storage node N1 ) of the drive transistor Td1 and load transistor Tp1 of the previous CMOS inverter. Therefore, the input and output nodes of a pair of CMOS inverters are cross-coupled to each other through a pair of local interconnect lines L1 and L2.

In this embodiment, the gates of the first drive transistor Td1 and the first load transistor Tp1 are formed by a common first conductor 404b, and the gates of the second drive transistor Td2 and the second load transistor Tp2 are formed by a common second conductor 404c. Formed, as shown in Figure 13(b). The first driving transistor Td1 and the first transfer transistor Tt1 have a common first semiconductor protrusion 403a, and the second driving transistor Td2 and the second transfer transistor Tt2 have a common second semiconductor protrusion 403d. The first conductor 404b, the drain region provided in the third semiconductor bump 403c of the second load transistor Tp2, and the common source/drain of the second drive transistor Td2 and the second transfer transistor Tt2 in the second semiconductor bump 403d region, connected with a buried conductor interconnection 411L2 forming one of a pair of local interconnections, the second conductor 404c, the drain region provided in the fourth 403b of the first load transistor Tp1, and the first semiconductor raised portion 403a The shared source/drain regions of the first driving transistor Td1 and the first transfer transistor Tt1 are connected by a buried conductor interconnection 411L1 forming another local interconnection. That is to say, a pair of local interconnects L1 and L2 respectively cross-couple a pair of input/output terminals of the above-mentioned flip-flop circuit composed of buried conductor interconnection 411L1 and buried conductor interconnection 411L2 .

In this embodiment, the buried conductor interconnections 411a1 and 411d1 are respectively connected to the other source/drain regions of the transfer transistors Tt1 and Tt2, and the plugs leading to the bit line BL are respectively connected to these buried conductor interconnections 411a1 and 411d1. Plugs leading to word line WL are connected to conductors 404a and 404d forming the gates of pass transistors Tt1 and Tt2, respectively. Buried conductor interconnections 411b and 411c are connected to the source regions of the first and second load transistors Tp1 and Tp2, respectively, and plugs leading to the power supply VDD are connected to these buried conductor interconnections 411b and 411c, respectively. Buried conductor interconnections 411a2 and 411d2 are respectively connected to the source regions of the first and second driving transistors Td1 and Td2, and plugs leading to the ground GND are connected to these buried conductor interconnections 411a2 and 411d2.

According to this structure, dense interconnections can be made, and local interconnections can be formed without additional processing steps. If the semiconductor protrusions of a plurality of Fin-type MISFETs are respectively arranged in parallel to each other, the semiconductor protrusions can be patterned in the form of rows or spaces, so even semiconductor protrusions with a narrow width W can be easily and precisely form.

The present invention can also be applied when a Fin type MISFET is formed on a substrate provided with a planar type MISFET. In addition, the buried conductor interconnection according to the present invention can be used for electrical connection between a Fin type MISFET and a planar type MISFET. An example is shown in Figs. 25(a) to 25(c). 25(a) to 25(c) respectively show structures at cross-sectional positions corresponding to FIGS. 4(a) to 4(c).

In the example of FIGS. 25(a) to 25(c), a wide semiconductor protrusion 403p is formed instead of one of the semiconductor protrusions 403 of the Fin type MISFET shown in FIGS. 4(a) to 4(e). . The wide semiconductor protrusions 403p have main channels formed on their top surfaces, and function as planar type MISFETs. Such a planar MISFET can be suitably used as an input/output section and an analog section of an integrated circuit. In this example, the cover insulating film 408 is not provided to facilitate the formation of the planar type MISFET. The gate 404p of the planar MISFET is provided separately from the gate 404 of the Fin-type MISFET.

In the example of FIGS. 25(a) to 25(c), the buried conductor interconnection 411 is connected to one of the source and drain of the semiconductor protrusion of the Fin type MISFET and the source of the semiconductor protrusion 403p of the planar type MISFET. and drain one. When the buried conductor interconnection for Fin-type MISFET is applied to planar-type MISFET, the structure can be co-fabricated and processed between Fin-type MISFET and planar-type MISFET, therefore, it can be made dense and reduce Fin-type MISFET and The cost of an integrated circuit where planar MISFETs coexist.

The examples of FIGS. 25(a) to 25(c) show a structure in which an SOI substrate is used, and the semiconductor protrusions 403 are formed from a semiconductor layer on an underlying insulating film, but the present invention is also applicable to a structure using a bulk substrate. In the structure of the bottom, a semiconductor protrusion is formed from a part of the substrate.

In the above element structure, the material of the underlying insulating film is not particularly limited as long as it has the desired insulating properties, and such materials may include, for example, SiO ₂ , Si ₃ N ₄ , AlN, metal oxides such as alumina, and organic insulating materials. . As the semiconductor forming the semiconductor protrusion, single crystal silicon can be suitably used.

In the present invention, a silicon substrate can be suitably used as the substrate under the underlying insulating film, but as long as the insulating film is under the semiconductor protrusion, the present invention can be constituted, except that the semiconductor protrusion is formed from the substrate under the insulating film. Part of the formation of the case other than. For example, there may be a structure in which an insulating film under a semiconductor layer is a carrier substrate, as in SOS (silicon sapphire or silicon ontite). Insulation carrier substrates include quartz and AlN substrates in addition to the above-mentioned SOS substrates. Using the technique of processing SOI (layering step and thin film forming step), semiconductor layers can be provided on these carrier substrates.

As the gate material in the present invention, conductors having desired electrical conductivity and workability can be used, and these materials include, for example, semiconductors containing impurities such as polysilicon containing impurities, polycrystalline SiGe, polycrystalline Ge, and polycrystalline SiC ; metals such as Mo, W, Ta, Ti, Hf, Re and Ru; metal nitrides such as TiN, TaN, HfN and WN; silicon compounds such as cobalt silicide, nickel silicide, platinum silicide and erbium silicide. As the structure of the gate electrode, a layered structure such as a layered film of a semiconductor and a metal film, a layered film of a metal film or a layered film of a semiconductor and a silicide film, and a single layer film can be used.

As the gate insulating film in the present invention, a SiO ₂ film or a SiON film can be used, and a high-dielectric insulating film (High-k film) can also be used. High-k films may include, for example, metal oxide films such as Ta ₂ O ₅ films, Al ₂ O ₃ films, La ₂ O ₃ films, HfO ₂ films, and ZrO ₂ films, and represented by HfSiO, ZrSiO, HfAlO, ZrAlO, etc. of metal oxides. The gate insulating film may have a layered structure, and may be, for example, a layered film made by forming a silicon-containing oxide film such as _SiO2 or HfSiO on a semiconductor layer such as silicon and providing a High-k film thereon.

A method of manufacturing the semiconductor device of the present invention will be described below by way of example.

First, an SOI substrate is prepared, which has a buried insulating film (underlying insulating film) made of _SiO2 on a silicon substrate, and a semiconductor layer made of single crystal silicon thereon. A sacrificial oxide film is formed on the semiconductor layer of the SOI substrate, and impurities for a channel formation region are ion-implanted through the sacrificial oxide film. Then, the sacrificial oxide film is removed, and an insulating film is formed on the semiconductor layer for forming a cover insulating film. The above ion implantation and formation and removal of the sacrificial oxide film may be omitted as appropriate.

Next, photolithography and dry etching are used to pattern the semiconductor layer and the insulating film formed thereon to form semiconductor protrusions. Then, a gate insulating film is formed on the surface (side surface) of the semiconductor protrusion.

If a cover insulating film is unnecessary on the top surface of the semiconductor protrusion, the above insulating film may be removed before applying photolithography. Instead of continuously patterning the above-mentioned insulating film and semiconductor layer, it is better to first pattern the above-mentioned insulating film, then remove the resist mask, and then use the above-mentioned patterned insulating film as a mask (hard mask) to pattern the above-mentioned semiconductor layer. change.

After forming the semiconductor protrusions and before forming the gate insulating film, the underlying insulating film may be etched anisotropically (downward) to form a π-gate structure, or may be etched isotropically (downward and sideways). ) to form an Ω gate structure or a GAA gate structure.

Next, a polysilicon film is formed on the entire surface and patterned to form a gate pattern. Impurities are ion-plated in the oblique direction of the flat surface of the substrate to make this gate pattern conductive and to form source and drain regions on the semiconductor protrusions. The structure at this time is shown in Figs. 15(a), (b), (c) and (d). Fig. 15(a) is a plan view, Fig. 15(b) is a sectional view taken along AA' line, Fig. 15(c) is a sectional view taken along BB' line, Fig. 15(d) is Sectional views taken along line CC', the symbols in these figures correspond to those in Figures 4(a) to 4(e).

Next, an interlayer insulating film 410 is formed on the entire surface, and this surface is polished by a chemical mechanical polishing (CMP) method.

Next, a trench is formed by photolithography and dry etching to expose the conductive portion (semiconductor bump) to be coupled. At this time, the capping insulating film in the trench is also removed to expose the surface of the semiconductor protrusion 403 . The configuration at this time is shown in Figs. 16(a), 16(b), 16(c) and 16(d). Fig. 16(a) is a plan view, Fig. 16(b) is a sectional view taken along AA' line, Fig. 16(c) is a sectional view taken along BB' line, Fig. 16(d) is Sectional views taken along line CC', the symbols in these figures correspond to those in Figures 4(a) to 4(e).

Next, by CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition) or the like, an underlying conductive film 431 is formed on the entire surface to cover the inside of the trench 430, and then a conductor is deposited by CVD or the like to fill it up. in the trench. Using the CMP method, all but a part of the underlying film and the conductor film in the trench are removed to form a flat surface, and the buried conductor interconnection 411 is formed. The configuration at this time is shown in Figs. 17(a) and 17(b). Fig. 17 is a sectional view taken along BB' line, and Fig. 17(c) is a sectional view taken along CC' line, the symbols in these figures are the same as those in Fig. 16(a) to 16(c) corresponding to the symbols. The underlying film 431 and the semiconductor protrusion 403 undergo a silicide formation reaction and are formed with lower contact resistance. If the silicide formation reaction is performed, an unreacted region (semiconductor such as single crystal silicon) is preferably left in the central portion of the semiconductor protrusion in terms of conductivity in the channel length direction in the semiconductor protrusion.

Secondly, using a known method, the upper interconnection 422 can be formed via a plug or directly coupled with the buried conductor interconnection 411, as shown in Figures 4(a) to 4(e) or Figures 5(a) to 5 (d). The plug can be formed with W or Cu, and the upper interconnect can be formed with Cu or Al.

The structure shown in FIG. 7( b ) can be obtained by performing dry etching until the underlying insulating film 402 is carved and filling the trenches with conductors in the above step of forming the trenches 430 . The structure shown in FIG. 7(a) can be formed by performing anisotropic dry etching until the underlying insulating film 402 is carved to form a trench, and then performing isotropic dry etching or wet etching to further remove the semiconductor protrusions in the trench. The lower portion of the insulating film is filled with a conductor to bury the conductor in the region where the insulating film has been removed.

By adding the following steps to the above-described process, side walls can be provided on the sides of the gate.

After patterning the gate electrode, an insulating film for forming side walls is provided on the entire surface to the thickness capable of burying the gate electrode, and the surface is flattened by the CMP method. Then, a resist pattern is provided on the insulating film, which has a width wider than that of the pattern of the gate in the length direction of the gate, so that the resist pattern is superimposed on the gate pattern, and selectively masked by using the resist pattern. Remove the insulating film. At this time, the cover insulating film on the semiconductor bump is also selectively removed. Therefore, a side wall 440 composed of an insulating film can be formed on the side of the conductor pattern 404 for the gate electrode, as shown in FIGS. 18(a) to 18(c). Fig. 18(a) is a plan view, Fig. 18(b) is a sectional view taken along BB' line, and Fig. 18(c) is a sectional view taken along CC' line, the symbols in these figures are the same as The symbols in Figures 4(a) to 4(e) correspond. Before or after the step of forming the sidewall, ion implantation of impurities may be performed, in this case, a relatively low-concentration impurity diffusion layer can be provided under the sidewall, and a structure called LDD (Low Doped Drain) can be formed. .

The side walls can also be formed by the following method. After forming the pattern of the gate, slightly provide an insulating film for forming side walls on the top and side surfaces of the recessed portion and the raised portion, deposit the insulating film to the same thickness, and use an anisotropic etching method only on the upper and lower sides. Lightly scratch (deep etch) the insulating film in the direction. The method of forming the sidewall is similar to the method used to produce a planar type MISFET, but in this method, the sidewall may be formed on the side of the semiconductor protrusion. In order to prevent this, it is required to etch back the insulating film sufficiently after the gate has a sufficient thickness so that the sidewall does not remain on the side of the semiconductor protrusion.

Further, after the formation of the side walls by the above-mentioned method and ion implantation of impurities, a low-resistance layer can be formed on the surface of the semiconductor protrusion. The structure when a low-resistance layer is provided on the surface of the semiconductor protrusion after the steps shown in FIGS. 18(a) to 18(c) is shown in FIGS. 19(a) to 19(c). Fig. 19(a) is a plan view, Fig. 19(b) is a sectional view taken along BB' line, and Fig. 19(c) is a sectional view taken along CC' line, the symbols in these figures are the same as The symbols in Figs. 18(a) to 18(c) correspond.

Due to the formation of the low-resistance layer, the width W of the semiconductor protrusion (including the low-resistance layer) is widened to increase the contact area, so the contact resistance between the semiconductor protrusion and the buried conductor interconnection can be compared with that of the low-resistance layer. Conductivity decreases together. Further, the conductivity of the semiconductor protrusion can be improved in the channel length direction. In addition, the low-resistance layer may serve as an etching stopper layer in a step of forming the trench 430 to be performed later. A low-resistance layer can be formed by selectively growing a metal or a metal compound such as NiSi, _CoSi2 , _TiSi2 , Ni, Co, Ti, or W in the exposed area of the semiconductor protrusion by a CVD method or the like. The metal so grown allows it to undergo a silicide formation reaction with the silicon of the semiconductor bump to reduce contact resistance. On the other hand, by non-selective growth of Ni, Co, Ti, etc. by PVD method, CVD method or the like, a low-resistance layer can be formed, and then the metal is reacted to form silicide (self-aligned method to make the metal and semiconductor convex The silicon in the starting part undergoes a silicide reaction, and then only the unreacted metal is removed). When the above silicide formation is performed, the unreacted region (single crystal silicon) is preferably left in the central portion of the semiconductor protrusion in terms of conductivity in the channel length direction in the semiconductor protrusion. Alternatively, unreacted regions can be intentionally eliminated to form Schottky sources/drains.

After the above-mentioned low-resistance layer 450 is formed, an interlayer insulating film 410 is formed on the entire surface, and the surface is flattened by a CMP method. Then, a trench 430 is formed by photolithography and dry etching to expose the conductor portion (semiconductor protrusion 403) to be coupled. The configuration at this time is shown in Fig. 20(a) to 20(d), Fig. 20(a) is a plan view, Fig. 20(b) is a sectional view taken along line AA', Fig. 20(c) is The sectional view taken along the BB' line, Fig. 20(d) is the sectional view taken along the CC' line, the symbols in these figures are the same as those in Fig. 19(a) to 19(c) correspond. Next, the underlying conductive film 431 is deposited in the trench 430; then, the trench is further filled with a conductor to form a buried conductor interconnection 411, as shown in FIGS. 21(a) to 21(c). Fig. 21(a) is a plan view, Fig. 21(b) is a sectional view taken along BB' line, and Fig. 21(c) is a sectional view taken along CC' line, the symbols in these figures are the same as The symbols in Figs. 20(a) to 20(d) correspond. On the other hand, after the trench 430 is formed, the low resistance layer 450 may be provided on the surface exposed in the trench. Secondly, using a known method, an upper interconnection 422 can be provided, which is directly coupled to the buried conductor interconnection 411 through a plug, as shown in Figures 4(a) to 4(e) or Figures 5(a) to 5(d).

In the above process, before forming the low-resistance layer 450, Si can be epitaxially grown on the surface of the semiconductor protrusion to provide the grown silicon layer 460, as shown in FIGS. 22(a1) and 22(a2), 22(b1). and 22(b2), 22(c1) and 22(c2) and 22(d1) and 22(d2). Figure 22(a1), 22(b1), 22(c1) and 22(d1) are sectional views taken along the BB' line in Figure 18(a), Figure 22(a2), 22(b2) , 22(c2) and 22(d2) are cross-sectional views taken along the line CC' in Figure 18(a), and the symbols in these figures are the same as those in Figure 18(a) to 18(c) correspond. By providing the grown silicon layer 460, the width W of the semiconductor protrusion is widened to increase the contact area, whereby the contact resistance between the semiconductor protrusion and the interlayer insulating film can be reduced. The grown silicon layer 460 may be provided on the entire surface of the exposed semiconductor protrusion, but may also be formed to widen the width of the top end of the semiconductor protrusion, and may be provided, for example, at least in the region from the top surface to each of the opposite sides. , as shown in Figure 22(a1). For conductivity, the impurity is preferably ion-implanted to grow the silicon layer 460, as shown in FIGS. 22(b1) and 22(b2). Second, the low resistance layer 450 is provided at least on the top surface of the semiconductor protrusion. If the width W of the semiconductor protruding portion is sufficiently widened by growing a silicon layer 460, as shown in FIGS. Sufficient to reduce the effect of contact resistance. In this case, the low-resistance layer 450 can be easily formed by depositing a metal such as Ni, Co, or Ti on the top surface of the semiconductor protrusion by sputtering. Next, an interlayer insulating film 410 is formed on the entire surface, and the surface is flattened by the CMP method. Then, the trench 430 is formed by photolithography and dry etching, exposing the conductive part (semiconductor protrusion) to be coupled. Next, as shown in FIGS. 22( d1 ) and 22 ( d2 ), conductors are filled in trenches 430 through an underlying film 431 to form buried conductor interconnections 411 . Secondly, the upper interconnection 422 can be provided by a known method, which is directly coupled to the buried conductor interconnection 411 through a plug, as shown in Figures 4(a) to 4(e) or Figures 5(a) to 5 (d) shown. After the interlayer insulating film 410 and the trench 430 are formed, a grown silicon layer 460 may be disposed on the surface of the semiconductor protrusion exposed in the trench, and then the low resistance layer 450 can be formed. Before the generation of the interlayer insulating film 410, by providing the growth silicon layer 460 on the entire surface of the semiconductor raised portion, and disposing the low-resistance layer 450 on the entire surface of the semiconductor raised portion, a structure similar to that shown in FIG. 19(b) can be obtained. shape.

Claims (21)

1. A semiconductor device, comprising: MIS type field effect transistor, which includes: a semiconductor raised portion protruding from the substrate plane; a gate extending from the top to the opposite side of the semiconductor raised portion on the semiconductor raised portion; between the gate and the semiconductor raised portion a gate insulating film between them, and a source region and a drain region disposed in the semiconductor raised portion; an interlayer insulating film provided on the substrate including the transistor; and Buried conductor interconnection formed by filling a trench in an interlayer insulating film with a conductor, Wherein, the buried conductor interconnection connects one of the source region and the drain region of the semiconductor raised portion with the other conductive portion under the interlayer insulating film. 2. The semiconductor device according to claim 1, characterized in that: the buried conductor interconnection is connected to one of the source region and the drain region of the semiconductor raised portion and the other conductive portion under the interlayer insulating film, and is connected to The connection region to one of the source region and the drain region has an upper surface coplanar with the upper surface of the interlayer insulating film and a lower surface lower than the upper surface of the semiconductor protrusion. 3. The semiconductor device according to claim 1, wherein the buried conductor interconnect contacts opposite sides of the semiconductor protrusion at a region connected to one of the source region and the drain region. 4. The semiconductor device according to claim 1, characterized in that: the semiconductor device comprises a first transistor and a second transistor which are field effect transistors of the MIS type, and the buried conductor interconnection is connected to the source region of the first transistor and one of the drain regions and one of the gate or the source and drain regions of the second transistor as the other conductive part. 5. The semiconductor device according to claim 1, characterized in that the semiconductor device comprises: a transistor as an MIS type field effect transistor, said transistor comprising: a plurality of semiconductor protrusions protruding from the substrate plane; a gate on a plurality of semiconductor protrusions and extending from the top of each semiconductor protrusion to its opposite side; a gate insulating film between the gate and each semiconductor protrusion; and a gate insulating film disposed on each semiconductor protrusion. source and drain regions in the raised portion; and In the transistor, the buried conductor interconnect is connected to one of the source and drain regions of one semiconductor bump and one of the source and drain regions of the other semiconductor bump as the other conductive portion . 6. The semiconductor device according to claim 5, wherein the plurality of semiconductor protrusions are arranged parallel to each other. 7. The semiconductor device according to claim 1, wherein the buried conductor interconnection is connected to the upper interconnection via a plug or directly. 8. The semiconductor device according to claim 1, wherein the buried conductor interconnection is connected to one of the source and drain regions through a low-resistance layer formed of metal or metal compound. 9. The semiconductor device according to claim 1, wherein the buried conductor interconnection has at least one connection region between the source region and the drain region of the semiconductor raised portion and the buried conductor interconnection. part, the width W of the part along the direction parallel to the substrate plane and perpendicular to the length of the channel is greater than the width W of the part below the gate. 10. The semiconductor device according to any one of claims 1 to 9, characterized in that: the semiconductor device comprises a first conductivity type transistor and a second conductivity type transistor as MIS type field effect transistors, which constitute a CMOS inverter Phaser, the gates of the first conductivity type transistor and the second conductivity type transistor are formed from a common conductor connected to the input node, and The buried conductor interconnection is connected to the drain region of the transistor of the first conductivity type and the drain region of the transistor of the second conductivity type, and is connected to the output node. 11. A semiconductor device comprising an SRAM cell having a pair of first and second drive transistors, a pair of first and second load transistors, and a pair of first and second pass transistors, wherein: Each transistor includes: a semiconductor protrusion protruding from the substrate plane; a gate extending from the top on the semiconductor protrusion to opposite sides of the semiconductor protrusion; a gate between the gate and the semiconductor protrusion. an insulating film; and a source region and a drain region provided in the semiconductor raised portion; the semiconductor bumps of the transistors are arranged in their longitudinal direction extending along the first direction; The first drive transistor and the first transfer transistor have a common first semiconductor protrusion, the second drive transistor and the second transfer transistor have a common second semiconductor protrusion, and the first load transistor has a common semiconductor protrusion adjacent to the first semiconductor protrusion. a third semiconductor bump of the second load transistor having a fourth semiconductor bump adjacent to the second semiconductor bump; and The gates of the first drive transistor and the first load transistor are formed by a common first conductor, the gates of the second drive transistor and the second load transistor are formed by a common second conductor, and the first conductor and the second conductor are formed according to their are arranged along a longitudinal direction extending in a second direction perpendicular to the first direction, and wherein The semiconductor device includes: an interlayer insulating film provided on a substrate including an SRAM cell; a first buried conductor interconnection connected to the first conductor, the drain region of the second load transistor, the common source/drain region of the second drive transistor and the second pass transistor, and formed in the interlayer insulating film ;and a second buried conductor interconnection connected to the second conductor, the drain region of the first load transistor, the common source/drain region of the first drive transistor and the first transfer transistor, and formed in the interlayer insulating film . 12. The semiconductor device according to claim 11, wherein: The first buried conductor interconnection has an upper surface coplanar with the upper surface of the interlayer insulating film, and In a region connected to the drain region of the second load transistor, the common source/drain region of the second drive transistor, and the second transfer transistor, a lower surface lower than the upper surface of the semiconductor raised portion; and The second buried conductor interconnect has an upper surface coplanar with the upper surface of the interlayer insulating film, and In a region connected to the drain region of the first load transistor, the common source/drain region of the first driving transistor, and the first transfer transistor, the lower surface is lower than the upper surface of the semiconductor protrusion. 13. The semiconductor device according to claim 11, wherein: The first buried conductor interconnect contacts opposite sides of the semiconductor bump in a region connected to the drain region of the second load transistor, the common source/drain region of the second drive transistor, and the second pass transistor; and The second buried conductor interconnect contacts the opposite side of the semiconductor bump in a region connected to the drain region of the first load transistor, the common source/drain region of the first drive transistor and the first pass transistor. 14. The semiconductor device according to any one of claims 11 to 13, wherein at least one of the transistors comprises: a plurality of semiconductor protrusions protruding from the substrate plane; gates formed of conductors on the plurality of semiconductor protrusions and extending from the top surface of each semiconductor protrusion to its opposite side; a gate insulating film between the gate and each semiconductor protrusion; and a gate insulating film disposed on each semiconductor protrusion A source region and a drain region in a semiconductor raised portion. 15. A method of manufacturing a semiconductor device, the semiconductor device comprising an MIS type field effect transistor, the transistor comprising: a semiconductor raised portion raised from a substrate plane; on the semiconductor raised portion from the top surface of the semiconductor raised portion A gate extending on its opposite side; a gate insulating film between the gate and the semiconductor raised portion, and a source region and a drain region arranged in the semiconductor raised portion, characterized in that the method comprises the steps of: Forming a MIS type field effect transistor; forming an interlayer insulating film to bury the semiconductor protrusion; A trench is formed in the interlayer insulating film, thereby exposing in the trench at least a portion of one of the source region and the drain region disposed in the semiconductor raised portion, and at least a portion of another conductive portion conducting with one of the source and drain regions; and The trench is filled with a conductor to form a buried conductor interconnection connected to one of the source and drain regions and the other conductive portion. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the other conductive portion is one of the gate and the source and drain regions of another transistor. 17. The method of manufacturing a semiconductor device according to claim 15, characterized in that: The MIS type field effect transistor includes: a plurality of semiconductor protrusions protruding from the substrate surface; a gate formed by a conductor disposed on the plurality of semiconductor protrusions and extending from the top of each semiconductor protrusion to the opposite side. electrode; a gate insulating film between the gate and each semiconductor raised portion; and a source region and a drain region provided in each semiconductor raised portion; and In the step of forming the trench, at least a part of one of the source region and the drain region provided in the semiconductor raised portion to be conducted to each other is exposed, and the trench is filled with a conductor to form a semiconductor connection to one of the transistors. A buried conductor interconnects one of the source and drain regions of the raised portion and one of the source and drain regions of the other semiconductor raised portion. 18. The method of manufacturing a semiconductor device according to claim 15, characterized by comprising the step of epitaxially growing Si on the surface of the semiconductor protrusion before forming the interlayer insulating film. 19. The method of manufacturing a semiconductor device according to claim 15, characterized by comprising the step of forming a low-resistance layer made of metal or a metal compound on the semiconductor protrusion before forming the interlayer insulating film. 20. The method of manufacturing a semiconductor device according to claim 15, characterized by comprising the step of epitaxially growing Si on the surface of the semiconductor protrusion exposed in the trench after forming the trench. 21. The method of manufacturing a semiconductor device according to any one of claims 15 to 18 and 20, characterized in that it includes the step of: after forming the trench, forming a semiconductor protrusion formed by A low-resistance layer formed of a metal or metal compound.

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