CN100547520C - Computer system and power management method thereof - Google Patents

Abstract

The invention provides a computer system and a power management method thereof. The computer system includes a host processor, a coprocessor, and an instruction stack for storing tasks requiring processing by the coprocessor. The power management method of the computer system comprises the following steps: judging whether a storage bus between the coprocessor and a memory is idle for a specific time; and if the bus between the coprocessor and the memory is idle for the specific time, judging whether the instruction stack is empty or not. And if the instruction stack is empty, a switching command is sent out to enable the coprocessor to enter a low power consumption mode. The main processor with lower power consumption in the computer system can enable the coprocessor with relatively higher power consumption to enter a low power consumption mode, thereby achieving the effect of reducing the power consumption of the computer system.

Description

Computer system and power management method of computer system

technical field

The invention relates to a power management method of a computer system, in particular to a power management method and equipment of a computer system with multiple processors.

Background technique

With the rapid development of integrated circuit technology, multimedia functionality is a basic requirement of consumers for portable devices. Taking the mobile phone as an example, the mobile phone has evolved from a device that was originally used simply for calling to one that can run Window mobile, Symbian, PalmOS and other operating systems, and integrates games, audio playback, video playback, digital photography, and personal information that can be downloaded freely. processing functions. To achieve these functions, the mobile phone can not only connect to the mobile phone network, but also may connect to the wireless local area network and communicate with the PC, or use Bluetooth technology to connect the wireless headset. All these additional functions rely on the battery pack to provide power. In addition, the complexity of the system and functions makes the mobile phone's processor (such as ARM7) have to have higher computing and processing capabilities, which directly leads to increased power consumption of the processor. In fact, in addition to improving the battery itself, improving the power management function of the mobile phone is also an effective way to improve the efficiency of the mobile phone. This is extremely helpful for improving application usage time and battery life, and can significantly increase standby time, talk time or playback time while the user uses all functions of the system.

Therefore, how to maintain a long standby time of the computer system while supporting new functions is an urgent problem to be solved.

Contents of the invention

The purpose of the present invention is to provide a computer system capable of supporting multiple functions and a power management method for reducing power consumption of the computer system.

The invention provides a power management method of a computer system. The computer system includes a main processor, a coprocessor and an instruction stack for storing tasks assigned by the main processor to the coprocessor. The power management method of the computer system includes: judging whether the storage bus between the coprocessor and a memory is idle for a specific time; if the bus between the coprocessor and the memory is idle for the specific time, then It is judged whether the instruction stack is empty. If the instruction stack is empty, a switching command is issued to cause the coprocessor to enter a low power consumption mode.

The present invention further provides a computer system, including: a first processor, a second processor, an instruction stack, a memory, and a computer coupled between the first processor and the second processor bridge. The second processor is used to execute the task assigned by the first processor. The instruction stack is used to store instructions assigned by the first processor to tasks executed by the second processor. The memory is coupled to the second processor through a memory bus, and is used for temporarily storing processing data. The bridge includes a bus state detection unit and an instruction stack state detection unit. The bus state detection unit is used for detecting the state of the storage bus and outputting a timeout signal to indicate that the storage bus is in an idle state. The instruction stack state detection unit is used to detect the state of the instruction stack, and output an instruction stack empty signal to indicate that the instruction stack is empty. The first processor outputs a switch command according to the timeout signal and the instruction stack empty signal, so that the second processor switches from a normal working mode to a low power consumption mode.

The main processor with low power consumption in the computer system of the present invention can make the coprocessor with relatively large power consumption enter the low power consumption mode, and only when the tasks that need to be performed by the coprocessor reach a certain amount, the coprocessor The switch from the low power consumption mode to the normal operation mode can achieve the effect of reducing the power consumption of the computer system.

Description of drawings

The above-mentioned other objects and features of the present invention will become clearer by describing in conjunction with the following embodiments and the accompanying drawings, wherein:

1 is a schematic diagram of a computer system according to an embodiment of the present invention;

Fig. 2 is a detailed schematic diagram of the computer system shown in Fig. 1;

FIG. 3 is a flowchart of a power management method according to an embodiment of the present invention;

FIG. 4 is a flowchart of a power management method according to another embodiment of the present invention.

Detailed ways

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

Generally speaking, there are two general-purpose processor architectures in the computer field, that is, an x86 architecture processor using a complex instruction system and an ARM architecture processor using a simplified instruction system. X86 processors are usually used in personal computers for office work, image processing, and database processing. Compared with the X86 processor, the ARM processor has the characteristics of low cost, low power consumption, and good openness, so it is usually used in consumer electronic products, such as mobile phones and digital cameras. However, computer systems using ARM processors do not support most extended hardware or software devices, for example, cannot process electronic documents such as WORD, EXCEL, PPT, and ACROBAT, thus limiting the improvement of consumer electronics products.

In order to solve the above problems, as shown in FIG. 1 , the present invention provides a computer system 100 including a coprocessor 11 of X86 architecture and a multimedia processor 12, so as to reasonably divide the processing tasks of the computer system 100 to achieve performance and power consumption. Optimization. For example, the coprocessor 11 is used to process tasks with higher performance requirements, such as formula calculation. The multimedia processor 12 is composed of an ARM processor and a graphics processing chip (GPU), and is used for performing routine tasks and processing multimedia information. The computer system 100 also includes a bridge 13 connected to the coprocessor 11 and the multimedia processor 12 for protocol conversion between the coprocessor 11 and the multimedia processor 12 . In this embodiment, the computer system 100 further includes a transmission controller 110 connected to the coprocessor 11, a peripheral controller 120 connected to the multimedia processor 12, and a memory connected to the transmission controller 110 and the multimedia processor 12 respectively. 111, 121. The transmission controller 110 can be implemented by a chipset to control data transmission and communication between the coprocessor 11 and other components. The peripheral controller 120 may be implemented by a westbridge, which is responsible for the communication between the multimedia processor 12 and other components and the direct communication between certain peripherals. As known to those skilled in the art, a power management unit (power management unit, PMU) is usually integrated in the computer system 100 for managing power consumption of the system. For example, the coprocessor 11 based on the X86 architecture can enter the energy-saving modes C0-C5 according to the ACPI (advanced configuration and power interface) specification. The multimedia processor 12 based on ARM architecture can also enter idle mode, sleep mode and shutdown mode.

In order to further reduce the power consumption of the computer system 100, the coprocessor 11 of the computer system 100 of the present embodiment can also enter the link (link) low power according to the active state power management (Active State Power Management, ASPM) mechanism defined by the PCIE specification. consumption mode. As shown in Figure 2, in this embodiment, the multimedia processor 12 can be regarded as the main processor of the computer system 100, responsible for processing daily affairs and multimedia tasks, and the coprocessor 11 is regarded as a PCIE device, used for processing multimedia tasks assigned by the processor 12. The memory 111 is used for temporarily storing data to be processed or processed data. The memory 121 is used for storing system programs and data, and has an instruction stack (instruction stack) 1211 for storing instructions assigned by the multimedia processor 12 to the coprocessor 11 for execution. The bridge 13 is connected to the coprocessor 11 and the multimedia processor 12 through the PCIE bus, and includes a detection module 131 and a protocol converter 132 . The protocol converter 132 is used to complete the protocol conversion between the ARM command (command) and the X86 command.

The detection module 131 includes a bus state detection unit 133 , an instruction stack state detection unit 134 and an output unit 135 . In this embodiment, if the bus state detection unit 133 does not detect that there is a data transmission operation between the memory 111 and the transmission controller 110 within a specific time, and the instruction stack state detection unit 134 detects that the instruction stack 1211 If it is empty, the output unit 135 will output a signal GNT to inform the multimedia processor 12 that the coprocessor 11 can be switched to the link low power consumption mode. Specifically, the bus state detection unit 133 is provided with a bus cycle detection unit 1331 and a timer 1332 . The bus cycle detection unit 1331 is connected to a memory bus (not shown) between the memory 111 and the transmission controller 110 to detect whether there is data transmission between the coprocessor 11 and the memory 111 . The timer 1332 is used to count a specific time, and the specific time is pre-configured by the multimedia processor 12 . When the bus cycle detection unit 1331 detects a data transfer bus cycle (data transfer bus cycle), the timer 1332 is cleared; when the bus cycle detection unit 1331 does not detect the data transfer bus cycle, the timer 1332 Start counting that specific time. If the counting time of the timer 1332 exceeds the specified time, a timeout signal T_OUT is sent to the output unit 135 to indicate that the storage bus has been free for the specified time, that is, there is no communication between the coprocessor 11 and the memory 111 within the specified time. Data transfer operation. The address range of the instruction stack 1211 in the memory 121 is pre-written by the multimedia processor 12 into the corresponding register of the instruction stack state detection unit 134 . The instruction stack state detection unit 134 judges whether the instruction stack 1211 is empty according to the address range of the instruction stack 1211 and the value of the detected stack pointer (stackpointer), and if it is empty, then sends an instruction stack empty signal S_EMPTY to the output unit 135 to indicate that there is no task to be performed by the coprocessor 11 at present. It can be known from the above description that the output unit 135 will output the signal GNT when receiving the timeout signal T_OUT and the instruction stack empty signal S_EMPTY at the same time, indicating that the coprocessor 11 has been idle for a specific time and there is no new task to execute. After the multimedia processor 12 receives the GNT signal sent by the detection module 131, it will send a switching command, so that the coprocessor 11 enters the link low power consumption mode, and the switching command is processed by the protocol conversion module 132 and then output to the coprocessing Device 11. However, since the coprocessor 11 probably still has some background data or processes being processed at this time, it cannot enter the link low power consumption mode. Therefore, in the present embodiment, coprocessor 11 can judge whether there is data or process in processing at present after receiving switching command, if not, then send a response signal ACK to multimedia processor 12 by protocol conversion module 132 and enter Link low power mode. If there is still data or process being processed, no response signal ACK will be sent.

As mentioned above, the coprocessor 11 of this embodiment is a processor of the X86 architecture, so it can enter the processor low power consumption mode C0-C5 according to the ACPI specification. Generally speaking, when the coprocessor 11 wants to enter the low power consumption mode of the processor, it needs to send a special configuration information to the memory 111, and the configuration information will be transmitted from the storage bus to the memory 111 through a configuration cycle (C state configure cycle). memory 111. Therefore, the bus state detection unit 133 of the detection module 131 in this embodiment is further provided with a low power consumption mode recognition unit 1333 for detecting configuration cycles on the storage bus. If the low power consumption mode identification unit 1333 detects a configuration cycle, it sends a signal C_MODE that has entered the low power consumption mode of the processor to the output unit 135. At this time, even if the output unit 135 receives the timeout signal T_OUT and the instruction stack empty signal at the same time S_EMPTY, also does not output signal GNT. That is to say, after the coprocessor 11 of the example of the present invention enters the processor low power consumption mode, the multimedia processor 12 will not issue a command for the coprocessor 11 to enter the link low power consumption mode. It should be noted that if the coprocessor 11 is not an X86 architecture processor, the low power consumption mode identification unit 1333 may not be provided, that is, the output unit 135 outputs the signal GNT only according to the timeout signal T_OUT and the instruction stack empty signal S_EMPTY.

On the other hand, the multimedia processor 12 of this embodiment is provided with a status recording unit 122 and a decision unit 123 . The state recording unit 122 is used to record the working mode of the coprocessor 11 through a processor state value, for example, when the processor state value is 1, it means that the coprocessor 11 is in the normal working mode; when the processor state value is 0, Indicates that the coprocessor 11 is in the link low power consumption mode. The initial value of the state recording unit 122 is the normal working mode. The instruction stack state detection unit 134 also judges whether the remaining size of the instruction stack 1211 is less than a specific value according to the stack pointer and the address range of the instruction stack 1211 , that is, determines whether the instruction stack 1211 is almost full. If the instruction stack 1211 is almost full, output an instruction stack full signal S_FULL to the decision unit 123 of the multimedia processor 12 . The decision-making unit 123 judges whether to output the coprocessor 11 from the link low power consumption mode to commands in normal operating mode. For example, when the decision unit 123 receives the instruction stack full signal S_FULL, if the value of the state recording unit 122 indicates that the coprocessor 11 is in the link low power consumption mode, the output makes the coprocessor 11 switch from the link low power consumption mode It is a command of the normal working mode, and modifies the value of the state recording unit 122. When the decision-making unit 123 receives the signal GNT output by the output unit 134, if the value of the state recording unit 122 indicates that the coprocessor 11 is in the normal operating mode, it outputs a switching command that causes the coprocessor 11 to enter the link low power consumption mode, and Modify the value of the status record unit 122 .

In this embodiment, the memory 111 and the memory 121 may be two physically independent memories, such as DDR, DDR2, etc., or may be two storage spaces located on the same physical memory. As known to those skilled in the art, the coprocessor 11 can read the instruction stack 1211 in the memory 121 through the transmission controller 110 to execute tasks assigned by the multimedia processor 12 (not shown).

FIG. 3 is a flowchart of a power management method for a computer system according to an embodiment of the invention. First, in step S30, the bus state detection unit 133 judges whether the memory bus between the memory 111 and the transmission controller 110 has been idle for a specific time, and if so, executes step S31. In step S31, the instruction stack state detection unit 134 judges whether the instruction stack 1211 is empty, if yes, it means that the X86 processor has neither data to transmit nor new tasks to execute, and thus proceeds to step S32. In step S32, it is judged whether the X86 processor is in the low power consumption mode of the processor, if yes, jump to step S34, if not, make the X86 processor enter the connection low power consumption mode (step S33). After step S33, step S34 is executed to judge whether the instruction stack is about to be stored full, if not, then make the X86 processor remain in the connection low power consumption mode, if so, then make the X86 processor be converted to normal by the connection low power consumption mode working mode (step S35), and end the process.

FIG. 4 is a flowchart of a power management method for a computer system according to another embodiment of the present invention. First, in step S401, if the bus cycle detection unit 1331 does not detect a data transmission bus cycle, then execute step S402, start the timer 1332 to count a specific time. Next, in step S403, it is judged again whether there is a data transmission bus cycle on the storage bus, and if yes, the timer 1332 is cleared (step S404) and then returns to step S401. If no data transmission bus cycle is found in step S403, step S405 is executed to determine whether the timer 1332 has timed out. If the timer 1332 has timed out, that is, the storage bus has been idle for a specific time, then it is determined whether the instruction stack 1211 is empty (step S406 ). If the instruction stack 1211 is empty, that is, the X86 processor has no new tasks to execute and no data to transmit, then step S407 is executed to determine whether the X86 processor is in the processor low power consumption mode. If the instruction stack 1211 is not empty, return to step S401. In step S407, if the coprocessor 11 is in the processor low power consumption mode, the process ends. If the coprocessor 11 is not in the processor low power consumption mode, then judge whether the coprocessor 11 is in the link low power consumption mode (step S408), if not, then send a message to make the coprocessor 11 enter the link low power consumption mode command (step S409). If the coprocessor 11 is in the link low power consumption mode, skip to step S412. After step S410, step S410 is executed to determine whether the coprocessor 11 outputs a response signal ACK according to the received command, if so, it indicates that the coprocessor 11 currently has no data or process to be processed, and enters the connection low power consumption mode (step S411). If in step S410, the coprocessor 11 does not output the response signal ACK, then return to step S401. After step S411, execute step S412 and step S413, when the remaining space of instruction stack 1211 is less than or equal to a certain value, promptly when instruction stack 1211 is about to be full, issue and make coprocessor 11 switch over by link low power consumption mode commands for normal operating mode. Then, it is judged whether the coprocessor 11 outputs the response signal ACK (step S414), if so, it indicates that the coprocessor 11 is converted from the link low power consumption mode to the normal operation mode (step S415), that is, the power management process of the present embodiment is ended . If not, the process ends.

Through the power management process of this embodiment, the multimedia processor 12 with low power consumption in the computer system 100 can make the coprocessor 11 with relatively large power consumption enter the link low power consumption mode according to the ASPM specification, and only when coprocessing is required When the tasks performed by the coprocessor 11 reach a certain amount, the coprocessor 11 will be converted from the link low power consumption mode to the normal working mode, thereby further reducing the power consumption of the computer system 100 .

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

Claims (12)

1. the method for managing power supply of a computer system, described computer system comprises that a primary processor, a coprocessor and are used to store the instruction stack that described primary processor is distributed to the task of described coprocessor processing, it is characterized in that the method for managing power supply of described computer system comprises:

Judge the memory bus idle special time whether between a described coprocessor and the storer;

If idle this special time of the bus between described coprocessor and the described storer judges then whether described instruction stack is empty; And

If described instruction stack is empty, then sends a switching order and make described coprocessor enter a low-power consumption mode.

2. the method for managing power supply of computer system according to claim 1, it is characterized in that, switch order described coprocessor is also comprised before entering the step of a low-power consumption mode sending one: judge whether described coprocessor is in described low-power consumption mode, if not, then send described switching command.

3. the method for managing power supply of computer system according to claim 2 is characterized in that, also comprises:

If described coprocessor is in described low-power consumption mode, whether the remaining space of then judging described instruction stack is less than a particular value; And

If the remaining space of described instruction stack then sends one and makes described coprocessor enter the order of a normal mode of operation less than this particular value.

4. the method for managing power supply of computer system according to claim 1 is characterized in that, described judge the memory bus between a described coprocessor and the storer whether the step of idle this special time comprise:

Judge whether a data transmission bus cycle is arranged on the memory bus between described coprocessor and the described storer; And

If do not have the described data transmission bus cycle on the described memory bus, then start this special time of timer timing;

If the timing time of this timer surpasses this special time, then show described memory bus idle this special time.

5. the method for managing power supply of computer system according to claim 4 is characterized in that, also comprises: if behind the described timer initiation, arranged, then with described timer zero clearing a data transmission bus cycle on the described memory bus.

6. the method for managing power supply of computer system according to claim 1 is characterized in that, also comprises:

Judge whether described coprocessor enters a processor low-power consumption mode according to the ACPI standard;

If then finish the power management flow process.

7. a computer system is characterized in that, comprising:

One first processor;

One second processor is used to carry out the task that described first processor distributes;

One instruction stack is used to store the instruction that described first processor is distributed to the task of described second processor execution;

One storer is coupled to described second processor by a memory bus, with temporary deal with data;

One bridge is coupled between described first processor and described second processor, comprising:

One bus state detecting unit is used to detect the state of described memory bus, and exports a timeout signal, is in idle condition to represent described memory bus;

One instruction stack state detecting unit is used to detect the state of described instruction stack, and exports an instruction stack spacing wave, is sky to represent described instruction stack; And

Wherein, described first processor switches order according to described timeout signal and instruction stack spacing wave output one, so that described second processor switches to a low-power consumption mode by a normal mode of operation.

8. computer system according to claim 7 is characterized in that, described bus state detecting unit comprises:

One bus cycles detecting unit is used to detect the data transmission bus cycle on the described memory bus;

One timer, the bus cycles detecting unit detects the data transmission bus cycle as described, this timer zero clearing; The bus cycles detecting unit does not detect the data transmission bus cycle as described, then this timer special time that picks up counting; And

Wherein, described bus cycles detecting unit is not if detect the data transmission bus cycle, and the timing time of this timer then should can be exported described timeout signal by the bus cycles detecting unit above this special time.

9. computer system according to claim 8 is characterized in that, the remaining space that described instruction stack state detecting unit detects described instruction stack is exported the full signal of an instruction stack to described first processor during less than a particular value.

10. computer system according to claim 9, it is characterized in that, described first processor is provided with a decision package, is used for making described second processor be switched to the order of normal mode of operation by low-power consumption mode according to full signal of described instruction stack and processor state value output one; And a state recording unit, be used to write down the described processor state value of described second processor, and export described processor state value to described decision package.

11. computer system according to claim 7 is characterized in that, described bus state detecting unit is provided with a low-power consumption mode recognition unit, is used for exporting a low-power consumption mode signal according to the configuration cycle on the described memory bus.

12. computer system according to claim 11, it is characterized in that, this bridge also comprises an output unit, it receives this low-power consumption mode signal, as this moment this output unit receive this timeout signal and this instruction stack spacing wave simultaneously, will can not export the described switching command that makes this second processor enter this low-power consumption mode.

Images