CN100544212C - High-speed LDPC decoder with reduced memory requirements - Google Patents

Abstract

The invention discloses a high-speed low-density check code decoder with reduced storage requirements, which includes a parameter node calculation unit VPU module, a check node calculation unit CPU module and a control logic module; the VPU module receives a sequence to be decoded, Store the original information and start iterative decoding. During the iterative decoding process, the CPU module and the VPU module transfer information to each other, respectively perform row operations and column operations, and the CPU stores the verification operation results; the control logic module controls the VPU module and the CPU module. The loop operation is controlled, and the legal codeword obtained by decoding is output. Aiming at shifted LDPC codes, the invention fully utilizes the minimum sum decoding algorithm to reduce storage requirements and highly parallelizes to increase decoding rate, saves message storage requirements, and achieves faster decoding speed and higher throughput rate.

Description

The loe-density parity-check code decoder of minimizing storage demand at a high speed

One, technical field

The invention belongs to the fec arrangement in the digital communication system, can in channel coding method is the Modern Communication System of LDPC sign indicating number, adopt, be particularly useful in the communication system of high decoding speed high-throughput requirement.

Two, background technology

The transmission of data in communication system through regular meeting because noise etc. is a series of former thereby cause various mistakes, because the existence of these mistakes has limited the speed of message transmission and the quality of transmission thereof greatly.Therefore, communication system generally uses the encoding and decoding technique of signal to guarantee reliable communication on the noisy communication channel.The dreamboat of coding techniques is to reach shannon limit in the communication system (Shannon ' s limit).In present existing coding method, low-density checksum (LDPC) coding method has shown the coding efficiency near shannon limit in some cases.

The LDPC sign indicating number to use now more Turbo code and have similar performance, one of their main difference is that the decoding of LDPC sign indicating number is easier, is more suitable in parallel processing in essence.In addition, has long minimum range between LDPC sign indicating number code word, to such an extent as to compare with Turbo code, the error of LDPC sign indicating number flat (error floor) appears at very low error rate zone, and the wrong code word probability that can't detect be one extremely low very near 0 value.The LDPC sign indicating number has caused very big concern because of its remarkable performance, and is widely regarded as up-and-coming error correction/encoding method in the communication system applications.

The LDPC sign indicating number is as a kind of linear block codes, and most of elements of its parity check matrix H are " 0 ", so be called " low-density ".It is the process of the continuous transmission information (message passing) of an iteration that the information of LDPC is propagated (blief propogation) decoding algorithm.Iteration through certain number of times makes the signal phasor that solves satisfy all check equations, and promptly multiplying each other with parity matrix is 0.

The type solution code calculation of LDPC sign indicating number is sum-product algorithm (Sum product algorithm).For this interpretation method, to the parameter node, the updating message that obtains will add up with the information of the check-node that links to each other with it, this be " with "; Equally, to check-node, the updating message that obtains is the long-pending form of all parameter nodal informations that are attached thereto, and this is " amassing "; Close and be called " with long-pending ".Sum-product algorithm is exactly the iteration transmission that utilizes parameter node and the direct updating message of check-node, seeks the correct code word that satisfies all check equations.

The decoding algorithm of general LDPC sign indicating number is to use log-likelihood ratio (Log-likelihood Ratio, Log likelihood ratio) to calculate confidence spread (LLR-Belief Propagation, LLR-BP) algorithm that diffuses information.It utilizes the LLR value to replace genuine probable value, avoids the multiplying in the sum-product algorithm, so that hardware is realized.The LLR-BP algorithm is actual to be the algorithm identical with sum-product algorithm.The LLR-BP algorithm has superior performance, and when the length long enough of code word, it will approach the channel capacity limit of Shannon theory.Yet the LLR-BP algorithm has used Log function and super tangent (tanh) function in the iterative decoding processing procedure, has always increased the difficulty of complexity of calculation and realization.

Therefore, people have proposed the approximate data simplified, the BP-based approximate data (it is approximate to be commonly referred to as " min-sum ") that proposes as people such as Chen and Fossorier etc.These algorithms are compared the complexity and the decoding performance that have reduced iterative decoding and are descended seldom with the LLR-BP algorithm.The Min-sum algorithm has avoided the LLR-BP algorithm to use complicated function in the iterative decoding process, but selects to have the bit value of minimum LLR from a plurality of bits relevant with given parity check equations, and this has reduced decoding complex degree widely.

The basic procedure of Min-sum algorithm is as follows:

1, initialization process is determined the value Z of parameter node _Mn, Z _MnFor each enters code element y at first _nValue.

2, row is handled (check-node operation).Z _MnFor propagating into the likelihood probability of check-node " m " from parameter node " n ", N (m) n represent the set of all the parameter nodes except n parameter node that link to each other with m check-node, L _Mn ⁽ⁱ⁾Be the reliability information that is transmitted to parameter node " n " by check-node " m ", subscript i represents iteration the i time.Finish the renewal of check-node by equation (1) to the parameter nodal information.

$L_{\mathrm{mn}}^{\left(i\right)}=\underset{n\′\∈N\left(m\right)\backslash n}{\mathrm{\Π}}\mathrm{sign}\left(Z_{\mathrm{mn}\′}^{(i-1)}\right)\×\underset{n\′\∈N\left(m\right)\backslash n}{\min }\left|Z_{\mathrm{mn}\′}^{(i-1)}\right|)---\left(1\right)$

3, row are handled (parameter nodal operation).L _n ⁽⁰) initial value that receives for channel, M (n) m represent to link to each other with parameter node " n " except m check-node the set of all check-nodes.Finish of the renewal of parameter node by equation (2) formula to check-node information.

$Z_{\mathrm{mn}}^{\left(i\right)}=L_n^{\left(0\right)}+\underset{m\′\∈M\left(n\right)\backslash m}{\mathrm{\Σ}}{L}_{m\′n}^{\left(i\right)}---\left(2\right)$

4, decoding.Z _n ⁽ⁱ⁾Value calculate by equation (3) and finish, if Z _n ⁽ⁱ⁾〉=0, C then _n=1, if Z _n ⁽ⁱ⁾＜0, C then _n=0.The value of code element c is just obtained like this.The LDPC decoder is carried out parity check equation, to determine whether the result is satisfied with.If check equations obtains well satisfying, then this decoding finishes.If this check equations fails to satisfy, then repeated execution of steps 2,3, correctly or to decoding reach maximum iteration time up to decoding.

$Z_n^{\left(i\right)}=L_n^{\left(0\right)}+\underset{m\′\∈M\left(n\right)}{\mathrm{\Σ}}{L}_{m\′n}^{\left(i\right)}---\left(3\right)$

Such decoding algorithm has been simplified complexity of decoding greatly, and simultaneously it does not need to know some information about channel noise, and this has brought very big easy to practical application.But this has also caused the decline on the decoding performance, therefore, equation (2) is increased by weights, to improve its decoding performance.To dissimilar LDPC sign indicating numbers,, can make the performance of the decoding performance of min-sum algorithm and LLR-BP algorithm suitable by selecting suitable α value.

$Z_{\mathrm{mn}}^{\left(i\right)}=L_n^{\left(0\right)}+\mathrm{\α}\underset{m\′\∈M\left(n\right)\backslash m}{\mathrm{\Σ}}{L}_{m\′n}^{\left(i\right)}---\left(4\right)$

By the simplification of decoding algorithm, greatly reduce the complexity that the LDPC decoder is realized.But the implementation complexity of high performance LDPC sign indicating number decoder is still higher, and this also is a reason also not adopted widely of LDPC sign indicating number up to the present.

Some LDPC sign indicating number decoder architectures of Ti Chuing mainly all were to adopt half parallel structure in recent years, promptly added parallel composition in serial process, to solve the wiring complexity issue in the Parallel Implementation.But this just must increase memory to preserve the intermediate object program in the decode procedure, has caused the decoder area to increase, and has also reduced decode rate simultaneously.Up to the present, also there is not a kind of structure to address these problems.

Three, summary of the invention

The object of the present invention is to provide a kind of loe-density parity-check code decoder of minimizing storage demand of high speed, this decoder has overcome the deficiencies in the prior art, the only storage that the result of line operate is compressed, reduced the decoding storage demand, have high degree of parallelism, can reach very high decoding speed and throughput.

The objective of the invention is to be achieved through the following technical solutions:

A kind of loe-density parity-check code decoder of minimizing storage demand of high speed is characterized in that: it comprises parameter node computing unit (VPU) module, parity check nodes computing unit (CPU) module and control logic module; The CPU module receives sequence to be decoded, stores this raw information and begins iterative decoding, information is passed to the VPU module carry out the parameter nodal operation; The VPU module is sent the operation result into the CPU module and is gone check-node operation and storage operation result; Control logic module is controlled the cycling of VPU module and CPU module, and the legal-code that obtains of output decoder.

Among the present invention, described iterative decoding contains successively and has the following steps:

1. receive sequence to be decoded, and store this raw information;

2. the maximum iterations that allows is set, with iterations zero setting, the beginning iterative decoding; Object LDPC sign indicating number is (N, M) (c, regular LDPC sign indicating number t), P=N/t=M/c;

3. P is listed as operation, i.e. the parameter nodal operation;

4. the result of row operation is sent into the check-node arithmetic element and carry out line operate, be i.e. check-node operation, and storage operation result; The operation of every row is divided into t time to be carried out, and M is capable to be handled simultaneously;

5. repeating step 3., 4. finish up to whole matrix manipulation is then finished iteration one time;

6. when decoding obtains a legal-code or reach maximum allowing iterations, stop decoding, the code word that output decoder obtains.

The CPU module comprises verification operation part, message output and symbol storage area among the present invention; Verification operation is partly finished check-node to the renewal of parameter nodal information and the storage and the transmission of line operate result; It is the result of last iteration that the message output provides the needed information of row operation to the VPU module; The symbol storage area is used for storing nearest input symbol of message position.

In CPU part of the present invention,, specific as follows comprising the decoding process of the cyclic shift of CPU and the configuration of information memory cell (register) thereof:

(1) information storage means of the memory cell old_reg of CPU, new_reg and signreg;

(2) old_reg of CPU, the new_reg displacement mode in each iterative process, and when each iteration finishes new_reg to the mapping mode of old_reg;

(3) CPU selection mode that corresponding VPU is given information.

At the message output of CPU of the present invention, the sizes values that CPU gives information to VPU is judged selection by the index of register.The index value is in t time of iteration operation among the new_reg, zero setting when finding minimum value, otherwise carry out from add operation.The old_reg value is given by new_reg when each iteration finishes, and wherein the index value is proceeded from add operation in the old-reg transmittance process, when the index value is t, should the value of cycle VPU from CPU is second minimum value then, otherwise is minimum value.

The class LDPC sign indicating number that decoder was suitable among the present invention is called displacement LDPC sign indicating number, and its make as depicted in figs. 1 and 2.Displacement LDPC sign indicating number is a kind of LDPC (1 number of the identical and every row of 1 number of every row is identical) sign indicating number of rule.Consider that a row is the LDPC sign indicating number of c for the t column weight heavily, decomposes its check matrix as shown in Figure 1.Check matrix H is by c * t sub-matrix H _IjForm, each submatrix is the square formation of a P * P, and the row of each square formation is heavy to be 1 with column weight.This LDPC sign indicating number information bit K=P*t then, the bit number M=P*c of verification, code word size N=K+M.Fig. 2 has illustrated the make of displacement LDPC numeral matrix with a simple example:

1) at first constructs H _I1, i.e. c square formation of first row, they are to obtain after being exchanged by the random column of unit matrix, and every row contains one 1 in the P * P square formation that has guaranteed to obtain, and every row contain one 1.

2) then for each square formation that obtains, will wherein all 1 move up 1, the top move on to below, then obtained secondary series submatrix H _I2

3) continue to obtain all submatrixs on the right by that analogy.

The check matrix that constructs according to this generally has the capable redundancy of c, the code check R of displacement LDPC sign indicating number〉c/ (c+t).Displacement LDPC sign indicating number has certain randomness, and its error-correcting performance is suitable with general random LDPC sign indicating number as can be known by emulation.

The present invention is by adopting improved minimum and decoding algorithm, at displacement LDPC sign indicating number, the decoding device of design conserve memory demand at a high speed.

The present invention has following characteristics:

(1), it is a kind of decomposition check node calculation step, and utilizes calculating intermediate object program constantly to transmit to satisfy the LDPC sign indicating number decoding policy that is correctly decoded between parity check nodes;

(2), it is preservation and their the continuous transmission between parity check nodes that utilizes line operate intermediate object program, reduces the line between parity check nodes arithmetic element and the parameter node arithmetic element.Only need keep in communication to reach each parity check nodes arithmetic element with a parameter node arithmetic element.

(3) utilize the min-sum decoding algorithm, the external information of transmitting mutually between parameter node and the parity check nodes is only stored the message of parity check nodes to the parameter node, the i.e. result of line operate or intermediate object program.And the mode with compression is stored, and only stores minimum value, second minimum value, minimum value position and sign bit, reaches the purpose that reduces storage demand.

(4), the present invention is not effective to any LDPC sign indicating number, and only effective to displacement LDPC sign indicating number, but the LDPC sign indicating number of structure is arranged for other, as half circulation (Quasi-Cyclic) LDPC sign indicating number, can be mapped to again on this framework through the form that rank transformation is converted into displacement LDPC sign indicating number and realize.

(5), realization of the present invention needs parameter node arithmetic element N/t, parity check nodes arithmetic element M, wherein each parity check nodes arithmetic element has only the input of a message in a clock cycle, and the parity check nodes arithmetic element of the general LDPC decoder of logic that its realization is shared is wanted much less.

The present invention makes full use of minimum and decoding algorithm reduces storage demand and highly-parallel realizes improving decode rate.It has reduced the wiring complexity than general full parallel decoding framework, has saved the message stores demand, can carry out the longer LDPC sign indicating number decoder design of long code; Compare general serial or half code parallel decoder,, can reach the throughput of decoding speed and Geng Gao faster because the message stores demand has been saved in the storage that the present invention only compresses the result of line operate.

Studies show that the present invention can save 70% external information storage demand to high code rate LDPC code, and in serial or part parallel decoder, the external information memory usage area of chip more than 70%.And degree of parallelism height of the present invention can be finished iteration one time with t clock cycle, and this will obtain than serial or faster decoding speed and the higher throughput of part parallel decoder.

Four, description of drawings

Fig. 1: the total structure mode figure of displacement LDPC code check matrix;

Fig. 2: the make figure of displacement LDPC code check matrix;

Fig. 3: decoding order schematic diagram;

Fig. 4: CPU first, verification operation part schematic diagram;

Fig. 5: CPU second portion, message output schematic diagram;

Fig. 6: CPU third part, symbol storage area schematic diagram;

Fig. 7: three kinds of register schematic diagrames that are used for storing external information;

Fig. 8: line operate result register cyclic shift schematic diagram;

Fig. 9: be the VPU configuration diagram;

Figure 10: the floor plan that is embodiment;

Figure 11: the layout figure that is embodiment.

Five, embodiment

A kind of loe-density parity-check code decoder of minimizing storage demand of high speed of the present invention, it comprises parameter node computing unit VPU module, parity check nodes computing unit CPU module and control logic module; Parameter node computing unit (VPU) receives sequence to be decoded, store this raw information and begin iterative decoding, in the iterative decoding process, CPU module and VPU module are transmitted information mutually, carry out line operate and row operation separately, and by CPU storage verification operation result; Control logic module is controlled the cycling of VPU module and CPU module, and the legal-code that obtains of output decoder.

The algorithmic descriptions of principle of the present invention and employing is as follows:

Suppose that check matrix H is made up of c * t sub-matrix, each submatrix is the square formation of a P * P.Then this decoder comprises P parameter node processing unit (VPU) and M=c * P code check node processing unit (CPU).Each decoding iteration needs t clock cycle.Each cycle has P VPU and M CPU to carry out data processing operation simultaneously.The annexation of CPU and VPU determines that by the first row submatrix of check matrix H each VPU links to each other with c CPU, and each CPU links to each other with 1 VPU.With matrix shown in Figure 3 is example, and VPU1 links to each other with CPU4,5, and VPU2 links to each other with CPU2,7, analogizes therewith.

CPU partly is a key component of the present invention.Following elder generation elaborates to the framework of CPU.

CPU finishes check node calculation, specifically can promptly find out two and the multiplication of all sign bits of absolute value minimum in t message corresponding to certain delegation referring to formula (1).The CPU part mainly comprises checked operation part, message output, sign bit storage area and relevant register storage area.

Fig. 4 has represented the first of CPU: the verification operation part.Press the decoding order of Fig. 3, we resolve into t time with every row operation and carry out, only import data (information of transmitting to this check-node that obtains by present clock period parameter node processing units row operational computations) at every turn, its size is compared with two minimum values in the existing intermediate object program (the new_reg register by a last check-node that links to each other with this check-node provides), upgrade two minimum values.If the value of input message becomes new minimum value, then be necessary to upgrade the minimum value position, be about to the index amount and put 0, otherwise index will add 1 certainly.In addition, multiplied each other in the sign position of input symbol of message position and existing intermediate object program (being XOR).Deposit these four result: minimum value min, the second minimum value 2nd-min, minimum value position index and sign bit sign in register Reg_new at last.The concrete selection mode of two minimum values is as follows: input information value magnitude (absolute value) compares with the min value that a last check-node transmits, if this value of information is less than min, then the min value is substituted by this value of information, former min value is as new 2nd-min value, upgrade the index value simultaneously, with the zero setting of index value; If the input information value is greater than the min value, then min remains unchanged, and oneself adds index value, selects less one with stylish 2nd-min value in input information value and former 2nd-min value.

Fig. 5 has represented the second portion of CPU: the message output.The line operate result (being provided by old_reg) of last iteration is provided from a last adjacent C PU for it, the symbol place value that provides according to value and the CPU third part of index extracts this moment corresponding check node to the message of parameter node, be transferred to continuous VPU, finish of the renewal of these row parameter node to check-node information for it.After this clock cycle finished, the old_reg value of this check-node continued to transmit to its next adjacent CPU.The concrete selection of subtend VPU input message is as follows: sign bit carries out XOR by respective symbol position among the signreg of the sign bit among the old_reg and this check-node and obtains.Choosing by index of data value judged, if the index value equates that with t then the biography of this output is 2nd-min to the value size of VPU, otherwise is min.Index continues after adding, and provides the result to its next adjacent C PU.

Fig. 6 has represented the third part of CPU: the symbol storage area.It only is made up of the FIFO of a t position, ejects a sign bit in each clock cycle and squeezes among this FIFO for the use of CPU second portion and with the current VPU of obtaining symbol of message position.

Here, designed (8192,7168) (4,32) regular QC-LDPC sign indicating number decoder and made example, at first it has been converted to the form of displacement LDPC sign indicating number, and adopted the decoder described in the present invention fully.It is example that this decoder adopts four bit quantizations.

Respectively used one group of register in Fig. 4,5,6, Fig. 7 understands the content of these register-stored specifically.New_reg stores the line operate object information of current current iteration, comprising current minimum value min, the current second minimum value 2nd-min, current minimum value position index with as the long-pending sign of all sign bits of pre-treatment.The line operate object information of old_reg storage previous iteration is comprising the long-pending sign of minimum value min, the second minimum value 2nd-min, minimum value position index and all sign bits.The signreg sequential storage enter 32 symbol of message positions of this CPU recently.

Fig. 8 is core of the present invention, promptly by shift register the intermediate object program of line operate is constantly transmitted between CPU, and this transmission is the transmission of CPU in turn very regularly.The purpose of doing like this is to make t message that each CPU handles in t the clock cycle of an iteration all from same VPU, and has reduced line between CPU and the VPU with this, has overcome the bottleneck of complete Parallel Implementation LDPC decoding.Can see that in Fig. 8 old_reg also in transmission constantly, has also guaranteed that in like manner the message of each CPU output all offers same VPU.When each iteration finished, when also promptly 32 steps of a line operate were finished, the result changed old_reg over to by new_reg with this iteration, offered in the next iterative process check-node to the generation of parameter node messages.

Cooperating Fig. 3 below, specify its operation principle, be simplified illustration, is example with first row matrix only.By Fig. 3, VPU1,2,3,4 links to each other with CPU4,2,3,1 respectively, and this annexation is constant all the time in iterative process.In first cycle, first piece to be operated, the information after VPU handles is stored in respectively in the register of the CPU that is attached thereto, leaves among the CPU2 as the result of VPU2.Second clock cycle, to second capable processing of piece, meanwhile, as Fig. 8, the value among the CPU (comprising the value among old_reg and the new_reg) circulates successively and moves down one, moves among the CPU3 as the value among the former CPU2.At this moment, CPU3 still links to each other with VPU3, this cycle VPU3 utilizes the value of the old_reg from CPU3 to finish the renewal of parameter node to check-node information, calculating the value of gained handles via CPU3, deposit in its new_reg register, can see, be still the row that this matrix second row is carried out so in essence and handle.Pass through t clock cycle so successively, finish the operation of whole row, promptly finish the once renewal of check-node to the parameter nodal information.Finish the mapping of new_reg by the mode among Fig. 8 again, beginning iterative decoding process next time to old_reg.By such decoder architecture, greatly reduce the line between CPU and the VPU.

Fig. 9 has represented the configuration diagram of VPU, and it has finished the calculating of formula (2) and (3), and the scale module has been finished in (4) about scale operation or the operation of removing side-play amount (offset).It and general VPU framework are similar.

Figure 10 and Figure 11 have showed the floor plan (floorplan) and the layout figure (layout) of this design example, and this design is based on 6 layers of smithcraft of the SMIC of SMIC 0.18 μ m and carries out.In Figure 10,1024 array of small squares at center are represented 1024 CPU, and 256 peripheral big squares are represented 256 VPU.Can guarantee that with arranging regularly among CPU such as Figure 10 the transmission between the CPU shift register is local communication mostly, reduce the wiring difficulty like this.Can be by seeing among Figure 11, the design's wiring complexity mainly concentrates among the CPU array, and complicated originally CPU and the interconnection between VPU no longer are problems.

Below provide some data effect of the present invention is described.Demand for the external information storage, with (8192,7168) (4,32) regular LDPC sign indicating number 6bit is quantified as example, common LDPC decoder architecture needs the memory space of 6 * 8192 * 4=196608bit at least, and framework of the present invention only needs the memory space of (16+16+32) * 1024=65536bit, has saved nearly 70% external information storage demand, and in serial or part parallel framework, the external information memory usage area of chip more than 70%.And framework degree of parallelism height of the present invention can be finished once with t clock cycle

Iteration, this will obtain than serial or faster decoding speed and the throughput of part parallel framework.

Compare with parallel fully decoder architecture, full parallel architecture realizes 1/2 code check under 0.16 μ m technology, and the LDPC sign indicating number decoder of 1024bit code length needs the area of 7mm * 7mm, and throughput is 1Gbps.Its chip is in order to hold complicated wiring, and the logic utilance only is 50%.Utilize framework of the present invention, under 0.18 μ m technology, realize code check〉the LDPC sign indicating number decoder of 0.875,8196 code length only needs the area of 4mm * 4mm, and working clock frequency can reach 200MHz, throughput is 3.2Gbps (being assumed to be iteration 16 times), and the logic utilance is 70%.

Claims (2)

1. A high-speed low-density check code decoder that reduces storage requirements, is characterized in that: it includes a parameter node calculation unit module, a check node calculation unit module and a control logic module; the parameter node calculation unit receives the Decode the sequence, store the original information and start iterative decoding. During the iterative decoding process, the check node computing unit module and the parameter node computing unit module transfer information to each other, perform row operations and column operations respectively, and are calculated by the check node The unit stores the result of the check operation; the control logic module controls the loop operation of the parameter node calculation unit module and the check node calculation unit module, and outputs the legal codeword obtained by decoding; the intermediate result of the row operation is passed through the shift register Constantly transfer between the check node calculation units; the check node calculation unit includes a check operation part, a message output part and a symbol storage part; the check operation part completes the update of the check node to the parameter node information and the row Storage and delivery of operation processing results; the message output part provides the information required by the column operation to the parameter node calculation unit, that is, the result of the last iteration; the symbol storage part is used to store the sign bit of the latest input message. 2. The high-speed low-density check code decoder with reduced storage requirements according to claim 1, wherein said iterative decoding comprises the following steps in sequence: ① Receive the sequence to be decoded and store the original information of the sequence to be decoded; 2. Set the maximum allowable number of iterations, set the number of iterations to zero, and start iterative decoding; the object LDPC code is a regular LDPC code of (N, M) (c, t), and the number of check matrix rows is N and the number of columns is M. Wherein N is the code length of LDPC codes, M is the number of checks, c is the number of "1" in each column of the check matrix, and t is the number of "1" in each row of the check matrix; make P=N/t =M/c is the size of each sub-matrix in the check matrix of the LDPC code; ③ Perform column operations on P columns from left to right at the same time, that is, parameter node operations; ④ Send the result of the column operation operation to the check node operation unit for row operation, that is, the check node operation, and store the operation result; the row operation of each row is divided into t times, and M rows are processed at the same time; ⑤Repeat steps ③ and ④ until the entire check matrix operation ends, then one iteration is completed; ⑥ When a legal codeword is obtained or the maximum allowable number of iterations is reached, stop decoding and output the codeword obtained by decoding.

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