CN100544002C - memory structure and preparation method thereof - Google Patents

Abstract

A memory structure comprises a semiconductor substrate, an active region arranged in the semiconductor substrate, a plurality of doped regions arranged in the semiconductor substrate, a first conductive plug electrically connected with a bit line and one of the doped regions, and a second conductive plug electrically connected with a capacitor and the other doped region. The first conductive plug comprises a first block arranged in the active area and a second block arranged at the first side edge of the active area, and the bit line is connected with the second block of the first conductive plug. The second conductive plug comprises a third block arranged in the active area and a fourth block arranged on the second side edge of the active area, and the capacitor is connected to the fourth block of the second conductive plug.

Description

Memory structure and preparation method thereof

technical field

The invention relates to a memory structure and a preparation method thereof, in particular to a memory structure with conductive plugs respectively extending to opposite sides of an active area and a preparation method thereof.

Background technique

In recent years, the number and density of storage units of a dynamic random access memory (DRAM) chip have increased significantly. Each memory cell is composed of a metal oxide semiconductor field effect transistor (MOSFET) and a capacitor, wherein the source of the transistor is electrically connected to the lower electrode of the capacitor. Capacitors can be divided into two types: stacked and deep trench. Stacked capacitors form capacitors directly on the surface of the silicon substrate, while deep trench capacitors form capacitors inside the silicon substrate.

FIG. 1 shows a known DRAM 100, which was disclosed in Symposium on VLSI Technology Digest of Technical Papers in 2005 by the researchers of Samsung electronics. The DRAM 100 includes a plurality of word lines 102 , a plurality of bit lines 104 , and a plurality of obliquely disposed active regions 106 . A bit line plug 108 is disposed in the middle of the active region 106 , and two capacitor plugs 110 are disposed at both ends thereof. Specifically, the DRAM 100 adopts a memory cell design of 6F ² , that is, 2F (word line)×3F (bit line)=6F ² , where F represents the minimum feature size.

However, the DRAM 100 must use double exposure technology (DET) to prepare a plurality of active regions 106 that are electrically isolated from each other and arranged obliquely. However, the double exposure technology is not suitable for mass production exposure machines in the industry at present. . Furthermore, the size of the capacitor plug 110 disposed between the two word lines 102 is 1F, and advanced photolithography technology (such as photolithography immersion technology) must be used to ensure the accuracy of its size and position.

FIG. 2 shows another known DRAM 120, which was disclosed in Symposium on VLSI Technology Digest of Technical Papers in 2004 by the researchers of Microntechnology. The DRAM 120 includes a plurality of word lines 122 , a plurality of bit lines 124 , and a plurality of obliquely disposed active regions 126 . A bit line plug 128 is disposed in the middle of the active region 126 , and two capacitor plugs 130 are disposed at two ends thereof. Compared with the DRAM 100 of FIG. 1, only its active region 106 is set obliquely. The DRAM 120 of FIG. The intersection of the active area 126 and the bit line 124 .

Contents of the invention

The main purpose of the present invention is to provide a memory structure and its fabrication method, which have conductive plugs respectively extending to opposite sides of the active region, thereby reducing the need for advanced photolithography techniques.

To achieve the above object, the present invention proposes a memory structure, which includes a semiconductor substrate, an active region disposed in the semiconductor substrate, a plurality of doped regions disposed in the semiconductor substrate, electrically connected bit lines and the plurality of A first conductive plug in one of the doped regions and a second conductive plug electrically connected to the capacitor and the other doped region. The first conductive plug includes a first block disposed in the active region and a second block disposed on the first side of the active region, and the bit line is connected to the first conductive plug through the bit line plug. Plug the second block. The second conductive plug includes a third block disposed in the active area and a fourth block disposed on a second side of the active area, and the capacitor is connected to the second conductive plug through a capacitor contact plug. Plug the fourth block. Preferably, the width of the first block is twice that of the second block, the width of the third block is twice that of the fourth block, and the first side and the second side of the active region The two sides are opposite sides of the active area.

According to the above purpose, the present invention proposes a method for preparing a memory structure, which includes forming a first etching mask on a substrate containing a dielectric structure, partially removing the dielectric structure other than the first etching mask to form a plurality of dielectric structures. The electric pillars and the plurality of first openings are between the plurality of dielectric pillars, forming a second etching mask covering the partial surface of the plurality of dielectric pillars, removing the partial surface not covered by the second etching mask Dielectric pillars are used to expand the first opening to form a second opening, and forming conductive plugs in the second opening.

The step of forming the second etching mask first forms a silicon-containing layer (such as a polysilicon layer) covering the plurality of dielectric pillars, and then performs at least an oblique doping process to implant impurities (such as boron difluoride) into a predetermined portion changing the chemical properties of the predetermined portion of the silicon-containing layer. Afterwards, a wet etching process is performed using ammonia water to remove the silicon-containing layer other than the predetermined portion, and the predetermined portion of the silicon-containing layer forms the etching mask. Preferably, before performing the oblique doping process, a third doping mask covering the bottom of the first opening may be additionally formed to prevent impurities from being implanted into the semiconductor substrate through the first opening during the subsequent oblique doping process. The internal, which affects the electrical characteristics of the prepared electronic components.

Compared with the known memory structure, when technology advances to the nanometer era (F is less than 100 nanometers), repeated exposure technology must be used and advanced photolithography technology must be used to define the size and position of its capacitor plug (i.e. contact hole). The fabrication of the memory structure does not require repeated exposure techniques, and does not require the use of advanced photolithography techniques (such as photolithographic immersion techniques) to define the size and location of the contact holes (ie, the capacitor plugs).

Description of drawings

Fig. 1 represents known DRAM;

Fig. 2 represents another known DRAM;

Fig. 3 to Fig. 16 represent the preparation method of the memory structure of the first embodiment of the present invention; And

FIG. 17 to FIG. 19 show the manufacturing method of the memory structure according to the second embodiment of the present invention.

Description of main component marking

10 memory structure 12 semiconductor substrate

13A doped region 13B doped region

14 character line 16 silicon nitride spacer

18 Silicon nitride layer 20 Dielectric structure

22 Silicon oxide layer 24 Silicon oxide layer

30 substrate 32 first etch mask

36A Dielectric cylinder 36B Dielectric cylinder

38 First opening 40 Silicon-containing layer

42 doping mask 44 predetermined area

46 Active Region 48 Doping Mask

50 second etch mask 52 second opening

54 The first conductive plug 54A The first block

54B Second Block 56 Second Conductive Plug

56A third block 56B fourth block

58 dielectric layer 60 position line contact plug

62 bit line 64 silicon nitride mask

66 Silicon nitride spacer 68 Silicon oxide layer

70 photoresist layer 72 linear opening

74 Contact hole 76 Capacitor plug

78 Capacitor 82 Lining oxide layer

82' doping mask 84 photoresist layer

100 DRAM 102 Character lines

104 bit lines 106 active regions

108 bit line plug 110 capacitor plug

120 DRAM 122 Character lines

124 bit lines 126 active areas

128 bit line plug 130 capacitor plug

Detailed ways

Fig. 3 to Fig. 16 show the preparation method of the memory structure 10 of the first embodiment of the present invention, wherein Fig. 3 (a) and Fig. 3 (b) are the partial cross-sections of Fig. 3 along the section line 1-1 and 2-2 respectively picture. Firstly, a first etching mask 32 (such as a photoresist layer) is formed on the substrate 30 . The substrate 30 includes a semiconductor substrate 12, a plurality of doped regions 13A and 13B disposed in the semiconductor substrate 12, a plurality of word lines 14 disposed on the semiconductor substrate 12, and nitrogen covering the side walls of the plurality of word lines 14. Si spacers 16 , a silicon nitride layer 18 covering the surface of the semiconductor substrate 12 , and a dielectric structure 20 covering the plurality of word lines 14 and the silicon nitride layer 18 . The dielectric structure 20 includes a silicon oxide layer 22 and a silicon oxide layer 24 , and the first etch mask 32 is formed on the silicon oxide layer 24 . The material of the silicon oxide layer 22 can be borophosphosilicate glass (BPSG), and the material of the silicon oxide layer 24 can be tetraethylorthosilicate (TEOS).

Referring to FIG. 4( a ) and FIG. 4( b ), they are partial cross-sectional views of FIG. 3 along section lines 1-1 and 2-2 respectively. Next, an anisotropic dry etching process is performed to partially remove the dielectric structure 20 outside the first etching mask 32 until the surface of the silicon nitride layer 18 to form a plurality of dielectric pillars 36B and a plurality of first openings 38 in the silicon nitride layer 18. Between the plurality of dielectric pillars 36B. Next, after removing the first etching mask 32, a deposition process is performed to form a silicon-containing layer (such as a polysilicon layer) 40 covering the surfaces of the plurality of dielectric pillars 36B, as shown in Figure 5(a) and Figure 5( As shown in b), it is a partial cross-sectional view of Fig. 3 along the section lines 1-1 and 2-2 respectively.

Referring to Fig. 6, Fig. 6(a) and Fig. 6(b), Fig. 6(a) and Fig. 6(b) are partial sectional views of Fig. 6 along section lines 1-1 and 2-2 respectively. A doping mask 42 is formed that covers the dielectric pillars 36B within the predetermined area 44 and exposes the dielectric pillars 36A outside the predetermined area 44 . Specifically, the plurality of dielectric pillars 36A and 36B are disposed between the plurality of word lines 14 and the plurality of active regions 46 , and the doping mask 42 covers the center of the active regions 46 The dielectric cylinder 36B. Afterwards, a first oblique doping process is performed to implant impurities (such as boron difluoride, BF ₂ ) into the silicon-containing layer 40 on the dielectric pillar 36A outside the predetermined region 44, as shown in FIG. 6(a) and Figure 6(b) shows. Furthermore, the first oblique doping process injects impurities into the silicon-containing layer 40 of a predetermined portion (ie, the left portion of the dielectric pillar 36A) to change the chemical properties of the silicon-containing layer 40 of the predetermined portion (for example, resist etching properties), the right part of the dielectric pillar 36A is not doped with impurities and retains its original chemical properties.

Referring to Fig. 7, Fig. 7(a) and Fig. 7(b), Fig. 7(a) and Fig. 7(b) are partial sectional views of Fig. 7 along section lines 1-1 and 2-2 respectively. After removing the doping mask 42 , a doping mask 48 is formed that exposes the dielectric pillars 36B within the predetermined region 44 . Next, a second oblique doping process is performed to implant impurities into the silicon-containing layer 40 on the dielectric pillar 36B in the predetermined region 44 . Preferably, the doping direction of the first oblique doping process is opposite to that of the second oblique doping process. Furthermore, the second oblique doping process injects impurities into the silicon-containing layer 40 in a predetermined portion (ie, the right portion of the dielectric pillar 36B) to change the chemical properties of the silicon-containing layer 40 in the predetermined portion. The left part of the electrical column 36B is not doped with impurities and retains its original chemical properties.

Referring to FIG. 8( a ) and FIG. 8( b ), they are partial cross-sectional views of FIG. 7 along section lines 1-1 and 2-2 respectively. After removing the doping mask 48, use an etchant (such as ammonia water) to carry out a wet etching process to partially remove the silicon-containing layer 40 on the dielectric pillar 36B (that is, remove the silicon-containing layer 40 on the left side wall of the dielectric pillar 36B). The impurity-doped silicon-containing layer 40) forms a second etch mask 50 that exposes the left sidewall of the dielectric pillar 36B. Similarly, the wet etching process also partially removes the silicon-containing layer 40 on the dielectric pillar 36A (that is, removes the silicon-containing layer 40 not doped with impurities on the right side wall of the dielectric pillar 36A), and exposes the The right side wall of the dielectric cylinder 36A is shown in FIG. 9( a ) and FIG. 9( b ), which are partial cross-sectional views of FIG. 6 along section lines 1 - 1 and 2 - 2 respectively.

Referring to FIG. 10( a ) and FIG. 10( b ), they are partial cross-sectional views of FIG. 7 along section lines 1-1 and 2-2 respectively. A wet etch process is performed using a buffered oxide etchant (BOE) to partially remove the dielectric pillars 36B not covered by the second etch mask 50 . The buffered oxide etchant can etch the dielectric pillar 36B through the sidewall of the dielectric pillar 36B not covered by the second etching mask 50 to enlarge the first opening 38 to form the second opening 52 . Next, use an anisotropic dry etching process to remove the second etching mask 50, and partially remove the silicon nitride layer 18 to expose the doped regions 13A and 13B in the semiconductor substrate 12, as shown in FIG. 11(a) and FIG. As shown in 11(b), it is a partial cross-sectional view of Fig. 7 along the section lines 1-1 and 2-2 respectively.

Referring to Fig. 12, 12(a) and Fig. 12(b), 12(a) and Fig. 12(b) are partial cross-sectional views of Fig. 12 along section lines 1-1 and 2-2 respectively. Perform a deposition process to form a conductive layer (such as a polysilicon layer), and then perform a planarization process (such as an etch-back process or a chemical mechanical polishing process) to partially remove the conductive layer to form a first conductive plug 54 in the predetermined region 44 In the second opening 52 and the second conductive plug 56 is in the second opening 52 outside the predetermined area 44 .

Furthermore, the first conductive plug 54 includes a first block 54A disposed in the active region 46 and a second block 54B disposed at a first side of the active region 46 . The second conductive plug 56 includes a third block 56A disposed in the active region 46 and a fourth block 56B disposed on a second side of the active region 46 . Preferably, the width of the first block 54A is about twice that of the second block 54B, the width of the third block 56A is about twice that of the fourth block 56B, and the active region 46 The first side and the second side are opposite sides of the active region 46 .

Referring to Figure 13, 13(a) and Figure 13(b), 13(a) and Figure 13(b) are partial cross-sectional views of Figure 13 along section lines 1-1 and 2-2 respectively. A dielectric layer 58 covering the first conductive plug 54 and the second conductive plug 56 is formed, and then a bit line contact plug 60 connected to the first conductive plug 54 is formed in the dielectric layer 58 . Next, deposit a conductive layer (such as a tungsten metal layer) on the dielectric layer 58, then form a silicon nitride mask 64 and perform a dry etching process to partially remove the conductive layer, and form a contact plug 60 connected to the bit line. The bit line 62 is above the dielectric layer 58 . Since the bit line contact plug 60 can be connected to the first block 54A or the second block 54B of the first conductive plug 54 to achieve the electrical connection between the bit line 62 and the doped region 13A, its size is defined And the lithography technology of the location has a large process margin (process window). Preferably, the bit line contact plug 60 is connected to the second block 54B of the first conductive plug 54 .

Referring to Fig. 14, 14(a) and Fig. 14(b), 14(a) and Fig. 14(b) are partial cross-sectional views of Fig. 14 along section lines 1-1 and 2-2 respectively. Silicon nitride spacers 66 are formed to electrically isolate the bitlines 62 . Next, a high density chemical vapor deposition process is performed to form a silicon oxide layer 68 that fills the gap between the bit lines 62 and covers the silicon nitride mask 64 . Afterwards, a planarization process is performed to partially remove the silicon oxide layer 68 on the silicon nitride mask 64 .

Referring to Fig. 15, 15(a) and Fig. 15(b), Fig. 15(a) and Fig. 15(b) are partial cross-sectional views of Fig. 15 along section lines 1-1 and 2-2 respectively. A photoresist layer 70 having a plurality of linear openings 72 is formed on the planarized surface, wherein the linear openings 72 expose a portion of the silicon oxide layer 68 . Secondly, using the photoresist layer 70 and the silicon nitride spacer 66 as an etching mask, a self-aligned dry etching process is performed to remove the silicon oxide layer 68 below the linear opening 72 to form several exposed second The contact hole 74 of the conductive plug 56 exposes the fourth block 56B of the second conductive plug 56 .

Referring to Fig. 16, 16(a) and Fig. 16(b), 16(a) and Fig. 16(b) are partial cross-sectional views of Fig. 16 along section lines 1-1 and 2-2 respectively. After removing the photoresist layer 70, silicon nitride deposition and dry etching processes are performed to increase the thickness of the silicon nitride spacer 66, and then a deposition process is performed to form a conductive layer (such as a polysilicon layer) that fills the contact hole 74. ). Next, a planarization process is performed to partially remove the conductive layer to form a capacitor plug 76 connecting the fourth block 56B of the second conductive plug 56 outside the predetermined area 44 . Afterwards, a capacitor 78 disposed on the dielectric layer 64 is formed, which is connected to the fourth block 56B of the second conductive plug 56 through the capacitor plug 76 , so as to form the memory structure 10 .

17( a ) to FIG. 19( b ) show the manufacturing method of the memory structure 10 according to the second embodiment of the present invention, which are partial cross-sectional views along the section lines 1-1 and 2-2 in FIG. 3 respectively. Firstly, the processes shown in FIG. 3(a), FIG. 3(b), FIG. 4(a) and FIG. 4 are performed, and then a lining oxide layer 82 is formed on the silicon-containing layer 40 by a deposition process. Next, a photoresist layer 84 is formed on the bottom of the first opening 38 by coating process and etching process, as shown in FIG. 17(a) and FIG. 17(b).

18 (a) and FIG. 18 (b), an etching process is performed to partially remove the lining oxide layer 82 not covered by the photoresist layer 84, that is, partially remove the lining oxide layer 82 on the top of the first opening 38. . Next, a cleaning process is performed to remove the photoresist layer 84 to form a doping mask 82' at the bottom of the first opening 38, as shown in FIG. 19(a) and FIG. 19(b). After that, the process of FIG. 5( a ), FIG. 5( b ) to FIG. 16 is performed to complete the memory structure 10 . The doping mask 82 ′ can prevent impurity (boron difluoride) from being injected into the semiconductor substrate 12 through the first opening 38 in the subsequent oblique doping process, thereby affecting the electrical characteristics of the electronic components.

Compared with the known memory structure 100, when entering the nanometer era (F is less than 100 nanometers), repeated exposure technology must be used and an advanced photolithography process must be used to define the size and position of its capacitor plug 110 (ie, the contact hole). The fabrication of the memory structure 10 does not require repeated exposure techniques, and does not require the use of advanced photolithography techniques (such as lithographic immersion techniques) to define the size and location of the contact holes 74 (ie, the capacitor plugs 76 ). Furthermore, both the bit lines 62 and the active regions 64 of the present invention are simple linear patterns designed horizontally, so repeated exposure techniques are not required. In addition, the present invention uses a photolithography mask with a simple linear pattern to define the linear opening 72 , and then uses a self-aligned dry etching technique to form the contact hole 74 , so advanced photolithography technology is not required.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and improvements based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various replacements and improvements that do not deviate from the present invention, and are covered by the claims.

Claims (18)

1. internal storage structure is characterized in that comprising:

Semiconductor substrate;

Active region is arranged among this semiconductor substrate;

A plurality of doped regions that are arranged in this semiconductor substrate;

Be electrically connected first conductive plunger of one of bit line and these a plurality of doped regions;

Be electrically connected second conductive plunger of one of capacitor and these a plurality of doped regions;

This first conductive plunger comprises second block that is arranged at first block in this active region and is arranged at the first side of this active region; And

This second conductive plunger comprises the 4th block that is arranged at the 3rd block in this active region and is arranged at the second side of this active region.

2. internal storage structure according to claim 1 is characterized in that this bit line connects second block of this first conductive plunger via bit line contact plug.

3. internal storage structure according to claim 1 is characterized in that this capacitor is connected in this second conductive plunger via the capacitor contact plunger.

4. internal storage structure according to claim 3 is characterized in that this capacitor contact plunger connects the 4th block of this second conductive plunger.

5. internal storage structure according to claim 1 is characterized in that this first conductive plunger is electrically connected bit line, and this second conductive plunger is electrically connected capacitor, and this capacitor is arranged at this bit line top.

6. internal storage structure according to claim 1, the width that it is characterized in that this first block are two times of this second block width.

7. internal storage structure according to claim 1, the width that it is characterized in that the 3rd block are two times of the 4th block width.

8. internal storage structure according to claim 1 is characterized in that the first side of this active region and the two opposite sides that the second side is this active region.

9. internal storage structure according to claim 1 is characterized in that also comprising two capacitors, is arranged at the same side of this active region.

10. the preparation method of an internal storage structure is characterized in that comprising:

Form first etching mask on the substrate that comprises semiconductor substrate, active region, doped region and dielectric structure;

Local this dielectric structure of removing is opened between these a plurality of dielectric cylinders to form a plurality of dielectric cylinders and a plurality of first;

Remove this first etching mask, the depositing silicon layer covers the surface of these a plurality of dielectric cylinders;

The part is removed the silicon-containing layer on this dielectric cylinder and is formed second etching mask, and it covers the local surfaces of these a plurality of dielectric cylinders;

Local this dielectric cylinder of removing forms second opening to enlarge this first opening;

Form in second opening of first conductive plunger in this presumptive area and second opening of second conductive plunger beyond this presumptive area in, this first conductive plunger comprises second block that is arranged at first block in this active region and is arranged at this active region first side, and this second conductive plunger comprises the 4th block that is arranged at the 3rd block in this active region and is arranged at this active region second side;

Form the multiple bit lines contact plunger, it connects first conductive plunger in this presumptive area; And

Form a plurality of capacitor contact plungers, it connects second conductive plunger beyond this presumptive area, and forms this internal storage structure.

11. the preparation method of internal storage structure according to claim 10 is characterized in that the step that forms second etching mask comprises:

Change the chemical property of the silicon-containing layer of predetermined portions.

12. the preparation method of internal storage structure according to claim 11, the chemical property that it is characterized in that changing the silicon-containing layer of predetermined portions is to carry out doping process impurity is injected the silicon-containing layer of this predetermined portions.

13. the preparation method of internal storage structure according to claim 12 is characterized in that this doping process is oblique doping process, this silicon-containing layer comprises polysilicon, and this impurity comprises boron difluoride.

14. the preparation method of internal storage structure according to claim 12, it is characterized in that removing this predetermined portions silicon-containing layer in addition is to utilize ammoniacal liquor to carry out wet etching process.

15. the preparation method of internal storage structure according to claim 11, the chemical property that it is characterized in that changing the silicon-containing layer of predetermined portions comprises:

Form first doping mask, it covers the dielectric cylinder of presumptive area; And

Carry out the first oblique doping process impurity is injected this presumptive area silicon-containing layer in addition.

16. the preparation method of internal storage structure according to claim 15 is characterized in that also comprising:

Form second doping mask, it exposes the dielectric cylinder of this presumptive area; And

Carry out the second oblique doping process impurity is injected the silicon-containing layer in this presumptive area;

Wherein the doping direction of this first oblique doping process is different from the doping direction of this second oblique doping process.

17. the preparation method of internal storage structure according to claim 16 is characterized in that also comprising formation the 3rd doping mask, it covers the bottom of this first opening.

18. the preparation method of internal storage structure according to claim 16 is characterized in that the doping direction of the doping of this first oblique doping process in the direction opposite this second oblique doping process.

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