CN100539125C - Integrated package structure of cantilever stack type system and its packaging method - Google Patents
Integrated package structure of cantilever stack type system and its packaging method Download PDFInfo
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- CN100539125C CN100539125C CN200710079206.8A CN200710079206A CN100539125C CN 100539125 C CN100539125 C CN 100539125C CN 200710079206 A CN200710079206 A CN 200710079206A CN 100539125 C CN100539125 C CN 100539125C
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000003466 welding Methods 0.000 claims abstract 6
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 239000000565 sealant Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 description 27
- 238000012856 packing Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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Abstract
The invention provides a cantilever stack type system integrated packaging structure and a packaging method thereof, wherein the method comprises the following steps: providing a substrate having a plurality of connection pads; providing a first chip, wherein the first chip is provided with a first active surface, a plurality of first welding pads are formed on the first active surface, and the first chip is arranged on the upper surface of the substrate in a mode that the first active surface faces upwards; providing a second chip, wherein the second chip is provided with a second active surface and a plurality of second welding pads are formed on the second active surface; and alternately arranging the second chips on the first chip in a mode that the second active surfaces face upwards, so that the first sides of the second chips protrude out of the first chip, and electrically connecting the second welding pads to the substrate and the first welding pads. The packaging structure obtained by the method overcomes the limitation of the prior art by utilizing the cantilever structure of the upper chip, effectively improves the packaging efficiency and reduces the packaging cost.
Description
Technical field
The present invention relates to the encapsulation of system combination type (system in package, SIP) structure and method for packing.
Background technology
The system combination type is encapsulated as and one saves the space, reduce power consumption, suppress the encapsulation technology of electromagnetic interference, in order to the function with subsystem be incorporated into same packaging body in.System combination type encapsulation technology has two kinds of practices usually when actual fabrication, a kind of is side-by-side (side by side), and multiple chips (die) is come encapsulation together; Another kind is a stacking-type, then is with the multiple chips storehouse, is combined into a complete subsystem.Below introduce side-by-side common in the integrated encapsulation of existing system and stacking-type structure.
Fig. 1 is the vertical view of existing side-by-side system combination type packaging structure.
With reference to figure 1, block form system combination type packaging structure 100 is because chip 110,120 is arranged side by side, so area further can't be dwindled, simultaneously, this framework also produces some restrictions to routing, for example: can not have under the staggered prerequisite at bare wire, only could mutual routing in the adjacent both sides of chip 110,120.In addition, if pin can not mean allocation during routing, will cause the encapsulation of the more pin of needs, and then cost and space will be caused burden.
Fig. 2 is the vertical view of first type structure of existing stacking-type system combination type encapsulation.Fig. 3 is an end view of second type structure of existing stacking-type system combination type encapsulation.
With reference to figure 2 and Fig. 3, compared to block form system combination type packaging structure 100, the area of stacking-type system combination type packaging structure 200,300 is less usually, be fit to be applied in compact consumption electronic product, again because four limits of chip 210,220 (or 310,320) can both routing, so have preferable routing elasticity.Compare the first type framework 200 of stacking-type system combination type encapsulation and the difference of the second type framework 300, the following square chip 220 of first type structure 200 has the restriction of size usually, be must be on the size greater than last square chip 210 to one specific degrees to meet the routing standard, therefore, when if die size is similar up and down, the size of following square chip 220 can be forced to strengthen, also thereby cause the increase of cost.Be useful in the situation that chip 310,320 sizes are similar and size square chip 320 down can't increase up and down as for 300 of second type structures, at this moment, an empty chip (dummy die) 330 can pressed from both sides between the chip 310,320 up and down, in order to will going up square chip 310 bed hedgehopping routings, but so may cause some restrictions to encapsulation specification (for example height).
In sum, be that block form or stacking-type system combination type packaging structure all must also all can impact cost or even encapsulation specification (for example height or area) via the thickness that strengthens encapsulation or area to increase the elasticity of routing.For addressing the above problem, therefore the present invention is proposed.
Summary of the invention
At the deficiencies in the prior art, the objective of the invention is to: a kind of cantilever stack formula system combination type packaging structure and method for packing thereof are provided, reduce packaging height and area, reduce packaging cost.
For reaching above-mentioned purpose, cantilever stack formula system combination type packaging structure of the present invention comprises: a substrate, and it is to have a upper surface and comprise a plurality of connection gaskets that are formed on described upper surface; One first chip, it is to have one first active surface and comprise a plurality of first weld pads that are formed on described first active surface, in order to be electrically connected to described connection gasket, described first chip is the described upper surface that is located at described substrate in the supine mode of described first active; And, one second chip, it is to have one second active surface and comprise a plurality of described second active surface second weld pads on every side that are formed on, described second chip is to be crisscross arranged on described first chip in the supine mode of described second active, and one first pleurapophysis being arranged for described first chip, described second weld pad is electrically connected to described first weld pad and described connection gasket respectively.
In one embodiment of this invention, described first chip and described second chip form a cross framework.
The present invention also discloses a kind of method for packing of cantilever stack formula system combination type packaging structure, comprises following steps: a substrate with a plurality of connection gaskets is provided; One first chip is provided, and described first chip has one first active surface and described first active surface is to be formed with a plurality of first weld pads, and in the supine mode of described first active upper surface of described first chip at described substrate is set; One second chip is provided, and described second chip is to have one second active surface and described second active surface is to be formed with a plurality of second weld pads; And, in the supine mode of described second active, be crisscross arranged described second chip on described first chip, make described second chip one first pleurapophysis be arranged, and be electrically connected described second weld pad to described substrate and described first weld pad for described first chip.
Compared with prior art, the beneficial effect that has of the present invention is:
Often cause the encapsulation of the more pin of needs compared to side-by-side system combination type packaging structure, the present invention utilizes cantilever design (promptly going up two arm overhangs about square chip), routing effectively is distributed in all directions,, finishes the encapsulation of least cost so can use lucky pin count.In addition, in side-by-side system combination type packaging structure, routing mutually only, and the present invention is at the chip all routings mutually of part (just going up the both sides up and down of square chip mid portion) that overlap in the adjacent both sides of chip, the elastic space that doubles for the connection of chip chamber.
On the other hand, though existing stacking-type system combination type packaging structure is saved the space and is had good routing elasticity, yet, first type structure only is useful in the situation of below area of chip greater than last square chip, and when the upper and lower area of chip is similar, strengthens the below area of chip if not force, just as second type structure, press from both sides an empty chip, with the bed hedgehopping height, and the two all can change encapsulation specification (area or height) and increase cost.Relatively, cantilever stack formula system combination type packaging structure provided by the present invention, need not increase packaging height, need not force and strengthen the below area of chip, utilize simple cantilever design just can overcome the restriction of prior art, and effectively promote packaging efficiency and reduce packaging cost, reach the encapsulation specification of the tightst (compact).
Description of drawings
Fig. 1 is the vertical view of existing side-by-side system combination type packaging structure.
Fig. 2 is the vertical view of first type structure of existing stacking-type system combination type encapsulation.
Fig. 3 is an end view of second type structure of existing stacking-type system combination type encapsulation.
Fig. 4 is according to one embodiment of the invention, a kind of vertical view of cantilever stack formula system combination type packaging structure.
Fig. 5 is the flow chart of the method for packing of cantilever stack formula system combination type packaging structure of the present invention.
Description of reference numerals: 100-block form system combination type packaging structure; 110,120,210,220,310,320,410,420-chip; First type structure of 200-stacking-type system combination type encapsulation; Second type structure of 300-stacking-type system combination type encapsulation; The empty chip of 330-; 400-cantilever stack formula system combination type packaging structure; 411,421-weld pad; The 450-substrate; The 451-connection gasket.
Embodiment
Fig. 4 is according to one embodiment of the invention, a kind of vertical view of cantilever stack formula system combination type packaging structure.
With reference to figure 4, cantilever stack formula system combination type packaging structure 400 comprises 450, two chips of a substrate (or lead frame) 410,420 and an adhesive body (not shown).Substrate 450 is to have a upper surface and comprise a plurality of connection gaskets (or pin) 451 that are formed on described upper surface, following square chip 410 is to be located at the upper surface (not shown) of substrate 450 in first active surface (not shown) mode up, and comprises a plurality of described first active surface first weld pads 411 of both sides up and down that are formed on.Last square chip 420 is to have one second active surface (not shown) and comprise a plurality of described second active surface second weld pads 421 on every side that are formed on, last square chip 420 is the tops that are located at chip 410 in the supine mode of second active, and it is staggered (for example with following square chip 410, both form a cross framework), described second weld pad 421 relies on lead or bonding wire to be connected to described connection gasket 451 (or pin of encapsulation) and described first weld pad 411.In this cross framework, the left and right sides cantilever of last square chip 420 all protrudes in down square chip 410, is mainly used to routing effectively is distributed in the encapsulation pin of all directions, has avoided too much sky (no connection, NC) phenomenon of pin generation.Overlap partly (just going up the zone outside square chip 420 left and right sides cantilevers) as for last square chip 420 and following square chip 410, then can be for interconnecting between two chips 410,420.Certainly, also can be connected between a plurality of first weld pads 411 and a plurality of connection gasket 451 with a plurality of bonding wires according to circuit requirements; Or with a plurality of second weld pads 421 and a plurality of connection gaskets 451 regional outside last square chip 420 left and right sides cantilevers of a plurality of bonding wires connections.Adhesive body is then in order to sealing and fixing square chip 420, the following square chip 410 and described bonding wire gone up.
Please note, more than be an embodiment, the present invention does not limit two chips 410,420 must form a cross framework, there is any side (or a cantilever) to protrude in down square chip 410 as long as go up square chip 420, just can effectively routing be distributed in all directions, certainly, the part that last square chip 420 protrudes in down square chip 410 many more (for example two cantilevers are better than a cantilever), effect is obvious more.Therefore, there is any side (or a cantilever) to protrude in down square chip 410, all is applicable to the notion of cantilever stack formula system combination type packaging structure of the present invention as long as go up square chip 420.
Fig. 5 is the flow chart of the method for packing of cantilever stack formula system combination type packaging structure of the present invention.Below with reference to the 4th and Fig. 5, the method for packing of cantilever stack formula system combination type packaging structure of the present invention is described.
Step S510: a substrate 450 is provided, and the upper surface of described substrate 450 comprises a plurality of connection gaskets 451.
Step S520: square chip 410 once is provided, described square chip 410 down has one first active surface and described first active surface is to be formed with a plurality of first weld pads 411, and, the upper surface of square chip 410 at substrate 450 is set down in the supine mode of first active.Because the method that is provided with is had now by present technique field person, does not repeat them here.
Step S530: square chip 420 on is provided, and the described square chip 420 of going up is to have one second active surface and described second active surface is to be formed with a plurality of second weld pads 421.
Step S540: in the supine mode of second active, be crisscross arranged and go up square chip 420 on following square chip 410, make square chip 420 have at least a side (or a cantilever) to protrude in described square chip 410 down, and connect the connection gasket 451 and described first weld pad 411 of described second weld pad 421 respectively to substrate 450 with bonding wire.With Fig. 4 is example, in this step, be to go up push-down stack on square chip 420 and the following square chip 410, to form a cross framework, and with wire bonder (the wire bond capillary) left and right sides cantilever routing of chip 420 up, routing effectively is distributed in all directions, the encapsulation of the suitableeest to reach (not can too much) pin.Wherein, the method for routing is had now by present technique field person, also will not give unnecessary details at this.
Step S550: pour into adhesive body (mold compound), coat at least and go up square chip 420, following square chip 410 and described bonding wire,, promptly finish whole canned program with sealing and stuck-module.Wherein, the method for encapsulating also belongs to prior art, also will not give unnecessary details at this.
Often cause the encapsulation of the more pin of needs compared to side-by-side system combination type packaging structure 100, the present invention utilizes cantilever design (promptly going up square chip about 420 two arm overhangs), routing effectively is distributed in all directions,, finishes the encapsulation of least cost so can use lucky pin count.In addition, in side-by-side system combination type packaging structure 100, only at the mutual routing of the adjacent both sides of chip 110,120 ability, and the present invention is at chip 410, the 420 all routings mutually of part (just going up the both sides up and down of square chip 420 mid portions) that overlap, the elastic space that doubles for the connection of 410,420 of chips.
On the other hand, though existing stacking-type system combination type packaging structure is saved the space and is had good routing elasticity, yet, 200 of first type structures are useful in the situation of below area of chip greater than last square chip, and when the upper and lower area of chip is similar, strengthen the below area of chip if not force, just construct 300 as second type, press from both sides an empty chip, with the bed hedgehopping height, and the two all can change encapsulation specification (area or height) and increase cost.Relatively, cantilever stack formula system combination type packaging structure provided by the present invention, need not increase packaging height, need not force and strengthen the below area of chip, utilize simple cantilever design just can overcome the restriction of prior art, and effectively promote packaging efficiency and reduce packaging cost, reach the encapsulation specification of the tightst (compact).
More than explanation is just illustrative for the purpose of the present invention, and it is nonrestrictive, those of ordinary skills understand, under the situation of the spirit and scope that do not break away from claim and limited, can make many modifications, variation or equivalence, but but all will fall within the claim restricted portion of the present invention.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710079206.8A CN100539125C (en) | 2007-02-09 | 2007-02-09 | Integrated package structure of cantilever stack type system and its packaging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710079206.8A CN100539125C (en) | 2007-02-09 | 2007-02-09 | Integrated package structure of cantilever stack type system and its packaging method |
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| CN101009273A CN101009273A (en) | 2007-08-01 |
| CN100539125C true CN100539125C (en) | 2009-09-09 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229960A (en) * | 1990-12-05 | 1993-07-20 | Matra Marconi Space France | Solid state memory modules and memory devices including such modules |
| US20020011654A1 (en) * | 2000-07-25 | 2002-01-31 | Naoto Kimura | Semiconductor device |
| US6930378B1 (en) * | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
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2007
- 2007-02-09 CN CN200710079206.8A patent/CN100539125C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229960A (en) * | 1990-12-05 | 1993-07-20 | Matra Marconi Space France | Solid state memory modules and memory devices including such modules |
| US20020011654A1 (en) * | 2000-07-25 | 2002-01-31 | Naoto Kimura | Semiconductor device |
| US6930378B1 (en) * | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
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| Publication number | Publication date |
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| CN101009273A (en) | 2007-08-01 |
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