CN100536087C - Method for manufacturing compressive nitride layer and method for forming transistor - Google Patents
Method for manufacturing compressive nitride layer and method for forming transistor Download PDFInfo
- Publication number
- CN100536087C CN100536087C CNB2006100772182A CN200610077218A CN100536087C CN 100536087 C CN100536087 C CN 100536087C CN B2006100772182 A CNB2006100772182 A CN B2006100772182A CN 200610077218 A CN200610077218 A CN 200610077218A CN 100536087 C CN100536087 C CN 100536087C
- Authority
- CN
- China
- Prior art keywords
- forming
- dielectric layer
- substrate
- layer
- semiconductor transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method for manufacturing a compressive nitride layer includes performing a chemical vapor deposition process to form a nitride layer on a substrate, wherein a specific gas is introduced during the chemical vapor deposition process, and the specific gas is selected from one of argon, nitrogen, krypton and xenon or a combination thereof. Due to the addition of the specific gas, the compressive stress can be reduced, and further the PMOS drive current gain can be increased.
Description
Technical field
The present invention relates to a kind of manufacture method of metal oxide semiconductor transistor, and particularly relate to the manufacture method of a kind of compressive nitrifier layer (compressive nitride film) and the method for formation metal oxide semiconductor transistor (MOS).
Background technology
Along with semiconductor technology enters the deep-sub-micrometer epoch, the time delay effect (time-delay performance) of transistor unit because lifting NMOS and PMOS drive current will be greatly improved, so the technology below the 65nm is increasingly important for the demand of drive current (drive current) lifting of NMOS and PMOS.For instance, have traditionally at development ILD low-k (low k) material and promote the research of drive current.And in recent years, the stress in thin film (film stress) of silicon nitride (SiN) pressure texture (stressor) of fleet plough groove isolation structure (STI) oxide layer, polysilicon top cover (Poly-Cap) and contact hole silicon nitride suspension layer (SiN contact etching stopr layer is abbreviated as SiN CESL) begun one's study both at home and abroad to the influence of the drive current of transistor unit.
The result is, the silicon nitride pressure texture and the contact hole silicon nitride suspension layer stress in thin film of sti oxide, polysilicon top cover is deposited as compression stress (compressive stress).And rete compression more, it is many more that the PMOS drive current increases ground.
But at low temperature below 400 ℃, plated film (As-deposit) technology of whole world the best also can only reach-1.6GPa at present in the mode of PECVD.Therefore, how obtaining more further, the rete of high compression stress has become one of problem of all circles' research.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of compressive nitrifier layer is being provided, and can obtain the rete of high compression stress.
A further object of the present invention provides a kind of method that forms metal oxide semiconductor transistor, to promote the drive current gain of PMOS.
Another purpose of the present invention provides a kind of method that forms metal oxide semiconductor transistor, can improve the structural stress of PMOS and NMOS simultaneously.
Another object of the present invention provides a kind of method that forms metal oxide semiconductor transistor, to increase current gain, keeps existing component structure simultaneously.
The present invention proposes a kind of manufacture method of compressive nitrifier layer, comprises carrying out chemical vapor deposition method one, to form one deck nitride layer in substrate.This method is characterised in that: need to feed specific gas during above-mentioned chemical vapor deposition method, and this kind specific gas is to be selected to comprise argon gas (Ar), nitrogen (N
2), wherein a kind of gas or its combination of krypton gas (Kr) and xenon (Xe).
Manufacture method according to the described compressive nitrifier layer of one embodiment of the present of invention, when specific gas is the composition gas of argon gas and nitrogen, argon flow amount is between 100sccm～5000sccm, and nitrogen flow is between 1000sccm～30000sccm.
According to the manufacture method of the described compressive nitrifier layer of one embodiment of the present of invention, wherein the low frequency power that above-mentioned chemical vapor deposition method adopted (LF Power) is between 50W～3000W.
According to the manufacture method of the described compressive nitrifier layer of one embodiment of the present of invention, can be at chemical vapor deposition method leading portion, stage casing or back segment the opportunity that wherein feeds aforementioned specific gas.
According to the manufacture method of the described compressive nitrifier layer of one embodiment of the present of invention, aforementioned nitride layer comprises the silicon nitride layer or the oxygen containing silicon nitride layer of silicon nitride layer, carbon containing.
The present invention reintroduces a kind of method that forms metal oxide semiconductor transistor, comprises a substrate is provided earlier, has formed at least one grid structure on it.Then, in the grid structure substrate on two sides, form source electrode and drain electrode, form the layer of metal silicide layer in the surface of grid structure end face and source electrode and drain electrode again.Afterwards, deposition one deck compressive dielectric layer in substrate with overlies gate structure, source electrode and drain electrode, feeds specific gas during the method that wherein deposits compressive dielectric layer is included in chemical vapor deposition method.Wherein, aforementioned specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.
The present invention proposes a kind of method that forms metal oxide semiconductor transistor again, and comprising provides a substrate earlier, and this substrate has PMOS district and nmos area, respectively forms a grid structure again in the substrate of PMOS district and nmos area.Then, in each grid structure substrate on two sides, form source electrode and drain electrode, again respectively at deposition one deck compressive dielectric layer (compressive dielectric film) and one deck tension force dielectric layer (tensile dielectric film) in the substrate of PMOS district and nmos area, to cover each grid structure, source electrode and drain electrode.Wherein, feed specific gas during the method that deposits aforementioned compressive dielectric layer is included in one chemical vapor deposition method, and this specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.
According to the method for the described formation metal oxide semiconductor transistor of an alternative embodiment of the invention, wherein form also to be included in behind each grid structure and form one deck first resilient coating (bufferlayer) in the substrate, to cover each grid structure.
Method according to the described formation metal oxide semiconductor transistor of an alternative embodiment of the invention, wherein form source electrode with the drain electrode back and before forming first resilient coating, more can form the layer of metal silicide layer on the surface of each grid structure end face and source electrode and drain electrode.
According to the method for the described formation metal oxide semiconductor transistor of an alternative embodiment of the invention, deposition tension dielectric layer just after the deposition compressive dielectric layer wherein.And, can after the deposition compressive dielectric layer and before the deposition tension dielectric layer, in substrate, form one deck second resilient coating, to cover above-mentioned compressive dielectric layer.
According to the method for the described formation metal oxide semiconductor transistor of an alternative embodiment of the invention, wherein after the deposition tension dielectric layer, just deposit compressive dielectric layer.And, can in substrate, form one deck second resilient coating, to cover the mentioned strain dielectric layer after the deposition tension dielectric layer and before the deposition compressive dielectric layer.
The present invention proposes a kind of method that forms metal oxide semiconductor transistor in addition, comprises a substrate is provided earlier, has formed at least one grid structure on it.Then, in the grid structure substrate on two sides, form source electrode and drain electrode, in substrate, deposit one deck compressive dielectric layer again, with overlies gate structure, source electrode and drain electrode, feed specific gas during the method that wherein deposits compressive dielectric layer is included in one chemical vapor deposition method, and this kind specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.Then, carry out one annealing process (annealing process).Again compressive dielectric layer is removed afterwards.Then, form the layer of metal silicide layer in the surface of each grid structure end face and source electrode and drain electrode.
According to the method for the described formation metal oxide semiconductor transistor of the various embodiments described above of the present invention, the low frequency power that aforementioned chemical vapor deposition method adopted is included between 50W～3000W.
Method according to the described formation metal oxide semiconductor transistor of the various embodiments described above of the present invention, when aforementioned specific gas is the composition gas of argon gas and nitrogen, argon flow amount can be between 100sccm～5000sccm, and nitrogen flow can be between 1000sccm～30000sccm.
According to the method for the described formation metal oxide semiconductor transistor of the various embodiments described above of the present invention, the aforementioned compressive dielectric layer that deposits comprises the silicon nitride layer or the oxygen containing silicon nitride layer of silicon nitride layer, carbon containing.
According to the method for the described formation metal oxide semiconductor transistor of the various embodiments described above of the present invention, aforementioned substrates can be at (100) crystal face to be had＜100〉crystal orientation substrate.
The present invention is because add heavy specific gas in chemical vapor deposition method, the bombardment when increasing film deposition (bombard), and with the high compression stress nitride layer of deposition one deck densification, but the therefore drive current of lift elements gain.And the present invention can reach required current gain with thin compressive nitrifier layer, so increase the effect of contact hole etching process window (process window) in addition.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 is that the resulting compressibility silicon nitride layer of the present invention and traditional silicon nitride layer and existing silicon nitride layer after improvement are in the comparative graph of Ion to Ioff_S.
Fig. 2 then is that three kinds of silicon nitride layers among Fig. 1 are in the comparative graph of Ion current gain and thickness.
Fig. 3 A to Fig. 3 D is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the second embodiment of the present invention.
Fig. 4 A to Fig. 4 C is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the third embodiment of the present invention.
Fig. 5 A to Fig. 5 E is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the fourth embodiment of the present invention.
The simple symbol explanation
300,400,500: substrate
302,402: isolation structure
304,404,502: grid structure
306,406,504,504a: source electrode and drain electrode
308,506: source electrode and drain electrode extension area
310,512: metal silicide layer
312,410a, 508: compressive dielectric layer
408,412: resilient coating
410b: tension force dielectric layer
510: source electrode and drain anneal technology
Embodiment
Notion of the present invention is when utilizing chemical vapor deposition method to form compressive dielectric layer, the bombardment when the heavy gas of adding increases deposition.Below be used as example explanation of the present invention, but the present invention is not limited to the described content of following embodiment for a plurality of embodiment.
First embodiment
Manufacture method according to a kind of compressive nitrifier layer of the first embodiment of the present invention can comprise and carry out chemical vapor deposition method one, and to form one deck nitride layer in substrate, above-mentioned chemical vapor deposition method for example is PECVD.And, during chemical vapor deposition method, need to feed specific gas, and this kind specific gas is to be selected to comprise argon gas (Ar), nitrogen (N
2), wherein a kind of gas or its combination of krypton gas (Kr) and xenon (Xe).For instance, when specific gas was the composition gas of argon gas and nitrogen, argon flow amount was between 100sccm～5000sccm, and nitrogen flow is between 1000sccm～30000sccm.In addition, between the preferably about 50W～3000W of the low frequency power that chemical vapor deposition method adopted (LF Power).
Following table one is with the method for first embodiment (experimental example 1～2) and in contrast to tradition (reference examples) does not feed specific gas of the present invention in addition in chemical vapor deposition method technological parameter form.
Table one
| SiH 4 (sccm) | NH 3 (sccm) | Ar (sccm) | N 2 (sccm) | HF (W) | LF(W) (Bias) | Stress (GPa) | |
| Reference examples | 240 | 3200 | 0 | 4000 | 100 | 0 | -0.07 |
| Experimental example 1 | 60 | 130 | 3000 | 1000 | 100 | 75 | -2.4 |
| Experimental example 2 | 60 | 40 | 4000 | 1000 | 100 | 200 | -2.5 |
From table one as can be known, traditional method (reference examples) can only reach-stress value of 0.07GPa; Otherwise method of the present invention (experimental example 2) can reach-stress value of 2.5GPa.In addition, can be at chemical vapor deposition method leading portion, stage casing or back segment the opportunity that feeds aforementioned specific gas.And resulting nitride layer can also be carbon containing (C) or the silicon nitride layer that contains oxygen (O) except silicon nitride layer.
And Fig. 1 resulting compressibility silicon nitride layer that is the present invention (compression stress for-2.4GPa) with traditional silicon nitride layer (compression stress for-0.06GPa) and existing after improvement silicon nitride layer (compression stress for-1.6GPa) in the comparative graph of Ion to Ioff_S, be about 800 dusts behind the film wherein, and substrate be have at (100) crystal face＜100〉crystal orientation.As can be seen from Figure 1, in identical Ioff_S value, existing silicon nitride layer after improvement (1.6GPa) (0.06GPa) can obtain higher Ion value than traditional silicon nitride layer; And compressibility silicon nitride layer of the present invention (Ion value 2.4GPa) is higher than existing silicon nitride layer (Ion value 1.6GPa) after improvement.Therefore, the present invention can increase PMOS drive current gain (drivecurrent gain) really.
Fig. 2 then is that three kinds of silicon nitride layers among Fig. 1 are in the comparative graph of Ion current gain and thickness.As can be seen from Figure 2, under the condition of identical Ion current gain (20%), (thickness 1.6GPa) need reach 850 dusts to existing silicon nitride layer after improvement.But, if adopt compressibility silicon nitride layer of the present invention (2.4GPa), then thicknesses of layers can be reduced to the 600 Izod right sides, can significantly promote contact hole etching process window (contact etching process window) thus, and when the thickness of silicon nitride layer is added to 1000 dusts, the Ion current gain of PMOS is brought up to greater than 40%.
And method proposed by the invention can also be applied in the chip problem on deformation (warping issue) that correction is caused after because of the deposit multilayer film.
Second embodiment
Fig. 3 A to Fig. 3 D is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the second embodiment of the present invention.
Please refer to Fig. 3 A, a substrate 300 is provided earlier, it can be at (100) crystal face has＜100〉crystal orientation substrate, and suppose that it can be divided into PMOS district and nmos area by a plurality of isolation structures 302.And in substrate 300, formed grid structure 304.The clearance wall that grid structure 304 comprises gate dielectric layer basically, is positioned at the grid on the gate dielectric layer and is formed at gate lateral wall, in addition can also comprise other member, but because this is to belong to the technical staff in the technical field of the invention can rely on existing technology to be known by inference, so do not give unnecessary details at this.
Then, please refer to Fig. 3 B, in grid structure 304 substrate on two sides 300, form source electrode and drain electrode 306, its method for example is an ion implantation technology, and when semiconductor technology enters the deep-sub-micrometer epoch (below the 65nm), can utilize directly growth source electrode and drain electrode 306 in substrate 300 of mode as selective epitaxial depositing operation (selective epitaxial deposition).Moreover, can form source electrode and drain before 306 earlier at 304 times formation of part grid structure source electrode and drain electrode extension area 308, to improve short-channel effect.
Can select the step of advanced row Fig. 3 C afterwards or leap to Fig. 3 D.Please refer to Fig. 3 C, can form layer of metal silicide layer 310 earlier on the surface of grid structure 304 end faces and source electrode and drain electrode 306.
Then, please refer to Fig. 3 D, deposition one deck compressive dielectric layer 312 in substrate 300 is to cover metal silicide layer 310; And if then carry out the step of Fig. 3 D certainly after the step of Fig. 3 B, what compressive dielectric layer 312 was covered is exactly grid structure 304, source electrode and drain electrode 306.The method of wherein above-mentioned deposition compressive dielectric layer 312 is during one chemical vapor deposition method, feed specific gas, and aforementioned specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.And the low frequency power that aforementioned chemical vapor deposition method adopted (LF Power) for example is between 50W～3000W.In addition, when aforementioned specific gas is the composition gas of argon gas and nitrogen, for instance: argon flow amount can be between 100sccm～5000sccm, and nitrogen flow can be between 1000sccm～30000sccm.And silicon nitride layer that above-mentioned compressive dielectric layer 312 for example is silicon nitride layer, carbon containing or oxygen containing silicon nitride layer.
Compressive dielectric layer 312 among above-mentioned second embodiment is the contact hole etching suspension layers (CESL) as whole M OS, so that reach lower stress.
The 3rd embodiment
Fig. 4 A to Fig. 4 D is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the third embodiment of the present invention.
Please refer to Fig. 4 A, a substrate 400 is provided earlier, it can be at (100) crystal face has＜100〉crystal orientation substrate, and suppose that it can be divided into the first district 400a and the second district 400b by a plurality of isolation structures 402; For instance, when the first district 400a was the PMOS district, then the second district 400b was a nmos area.Then, in the substrate 400 of the first district 400a and the second district 400b, respectively form a grid structure 404.The right time forms source electrode and drain electrode 406 in each grid structure 404 substrate on two sides 400, and can be with reference to the explanation (asking for an interview Fig. 3 B) of second embodiment with the mode of drain electrode 406 about forming source electrode.Afterwards, can be chosen in and form one deck first resilient coating (buffer layer) 408 in the substrate 400, to cover each grid structure 404; Or directly carry out following step.In addition, forming source electrode, can form layer of metal silicide layer (not illustrating) in addition on the surface of each grid structure 404 end face and source electrode and drain electrode 406 with drain electrode 406 backs and before forming above-mentioned first resilient coating 408.
Then, please continue A with reference to Fig. 4, deposition one deck compressive dielectric layer (compressivedielectric film) 410a in substrate 400, feed specific gas during the method that wherein deposits aforementioned compressive dielectric layer 410a is included in one chemical vapor deposition method, and this specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.And the low frequency power that aforementioned chemical vapor deposition method adopted for example is between 50W～3000W.In addition, when aforementioned specific gas was the composition gas of argon gas and nitrogen, argon flow amount for example was can be between 100sccm～5000sccm, and nitrogen flow for example is between 1000sccm～30000sccm.And above-mentioned compressive dielectric layer 410a can be the silicon nitride layer or the oxygen containing silicon nitride layer of silicon nitride layer, carbon containing.
Then, please refer to Fig. 4 B, the compressive dielectric layer 410a on second district (that is nmos area) 400b is removed, in substrate 400, form one deck second resilient coating 412 again, to cover above-mentioned compressive dielectric layer 410a.
Afterwards, please refer to Fig. 4 C, deposition one deck tension force dielectric layer (tensile dielectric film) 410b in the substrate 400 of second district (that is nmos area) 400b is to cover each floor structure of this district 400b.Therefore, the 3rd embodiment can improve the structural stress of PMOS district and nmos area simultaneously.
In addition, the first district 400a in Fig. 4 A to Fig. 4 C is meant nmos area, and on behalf of present embodiment, the second district 400b then just to deposit compressive dielectric layer after the first deposition tension dielectric layer when being meant the PMOS district.And, can in substrate 400, form one deck second resilient coating 412, to cover the mentioned strain dielectric layer after the deposition tension dielectric layer and before the deposition compressive dielectric layer.
The 4th embodiment
Fig. 5 A to Fig. 5 E is a kind of technology generalized section that forms metal oxide semiconductor transistor according to the fourth embodiment of the present invention.
Please refer to Fig. 5 A, a substrate 500 is provided earlier, it can be at (100) crystal face has＜100〉crystal orientation substrate, and in substrate 500, formed a grid structure 502.Then, in grid structure 502 substrate on two sides 500, form source electrode and drain electrode 504.Moreover, can form source electrode and drain before 504 earlier at 502 times formation of part grid structure source electrode and drain electrode extension area 506, to improve short-channel effect.
Then, please refer to Fig. 5 B, deposition one deck compressive dielectric layer 508 in substrate 500, with overlies gate structure 502, source electrode and drain electrode 504, feed specific gas during the method that wherein deposits compressive dielectric layer 508 is included in one chemical vapor deposition method, and this kind specific gas is to be selected from wherein a kind of gas or its combination that comprises argon gas, nitrogen, krypton gas and xenon.For instance, when aforementioned specific gas was the composition gas of argon gas and nitrogen, argon flow amount can be between 100sccm～5000sccm, and nitrogen flow can be between 1000sccm～30000sccm.And the low frequency power that aforementioned chemical vapor deposition method adopted for example is between 50W～3000W.Moreover, silicon nitride layer that the aforementioned compressive dielectric layer that deposits 508 can be silicon nitride layer, carbon containing or oxygen containing silicon nitride layer
Then, please refer to Fig. 5 D, carry out one annealing process (annealing process) 510, such as source electrode and drain anneal technology (sourse/drain annealing process).At this moment, compressive dielectric layer 508 can become the pressure texture (poly stressor) of polysilicon, so that the polysilicon layer in the substrate 500 is remembered its stress.
Afterwards, please refer to Fig. 5 E, compressive dielectric layer (ask for an interview Fig. 5 D 508) is removed, again in the surface of grid structure 502 end faces and source electrode and drain electrode 504a formation layer of metal silicide layer 512.Therefore, the method for the 4th embodiment not only can increase current gain, also can keep existing component structure simultaneously.
In sum, in the method for the invention, during chemical vapor deposition method, need to feed heavy specific gas, bombardment when increasing film deposition (bombard), therefore can deposit the high compression stress nitride layer of one deck densification, the thickness of while compresses nitride layer, and the effect that increases contact hole etching process window (process window) is arranged.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100772182A CN100536087C (en) | 2006-04-30 | 2006-04-30 | Method for manufacturing compressive nitride layer and method for forming transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100772182A CN100536087C (en) | 2006-04-30 | 2006-04-30 | Method for manufacturing compressive nitride layer and method for forming transistor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910134316A Division CN101533782A (en) | 2006-04-30 | 2006-04-30 | Method for forming metal oxide semiconductor transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101064254A CN101064254A (en) | 2007-10-31 |
| CN100536087C true CN100536087C (en) | 2009-09-02 |
Family
ID=38965156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100772182A Active CN100536087C (en) | 2006-04-30 | 2006-04-30 | Method for manufacturing compressive nitride layer and method for forming transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100536087C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594364B (en) * | 2012-08-14 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of a kind of semiconducter device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| US20050285137A1 (en) * | 2004-06-29 | 2005-12-29 | Fujitsu Limited | Semiconductor device with strain |
| CN101088150A (en) * | 2004-11-16 | 2007-12-12 | 应用材料股份有限公司 | Tensile and compressive stressed materials for semiconductors |
-
2006
- 2006-04-30 CN CNB2006100772182A patent/CN100536087C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030040158A1 (en) * | 2001-08-21 | 2003-02-27 | Nec Corporation | Semiconductor device and method of fabricating the same |
| US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
| US20050285137A1 (en) * | 2004-06-29 | 2005-12-29 | Fujitsu Limited | Semiconductor device with strain |
| CN101088150A (en) * | 2004-11-16 | 2007-12-12 | 应用材料股份有限公司 | Tensile and compressive stressed materials for semiconductors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101064254A (en) | 2007-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11664376B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN101584025B (en) | Method of producing highly strained pecvd silicon nitride thin films at low temperature | |
| TWI411100B (en) | Si-Ge based semiconductor device with high stress lining for improving channel carrier mobility | |
| US20070128806A1 (en) | High performance CMOS transistors using PMD liner stress | |
| US7485515B2 (en) | Method of manufacturing metal oxide semiconductor | |
| US20050032321A1 (en) | Strained silicon MOS devices | |
| US20060172556A1 (en) | Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor | |
| JP2008041981A (en) | Manufacturing method of semiconductor device | |
| US20100270622A1 (en) | Semiconductor Device Having a Strain Inducing Sidewall Spacer and a Method of Manufacture Therefor | |
| CN103066122A (en) | MOSFET and manufacturing method thereof | |
| KR100821089B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN101120437A (en) | Dielectric film and method for forming same | |
| CN101162707B (en) | Semiconductor device structure and method of forming transistor density based stress layers | |
| US20050118770A1 (en) | Method for introducing hydrogen into a channel region of a metal oxide semiconductor (MOS) device | |
| CN100536087C (en) | Method for manufacturing compressive nitride layer and method for forming transistor | |
| US7429517B2 (en) | CMOS transistor using high stress liner layer | |
| CN109830433A (en) | The method for making semiconductor element | |
| JP2002222941A (en) | Mis semiconductor device and manufacturing method therefor | |
| CN111933566A (en) | Method for forming shallow trench isolation structure | |
| US8114784B2 (en) | Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement | |
| US20070148927A1 (en) | Isolation structure of semiconductor device and method for forming the same | |
| JP2007005627A (en) | Method for manufacturing semiconductor device | |
| US20080160786A1 (en) | Method for increasing film stress and method for forming high stress layer | |
| KR20110137435A (en) | Manufacturing Method of Semiconductor Device | |
| CN101533782A (en) | Method for forming metal oxide semiconductor transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |