CN100533584C - serial read-only memory device and memory system - Google Patents
serial read-only memory device and memory system Download PDFInfo
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- CN100533584C CN100533584C CNB2004101015195A CN200410101519A CN100533584C CN 100533584 C CN100533584 C CN 100533584C CN B2004101015195 A CNB2004101015195 A CN B2004101015195A CN 200410101519 A CN200410101519 A CN 200410101519A CN 100533584 C CN100533584 C CN 100533584C
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Abstract
The invention relates to a serial read-only memory (SROM) device, which corresponds to an address range and comprises a memory array, an address clock pin for receiving an address clock signal so as to start an address cycle, a data clock pin for receiving a data clock signal so as to start a data cycle, a chip select/cascade (CS/CAS) pin for receiving a first control signal in the address cycle and a second control signal in the data cycle, a first data pin for receiving an address in the address cycle and outputting data in the data cycle, and a second data pin for receiving external data and being connected with the first data pin through a cascade data path defined between the first data pin and the second data pin. When the serial data path is in a conducting state, the external data received by the second data pin can be transmitted to the first data pin.
Description
Technical field
The present invention is particularly to a kind of new serial connection type serial ROM relevant for a kind of serial (serial) ROM device.
Background technology
In computer system, usually hardware identification symbol (hardware identifier) or system configuration information are to be stored in ROM (read-only memory) (read-only memory, hereinafter to be referred as ROM) device in, then be stored in sometimes among the serial ROM (serial ROM is hereinafter to be referred as SROM).A SROM comprises memory cell array usually, can supply sequential access.Each memory cell is corresponding to an address, and SROM is then corresponding to an address realm.When the address of delivering to SROM was dropped in the address realm of SROM, SROM then was activated, and stored this address down, and stored the memory cell that the address is consistent therewith read data from SROM.When data after a memory cell is read thus, increase progressively this automatically and store the address, read next memory cell in the array again.Computer system is when starting, and controller can provide an initial address, if this initial address drops in the address realm of SROM, then data can be read from SROM sequentially.
The memory capacity that provides in the accumulator system up to 16Mb normally is provided serial ROM W551C by winbond electronics (Winbond Electronics Corp.) manufacturing.The part of an accumulator system 100 represented in Fig. 1 summary, and it comprises the W551C of a plurality of SROM of having 102a and 102b, and it is connected to several bus lines.These bus lines can comprise data clock pulse line, the address clock pulse line that is used for the receiver address clock signal that is used for receiving the data clock signal and be used for the data line of the receiver address or the data of transmission.These bus lines more are connected to the other parts of system 100, and it is whole to be to represent with peripheral circuit 104, is used to provide control signal or swap date.Peripheral circuit 104 can comprise microprocessor, ROM arranged side by side or the like.Each serial ROM W551C 102a corresponds to different address realms respectively with 102b.For instance, serial ROM W551C 102a can be the address realm of 101-200, and serial ROM W551C 102b then can be the address realm of 201-300.
When system 100 started, peripheral circuit 104 can see through address clock pulse line, send the address clock signal, and SROM 102a and 102b and begin an address cycle are used for resetting.Then at this point the location is in the cycle, and initial address can see through data line and deliver to all SROM.If this initial address drops in the address realm of certain SROM, then this SROM can be activated and this initial address is deposited in wherein.Follow in data in the cycle, data is positioned at the memory cell of this initial address and reads from the SROM that is activated.In the example of W551C SROM, data can be in the data clock signal during one or two edge side in each cycle, reads from SROM.Read from memory cell after the data, being stored in this address that is activated among the SROM just can automatically increase by 1 at every turn, the more next memory cell of access.
Because the same time is merely able to SROM of access, each SROM must be assigned to the address realm different with other SROM in accumulator system 100.In addition, owing to only have 24, so according to the framework of this 24 bit address, only there is 16Mb in the maximal memory space of accumulator system 100 in the address that address cycle is imported.Want the memory space of extended storage system 100, then need to be increased in the address bit quantity that address cycle is delivered to SROM, and this practice needs the other parts of system, for example hardware or software are revised in the lump on a large scale.
Summary of the invention
The embodiment of the invention proposes a kind of serial ROM (SROM) device, its corresponding address realm, and comprise memory array, the receiver address clock signal is so that start the address clock pulse pin of an address cycle, reception data clock signal is so that start the data clock pulse pin in a data cycle, in address cycle, receive first control signal and receive chip selection/serial connection (CS/CAS) pin of second control signal in the cycle in data, receiver address and export the first data pin of data in the cycle in address cycle in data, and receive outside data and can see through and be defined in the second data pin that serial connection data path therebetween is connected with the first data pin.When the serial connection data path was conducting state, the outside data that the second data pin is received can be sent to the first data pin.
In addition, the embodiment of the invention proposes a kind of accumulator system in addition, comprising: address clock pulse bus, and in order to the transfer address clock signal, wherein above-mentioned address clock signal starts an address cycle; Data clock pulse bus, in order to transmit the data clock signal, wherein above-mentioned data clock signal starts a data cycle; Data bus, in order in above-mentioned address cycle, transmitting an address, and in above-mentioned data transmission data in the cycle; Chip controller; And a plurality of serial ROMs (SROM) chip.Each SROM chip corresponds respectively to an individual address scope and comprises: memory array; Address clock pulse pin is coupled to above-mentioned address clock pulse bus, in order to receive above-mentioned address clock signal; Data clock pulse pin is coupled to above-mentioned data clock pulse bus, in order to receive above-mentioned data clock signal; Chip selection/serial connection (CS/CAS) pin is coupled to the said chip controller, in order to receive a serial connection signal in address cycle, receives a chip select signal in the cycle in data; The first data pin is in order to receiving above-mentioned address, in data output data in the cycle in address cycle; And the second data pin, one of be defined in therebetween the serial connection data path and be connected in order to receive outside data and can see through with the above-mentioned first data pin, wherein when above-mentioned serial connection data path was conducting state, the said external data that the above-mentioned second data pin is received can be sent to the above-mentioned first data pin.
Further feature that the present invention is relevant and advantage then part are found in the following description, and part can realize and knows by understanding easily in the explanation or seeing through invention.The feature of invention and advantage then can see through appended claim specifically noted element and combination thereof and can understand and learn.
Description of drawings
Fig. 1 shows use a plurality of existing serial ROMs (SROM) a kind of existing accumulator system that chip constituted.
Fig. 2 shows the structural drawing of the SROM that meets the embodiment of the invention.
Fig. 3 shows a plurality of accumulator systems that SROM constituted shown in Figure 2.
The figure number explanation
100 accumulator systems; 102a, 102b SROM; 104 peripheral circuits;
200、200-1、200-2、200-3、200-4、200-5 SROM；
202 address clock pulse pins; 204 data clock pulse pins;
206 first data pins; 208 chip selection/serial connection pins;
210 second data pins; 212 chip controllers;
214 memory arrays; 216 on-off elements;
218 latch components; 300 accumulator systems;
302 address clock pulse buses; 304 data clock pulse buses;
306 data buss; 308 controllers.
Embodiment
The Ref. No. of the embodiment of the invention and example then cooperate appended graphic being described in detail as follows.In the following description, except annotation, the identical reference numerals that is adopted in all are graphic is to be used for indicating identical or the similar elements part.
A kind of SROM accumulator system with a plurality of serial ROMs (SROM) chip is proposed in the embodiment of the invention.And in the SROM of embodiment of the invention accumulator system, be used under the situation of address bit quantity of addressing SROM chip not increasing, its memory capacity can expand easily.In other words, do not need because expand the memory storage amount, and revise the bus structure of this accumulator system.Below with reference to Fig. 2 and Fig. 3 the embodiment of the invention is described.
Fig. 2 represents the SROM 200 of the embodiment of the invention.As shown in Figure 2, SROM 200 has at least five pins, comprises address clock pulse pin 202, data clock pulse pin 204, the first data pin 206, chip selection/serial connection (CS/CAS) pin 208 and the second data pin 210.In SROM200, chip controller 212 is coupled to address clock pulse pin 202 and receives an address clock signal, in order to begin an address cycle.Chip controller 212 also is coupled to data clock pulse pin 204 and receives a data clock signal, in order to begin a data cycle.Chip controller 212 also is coupled to the first data pin 206 and receives an address in address cycle.Chip controller 212 also is coupled to CS/CAS pin 208 and receives a chip select signal.The operation of chip controller 212 control store arrays 214, it is in order to give information on the first data pin 206.Memory array 214 comprises a memory cell array, and each memory cell is corresponding to an address.The address of all memory cells then defines the address realm of SROM 200.On-off element 216 is connected between the first data pin 206 and the second data pin 210.218 of breech lock (latch) elements couple address clock pulse pin 202 and CS/CAS pin 208, and in order to during address cycle, breech lock is lived the signal on the CS/CAS pin 208.The state of on-off element 216 is then being controlled in the output of latch component 218.When latch component 218 was output as logic ＂ 1 ＂, on-off element 216 was closed circuit state, the data path between the conducting first data pin 206 and the second data pin 210, and this is called a serial connection data path.When latch component 218 was output as logic ＂ 0 ＂, on-off element 216 was an open-circuit condition, and this serial connection data path then is blocked.
During operation, the address clock signal is sent to address clock pulse pin 202 earlier, so that the start address cycle.During address cycle, one 24 address sees through the first data pin 206 and is sent to chip controller 212 in the then mode of position of position.If the address that is received is to drop in the address realm of SROM 200, then SROM 200 is activated and this address is stored among the SROM 200.Then, receive the data clock signal, the beginning data cycle at data clock pulse pin 204.In cycle,, read data in data by memory array 214 from memory cell corresponding to stored address.After finishing access corresponding to the memory cell of stored address, stored address can add 1 automatically, the next memory cell of access.Data is then by 206 outputs of the first data pin.
In address cycle, appear at the first kind control signal of CS/CAS pin 208 or claim the serial connection signal, be latched in latch unit 218, it is used for the state of gauge tap element 216.If the serial connection signal is a logical zero, then latch unit 218 outputs " 0 " and on-off element 216 are open-circuit condition.If the serial connection signal is a logical one, then latch unit 218 outputs " 1 " and on-off element 216 are closed circuit state.When on-off element 216 is closed circuit state, the serial connection data path of SROM 200 is conducting, and outside data can provide to the second data pin 210, and SROM 200 can these data to the first data pins 206 of output.
, appear at the second class control signal of CS/CAS pin 208 or claim that chip select signal is then determined whether that by chip controller 212 usefulness SROM 200 is selected in the cycle in data.If chip select signal is a logical zero, then SROM 200 is disengaged selection, and does not have data can be read out memory array 214 in the cycle in data.Otherwise then selected the and data of SROM 200 can be read from memory array 214.
New SROM structure shown in Figure 2 can be used accumulator system of construction, is used for addressing wherein under the condition of each SROM chip required address figure place, extended storage capacity needn't increasing.Fig. 3 then shows an accumulator system 300 of the embodiment of the invention, and it adopts SROM shown in Figure 2 200 to come extended storage capacity.
As shown in Figure 3, accumulator system 300 comprises a plurality of SROM 200, is denoted as 200-1,200-2,200-3,200-4,200-5,200-6 or the like respectively.202 of the address clock pulse pins of each SROM 200 are coupled to address clock pulse bus 302, in order to the receiver address clock signal.204 of the data clock pulse pins of each SROM 200 are coupled to data clock pulse bus 304, in order to receive the data clock signal.
The configuration mode of these SROM 200 is to adopt polyphone (cascaded) kenel, and one or more SROM200 is configured in first row (tier), and one or more SROM is configured in second row, and one or more SROM is configured in the 3rd row, and the rest may be inferred.The first data pin 206 of arbitrary SROM 200 in first row is coupled to data bus 306, is used for receiver address signal in address cycle, and at the data signal of giving information in the cycle.Arbitrary SROM 200 in other row who is not first row, its 206 of first data pin is coupled to the second data pin 210 of its next-door neighbour first line center SROM 200.For instance, the first data pin 206 of the interior arbitrary SROM of second row is coupled to the second data pin 210 of SROM 200 in first row.The first data pin 206 of arbitrary SROM is coupled to the second data pin 210 of SROM 200 in second row in the 3rd row.
With regard to example accumulator system 300 shown in Figure 3, SROM 200-1 and SROM 200-2 are configured in first row, so the first data pin 206 of SROM 200-1 and 200-2 directly is coupled to data bus 306.SROM 200-3,200-4,200-5 are then second row.The first data pin 206 of SROM 200-3 and 200-4 is coupled to the second data pin 210 of SROM 200-1.The first data pin 206 of SROM 200-5 is coupled to the second data pin 210 of SROM 200-2.SROM 200-6 is then the 3rd row, so its first data pin 206 is coupled to the second data pin 210 of SROM 200-3.Therefore, SROM 200-3 sees through SROM 200-1 to be coupled to data bus 306, so if the serial connection data path of SROM 200-1 is conducting state and SROM 200-3 is activated and selects, just the data that is stored in the SROM 200-3 can be come access through SROM 200-1.Similarly, SROM 200-6 is coupled to data bus 306 through SROM 200-1 and 200-3, so if the serial connection data path of SROM200-1 and SROM 200-3 is conducting state and SROM 200-6 is activated and selects, just the data that is stored in the SROM 200-6 can be come access through SROM 200-1 and 200-3.
As shown in Figure 3, accumulator system 300 more comprises a controller 308, it provides serial connection signal and chip select signal to each SROM 200, allows each SROM 200 can be selected independently of one another or remove and select, and allows its serial connection data path be conducting or blocking state.Therefore, even have two or more SROM 200 to have the overlapping address scope and in address cycle, all be activated, still can see through control and allow the same time only get a SROM 200.The result is that accumulator system 300 can be by allowing two or more SROM 200 have overlapping address realm, and unlimited extended storage capacity, is used for all SROM 200 required address bit quantity of addressing simultaneously still to keep identical.
In when operation, see through address clock pulse bus 302 earlier, the address clock signal is delivered to the address clock pulse pin 202 of all SROM 200, start address cycle.In address cycle, an address that for example has 24 sees through the chip controller 212 that the data bus 306 and the first data pin 206 are delivered to each SROM 200 then in the then mode of position of position.If received address is dropped in the address realm of certain SROM 200, this SROM then can be activated, and this address is stored in its inside.308 of controllers can provide the CS/CAS pin 208 of a serial connection signal to each SROM 200 in address cycle, be used for controlling the serial connection data path of indivedual SROM 200.
Then, see through the data clock pulse pin 204 that 304, one data clock signals of data clock pulse bus then are sent to all SROM 200, the beginning data cycle.In cycle, data is read by the SROM200 that is activated in data.If the SROM that is activated 200 is that data can directly output to data bus 306 first row.If the SROM that is activated 200 is not first row, data then can see through one or more other SROM 200 and deliver to data bus 306.That is to say that suppose that the polyphone data path of these other SROM 200 is conducting state, the SROM 200 that then is activated just can be coupled to data bus 306 indirectly.In cycle, chip select signal can provide the CS/CAS pin 208 to each SROM 200 in data, in order to select or to remove and select indivedual SROM 200.
Because accumulator system 300 allows repeat to address (RA) scope between two or more SROM 200, be activated so in address cycle, have above a SROM 200, and controller 308 must provide suitable control signal to SROM 200, so that guarantee that each time only can SROM 200 of access, below explanation in detail.
For instance, in accumulator system 300,, in address cycle, have one and drop in the SROM 200-1 address realm initial address and deliver to all SROM 200, and start SROM 200-1 for access SROM 200-1.Chip select signal with logical one then provides the CS/CAS pin 208 to SROM 200-1 in cycle data, make the selected and data of SROM 200-1 to read from SROM200-1.For having in the accumulator system 300 and SROM 200-1 not for the SROM 200 of overlapping address scope, in address cycle, can't start these SROM 200, therefore provide control signal can't throw into question to these SROM 200.Yet,, must avoid access to arrive these SROM 200 in the cycle in data for for the SROM 200 that has in the accumulator system 300 with SROM 200-1 overlapping address scope.Avoid the mode of access to select these SROM 200, perhaps block the data path of these SROM 200 and data bus line 306 through removing in the cycle in data.For instance,, drop between 1 and 1000, then can start SROM 200-1 and 200-3 so the initial address that is provided in address cycle is provided if SROM 200-1 and SROM 200-3 have address realm 1-1000.Controller 208 can provide the chip select signal of a logical zero to SROM 200-3 in cycle data, remove to select SROM 200-3 thus, perhaps provide the serial connection signal of a logical zero to block the serial connection data path of SROM 200-1 to SROM 200-1.Can block the data path of SROM200-3 and data bus 306 thus.
In the example of another access SROM 200-4, in address cycle, an initial address that drops on the SROM200-4 address realm can be delivered to each SROM 200, and start SROM 200-4.In order to ensure the data path that is present in 306 of SROM 200-4 and data buss, the serial connection data path of SROM 200-1 must conducting.Therefore, in address cycle, the serial connection signal that a logical one must be provided is to SROM 200-1.At this moment, if in accumulator system 300, there is another SROM 200, it has the address realm overlapping with SROM 200-4, then must provide the chip select signal of a logical zero to this another SROM 200 in the cycle in data, remove to select this another SROM 200 thus, also or blocking-up at the data path of 306 of this another SROM 200 and data buss.Here the address realm and the SROM 200-4 that suppose SROM200-1 are overlapping, then must provide the chip select signal of a logical zero to SROM 200-1 in cycle data.Yet, must be noted that the serial connection data path of SROM 200-1 must conducting, the data of access SROM 200-4 thus.In another example, if the address realm of SROM200-3 and SROM 200-4 are overlapping, then can select following a kind of mode: in cycle data, remove selection SROM 200-6 by the chip select signal that a logical zero is provided; Or by in address cycle, the serial connection signal of logical zero being delivered to the path that SROM 200-3 blocks SROM 200-6 and data bus line 306.Similarly, if the address realm of SROM 200-2 and SROM 200-4 are overlapping, then can remove and select SROM200-2 by the chip select signal of in cycle data, sending into logical zero.If the address realm of SROM 200-5 and SROM 200-4 are overlapping, then can be chosen in the chip select signal of sending into logical zero in the cycle data and remove SROM 200-5, or in address cycle, the serial connection signal of logical zero delivered to the path that SROM 200-2 blocks 306 of SROM 200-5 and data buss.
Mandatory declaration be that above-mentioned accumulator system 300 only is an illustration, be not in order to limit embodiments of the present invention.The SROM of application-specific requirement can see through similar mode and be connected in series, and unconfined memory capacity is provided.For instance, the accumulator system embodiment that meets spirit of the present invention can comprise and surpass or be less than 3 rows and every row can comprise any amount of SROM.Only need controller (for example controller 308 of accumulator system 300) adjustment is suitably controlled signal to all SROM to provide.The accumulator system that meets spirit of the present invention then can adopt any way that control signal is provided, and for example is connected in series signal and chip select signal, clashes as long as can avoid having between the two or more SROM of overlapping address scope.
In addition, the chip select signal that is logic of propositions " 1 " in the above description is in order to selecting indivedual SROM, and the chip select signal of logical zero is selected indivedual SROM in order to remove.Also the serial connection signal of logic of propositions " 1 " the CS/CAS pin 208 of delivering to SROM 200 can allow wherein on-off element 216 is closed condition in addition, with the serial connection data path of conducting SROM 200; The CS/CAS pin 208 that the serial connection signal of logical zero is delivered to SROM 200 can allow wherein on-off element 216 is open-circuit condition, blocks the serial connection data path of SROM 200 thus.Yet, haveing the knack of this operator is appreciated that, select indivedual SROM and the logical zero of serial connection signal or the serial connection data path state that logical one is indicated SROM by the logical zero of chip select signal or logical one, only for the selection of relativity and can decide according to these SROM practical applications.
In addition, mandatory declaration be " row (tier) " at this only be the electric connection that is used for representing between SROM, be not to be used for limiting the actual disposition mode of SROM on circuit board.
Claims (21)
1. serial ROM device, its corresponding address realm is characterized in that, comprising:
Memory array;
Address clock pulse pin, in order to the receiver address clock signal, wherein above-mentioned address clock signal starts an address cycle;
Data clock pulse pin, in order to receive the data clock signal, wherein above-mentioned data clock signal starts a data cycle;
The first data pin is in order to receiver address in address cycle, in data output data in the cycle; And
The second data pin, be connected with the above-mentioned first data pin in order to receive outside data and can see through a serial connection data path that is defined in therebetween, wherein when above-mentioned serial connection data path was conducting state, the said external data that the above-mentioned second data pin is received can be sent to the above-mentioned first data pin; And
Chip selection/serial connection pin, in order in address cycle, to receive one first control signal, receive one second control signal in cycle in data, wherein above-mentioned first control signal is in order to determine the state of an on-off element, above-mentioned on-off element is in order to control above-mentioned serial connection data path, and above-mentioned second control signal is selected in order to decision or removed and select above-mentioned serial ROM device.
2. serial ROM device as claimed in claim 1, it is characterized in that, above-mentioned memory array comprises the array that is made of a plurality of memory cell, each memory cell is corresponding to an address, and the address definition of all memory cells goes out the address realm of described serial ROM device.
3. serial ROM device as claimed in claim 1 is characterized in that, more comprises a latch component, in order to live in to state first control signal at the address cycle breech lock.
4. serial ROM device as claimed in claim 1, it is characterized in that, when the address in the cycle from the received address of the first data pin was address realm at described serial ROM device, then described serial ROM device was activated.
5. serial ROM device as claimed in claim 4, it is characterized in that, above-mentioned second control signal determines that described serial ROM device is selected or removes and select, and when described serial ROM device was activated and is selected, the above-mentioned first data pin is read and delivered to data from above-mentioned memory array.
6. serial ROM device as claimed in claim 1, it is characterized in that, more comprise a controller, it is coupled to above-mentioned address clock pulse pin, above-mentioned data clock pulse pin, said chip selection/serial connection pin and the above-mentioned first data pin, wherein above-mentioned controller determines according to the address that the above-mentioned first data pin is received whether described serial ROM device is activated in address cycle, and above-mentioned first control signal that is received according to said chip selection/serial connection pin in address cycle determines the whether conducting of above-mentioned serial connection data path, and determines in above-mentioned second control signal that data was received according to said chip selection/serial connection pin in the cycle whether described serial ROM device is selected.
7. serial ROM device as claimed in claim 1 is characterized in that, the above-mentioned data cycle is to begin after above-mentioned address cycle.
8. an accumulator system is characterized in that, comprising:
Address clock pulse bus, in order to the transfer address clock signal, wherein above-mentioned address clock signal starts an address cycle;
Data clock pulse bus, in order to transmit the data clock signal, wherein above-mentioned data clock signal starts a data cycle;
Data bus, in order in above-mentioned address cycle, transmitting an address, and in above-mentioned data transmission data in the cycle;
Chip controller; And
A plurality of serial ROM chips, each corresponds respectively to an individual address scope and comprises:
Memory array;
Address clock pulse pin is coupled to above-mentioned address clock pulse bus, in order to receive above-mentioned address clock signal;
Data clock pulse pin is coupled to above-mentioned data clock pulse bus, in order to receive above-mentioned data clock signal;
The first data pin is in order to receiving above-mentioned address, in data output data in the cycle in address cycle; And
The second data pin, be connected with the above-mentioned first data pin in order to receive outside data and can see through a serial connection data path that is defined in therebetween, wherein when above-mentioned serial connection data path was conducting state, the said external data that the above-mentioned second data pin is received can be sent to the above-mentioned first data pin;
On-off element is in order to control above-mentioned serial connection data routing; And
Chip selection/serial connection pin, be coupled to the said chip controller, in order in address cycle, to receive a serial connection signal, receive a chip select signal in cycle in data, wherein above-mentioned serial connection signal is in order to determine the state of above-mentioned on-off element, above-mentioned on-off element is in order to control above-mentioned serial connection data path, select signal in the said chip that the said chip selection/serial connection pin of each serial ROM chip is received, select or remove and select corresponding above-mentioned serial ROM device in order to decision.
9. accumulator system as claimed in claim 8, it is characterized in that, the above-mentioned memory array of each serial ROM chip comprises the array that is made of a plurality of memory cell, each memory cell is corresponding to an address, and the address definition of all memory cells goes out the address realm of corresponding above-mentioned serial ROM chip in the above-mentioned memory array.
10. accumulator system as claimed in claim 8 is characterized in that, each serial ROM chip more comprises:
The door lock element is in order to live in to state the serial connection signal at the address cycle breech lock.
11. accumulator system as claimed in claim 8, it is characterized in that, for any above-mentioned serial ROM chip,, then start corresponding above-mentioned serial ROM chip when the address in the cycle is during at its address realm from its received address of first data pin.
12. accumulator system as claimed in claim 11, it is characterized in that, the said chip that each above-mentioned serial ROM chip chips selection/serial connection pin is received is selected signal, in order to determine that corresponding above-mentioned serial ROM chip is selected or to remove and select; And when corresponding above-mentioned serial ROM chip was activated and is selected, data was read from above-mentioned memory array wherein, and delivers to the above-mentioned first data pin wherein.
13. accumulator system as claimed in claim 8, it is characterized in that, each above-mentioned serial ROM chip, more comprise a controller, it is coupled to above-mentioned address clock pulse pin, above-mentioned data clock pulse pin, said chip selection/serial connection pin and the above-mentioned first data pin in the corresponding above-mentioned serial ROM chip; The wherein above-mentioned controller address that the basis above-mentioned first data pin is wherein received in address cycle, whether the corresponding above-mentioned serial ROM chip of decision is activated, and the above-mentioned serial connection signal that basis said chip selection/serial connection pin is wherein received in address cycle, the whether conducting of decision above-mentioned serial connection data path wherein, and at the data said chip selection signal that basis said chip selection/serial connection pin is wherein received in the cycle, whether the above-mentioned serial ROM chip of decision correspondence is selected.
14. accumulator system as claimed in claim 8 is characterized in that, the above-mentioned data cycle is to begin after above-mentioned address cycle.
15. accumulator system as claimed in claim 8, wherein above-mentioned a plurality of serial ROM chip configuration becomes one or more rows, and be electrically connected to each other in the serial connection mode, wherein the above-mentioned first data pin at first each serial ROM chip of arranging is to be connected directly to above-mentioned data bus.
16. accumulator system as claimed in claim 8, it is characterized in that, above-mentioned a plurality of serial ROM chip configuration becomes two or more rows, and wherein the above-mentioned first data pin at second each serial ROM chip of arranging is the above-mentioned second data pin that is coupled to one of serial ROM chip person among first row.
17. accumulator system as claimed in claim 8, it is characterized in that, above-mentioned a plurality of serial ROM chip configuration becomes to surpass two rows, wherein the above-mentioned first data pin of each serial ROM chip in other row who is not first row is the above-mentioned second data pin that is coupled to one of its next-door neighbour first line center serial ROM chip person.
18. accumulator system as claimed in claim 8, it is characterized in that, the said chip controller couples so that provide above-mentioned car to connect signal to above-mentioned a plurality of serial ROM chips in above-mentioned address cycle, and provides said chip to select the above-mentioned a plurality of serial ROM chips of signal in the cycle in above-mentioned data.
19. accumulator system as claimed in claim 18, it is characterized in that, the said chip controller provides above-mentioned serial connection signal and said chip to select signal to above-mentioned a plurality of serial ROM chips, so as in data only to allow above-mentioned a plurality of serial ROM chip in the cycle one by access.
20. accumulator system as claimed in claim 19, it is characterized in that, if one of in above-mentioned a plurality of serial ROM chip the person have with above-mentioned data in the cycle by the overlapping address realm of another person of access, then the said chip controller is sent chip select signal person one of to above-mentioned a plurality of serial ROM chips, with so that it is removed effectively selects.
21. accumulator system as claimed in claim 19, it is characterized in that, if one of in above-mentioned a plurality of serial ROM chip the person have with above-mentioned data in the cycle by the overlapping address realm of another person of access, then said chip control is sent serial connection signal and chip select signal to above-mentioned a plurality of serial ROM chips, one of makes in above-mentioned a plurality of serial ROM chips that the path between person and above-mentioned data bus is blocked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101015195A CN100533584C (en) | 2004-12-21 | 2004-12-21 | serial read-only memory device and memory system |
Applications Claiming Priority (1)
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| CNB2004101015195A CN100533584C (en) | 2004-12-21 | 2004-12-21 | serial read-only memory device and memory system |
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| CN1797603A CN1797603A (en) | 2006-07-05 |
| CN100533584C true CN100533584C (en) | 2009-08-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9697141B2 (en) * | 2014-10-17 | 2017-07-04 | Sk Hynix Memory Solutions Inc. | LBA blocking table for SSD controller |
| CN105912483B (en) * | 2015-02-23 | 2019-06-21 | 东芝存储器株式会社 | Storage System |
| CN110879633B (en) * | 2018-09-05 | 2021-06-25 | 宇瞻科技股份有限公司 | double data rate memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6269047B1 (en) * | 1994-01-31 | 2001-07-31 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US6504778B1 (en) * | 1999-10-13 | 2003-01-07 | Nec Corporation | Semiconductor memory device |
| EP1287530A1 (en) * | 2000-05-01 | 2003-03-05 | Advanced Technology Materials, Inc. | Reduction of data dependent power supply noise when sensing the state of a memory cell |
| CN1402250A (en) * | 2001-08-16 | 2003-03-12 | 联华电子股份有限公司 | Memory circuit and output buffer thereof |
| CN1412615A (en) * | 2002-10-24 | 2003-04-23 | 统宝光电股份有限公司 | Switching signal generator |
| CN1523608A (en) * | 2003-01-16 | 2004-08-25 | ���µ�����ҵ��ʽ���� | Semiconductor memory device |
-
2004
- 2004-12-21 CN CNB2004101015195A patent/CN100533584C/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6269047B1 (en) * | 1994-01-31 | 2001-07-31 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US6504778B1 (en) * | 1999-10-13 | 2003-01-07 | Nec Corporation | Semiconductor memory device |
| EP1287530A1 (en) * | 2000-05-01 | 2003-03-05 | Advanced Technology Materials, Inc. | Reduction of data dependent power supply noise when sensing the state of a memory cell |
| CN1402250A (en) * | 2001-08-16 | 2003-03-12 | 联华电子股份有限公司 | Memory circuit and output buffer thereof |
| CN1412615A (en) * | 2002-10-24 | 2003-04-23 | 统宝光电股份有限公司 | Switching signal generator |
| CN1523608A (en) * | 2003-01-16 | 2004-08-25 | ���µ�����ҵ��ʽ���� | Semiconductor memory device |
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| CN1797603A (en) | 2006-07-05 |
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