CN100527642C - Bidirectional turbo ISI canceller-based DSSS receiver for high-speed wireless LAN - Google Patents

Abstract

A bidirectional turbo ISI canceller cancels precursor-ISI (94) as well as postcursor-ISI (90) in a received signal without incorporating a multiplicative feedforward equalization filter. This is accomplished by taking a three-step receiver design approach. In the first step, an optimal single-symbol RAKE receiver is 1 designed to comprise a CMF (9), a codeword correlator bank, and an energy bias EB (15) canceller under the assumption that no ISI is generated by preceding or trailing symbols. In a second step, a DFE (16) is included for suppressing postcursor-ISI (90) caused by a preceding symbol. Finally, a precursor-ISI (94) canceler is used to remove the remaining ISI caused by a trailing symbol. All three components may 10 be integrated into a BTIC-based receiver applying turbo-iteration processing.

Description

Reduce method and system, ISI arrester and the receiver of distorted signals in the receiver

Technical field

Relate generally to radio communication of the present invention, more particularly, the present invention relates to by adopting two-way spy to broadcast (turbo) ISI arrester, iteration remove on the wireless multipath channel (precursor) intersymbol interference (precursor inter-symbol interference) in advance (ISI) and direct sequence spread spectrum (DSSS) package receiver of follow-up (postcursor) ISI.

Background technology

The DSSS technology is widely used in the main wireless communication standard such as IS-95, CDMA 2000, W-CDMA, IEEE 802.11 wireless lan (wlan)s and other network.These DSSS systems send information bit in broadband chip (chip) sequence mode usually, but for the embedded data modulator approach, that is, select modulation from prevailing BPSK and QPSK to high order QAM and code word, and they are significantly different.

Current, be used 802.11b standard based on the DSSS system of complementary code keying (CCK) as 5.5Mbps/11Mbps speed, be used for the high speed expansion of 802.11 WLAN of original 1Mbps/2Mbps speed.802.11b DSSS/CCK is based on the spectrum spreading method that code word is selected modulation, the utilization size is 256 the long quaternary benefit of 8-Codeword Sets, and this method can send 4 or 8 information bits by each symbol (symbol).

Because the CCK code word has good auto-correlation and their cross correlation, so common flank speed combination (MRC) RAKE receiver and codeword correlator bank can realize satisfied decoding performance with Gauss or moderate multipath channel.Yet, when multidiameter is expanded greater than 100ns, only no longer can support this performance based on the correlator bank of RAKE, therefore, need replenish composite signal to this receiver and handle, for example, disturb (ICI) equilibrium between ISI or chip.

In order to realize that MRC handles and equilibrium, this receiver need be known multipath channel coefficient (coefficient) accurately.In the variation of multipath channel very slow and its profile by the typical radio lan environment of close separation under, usually utilize broadband preposition (preamble) sequence partly to estimate channel coefficients in advance, then, utilize the decode data symbol part of same grouping of this estimated value.In this case, can with its tap (tap) form of channel matched filter (CMF) of conjugation of (time-inversed) channel estimation value time reversal, realize the MRC RAKE receiver, and, it is usually located at before the correlator bank, to make up by finished multipath before code word is relevant, it is minimum that receiver is realized that complexity is reduced to.During detecting data symbol, CMF not only has the rake advantage, and can guarantee robust time tracking (time-tracking), because after passing through CMF, this signal has balancing waveform with respect to real-valued central peak.

On the contrary, if in order to improve the detection performance, between CMF and codeword correlator bank, adopt decision zeedback equalizer (DFE), then also should utilize preposition part to estimate related DFE coefficient, only be used to delete under the situation of the feedback filter of ISI in advance, can utilize the simple auto-correlation of CMF coefficient, directly calculate the DFE coefficient.Yet, if insert feedforward filter for the ISI that goes ahead of the rest by inhibition further improves performance, then the complexity of receiver significantly improves because must use one of complicated matrixing, spectrum factorization (factorization) or adaptive equalizer training or more than.

In Data Detection was handled, feedforward filter needed complicated multiplying, and feedback filter only needs add operation.Therefore, in the high speed WLAN of reality transmitted in packets, DFE only is made of feedback filter usually, and can not suppress ISI in advance.When multidiameter is expanded when elongated, remaining ISI in advance has decisive influence to the detection of packets performance.

In view of the foregoing, need a kind of in fact feasible ISI in advance to eliminate system and method, more particularly, but need a kind of ISI in advance that can in comprising the various communication systems that are not limited to the DSSS package receiver, use to eliminate system.

Summary of the invention

An object of the present invention is to provide a kind of practicable ISI in advance and eliminate system and method, but they can be used to comprise the various communication systems that are not limited to the DSSS package receiver.

Another object of the present invention provides a kind of improved ISI in advance that can realize and eliminates system and method on the DSSS/CCK communication system.

Another object of the present invention provide a kind of in multipath channel the improved DSSS/CCK RAKE receiver of robust, its robustness is to realize by the iteration ISI removing method of introducing a kind of novelty and device, this method and apparatus is used for eliminating ISI in advance, the system that is suitable for carrying out DSSS/CCK communication.

Another object of the present invention provides a kind of DSSS/CCK receiver, is reducing under computational complexity and the situation of time of delay, and this DSSS/CCK receiver ISI that go ahead of the rest at least eliminates, and the ISI elimination but also carry out follow-up ISI elimination of preferably not only go ahead of the rest.

According to an aspect of the present invention, provide a kind of method that is used for reducing distorted signals, comprising: obtain chip sequence from the signal that receives at receiver; According to the previous detection CCK chip sequence that is used to form previous CCK code word, produce follow-up ISI and eliminate item; From chip sequence, eliminate follow-up ISI, to produce chip tolerance; According to described chip tolerance, determine current C CK code word; According to chip estimated value time reversal of current C CK code word, producing in advance, ISI eliminates item; And, from previous CCK code word, eliminate ISI in advance according to chip estimated value time reversal of current C CK code word.

According to a further aspect in the invention, provide a kind of system that is used for reducing distorted signals on receiver, comprising: channel matched filter is used for producing chip sequence according to the signal that receives; Decision zeedback equalizer DFE is used for according to the previous detection CCK chip sequence that is used to form previous CCK code word, produces follow-up ISI and eliminates item, and eliminate follow-up ISI from chip sequence, to produce chip tolerance; And CCK correlation-decision, be used for according to described chip tolerance, produce current C CK code word, wherein according to the conjugate of the chip value of next symbol, DFE produces in advance, and ISI eliminates item, and according to chip estimated value time reversal of current C CK code word, DFE eliminates ISI in advance from previous CCK code word.

According to another aspect of the invention, provide a kind of bidirectional turbo ISI canceller BTIC, comprising: single symbol detector is used for producing chip sequence according to received signal; Follow-up ISI arrester is used for according to the previous detection chip sequence that is used to form previous CCK code word, produces follow-up ISI and eliminates item, and eliminate follow-up ISI from chip sequence, to produce chip tolerance; And the ISI arrester of going ahead of the rest, be used for estimating time reversal according to the chip of the current C CK code word of utilizing the generation of described chip tolerance, produce the ISI that goes ahead of the rest and eliminate item, to eliminate ISI in advance from previous CCK code word.

In accordance with a further aspect of the present invention, provide a kind of receiver, comprising: first feeds back arrester, is used to eliminate the follow-up ISI of symbol generation formerly; The second feedback arrester is used to eliminate the ISI in advance that tail symbol produces, and wherein the first feedback arrester and the second feedback arrester use a DFE coefficient set respectively, and described DFE coefficient set by time reversal to eliminate follow-up ISI and ISI in advance.

Bidirectional turbo ISI canceller (BTIC) is provided, can realizes these and other objects and advantage, this bidirectional turbo ISI canceller (BTIC) is eliminated ISI and follow-up ISI in advance, and does not insert multiplication (multiplicative) feed forward equalization filter.Go ahead of the rest ISI and follow-up ISI removing method of iteration has been applied to simple BPSK modulation case and M unit pulse amplitude modulation situation.Yet, BTIC of the present invention adopt signal processing time reversal, based on tentative judgement (tentative-decision) eliminate in advance and for carry out the DSSS/CCK code word judge they are made amendment after, the integrated approach of iteration (spy broadcasts) signal processing.

Detect performance in order systematically to improve, at least one embodiment of the present invention adopts three step receiver methods for designing.The first step comprises design, is supposing that formerly symbol or afterbody (trailing) symbol do not produce under the situation of ISI, designing optimal list symbol RAKE receiver, and this receiver comprises: CMF, codeword correlator bank and energy-bias (EB).For more real multipath channel situation, second step was inserted the DFE be used to suppress the follow-up ISI that symbol formerly produces.At last, utilize unique precursor ISI arrester to eliminate all the other ISI that tail symbol produces.All these three parts all can be integrated into and adopt the special receiver based on BTIC of broadcasting iterative processing.

When detecting each CCK symbol, each iteration is used twice DFE and codeword correlator bank, to eliminate follow-up ISI and ISI in advance.The DFE coefficient that ISI eliminates because be used to go ahead of the rest is identical with the coefficient that is used to carry out follow-up ISI elimination, so in order to realize BTIC, do not need additional firmware or carry out new coefficient calculations.Because along with the increase of multidiameter expansion, eliminate by the ISI that go ahead of the rest more and more significant to the raising of performance, so for the performance of maintenance DSSS/CCK system in the channel that heavily trails, BTIC is very effective.

Although what preferred embodiment was considered is the receiver design that is applied to high speed 802.11b Wireless LAN system, to improve the decoding performance of receiver under the multipath channel environment, but through revising slightly, other embodiment can be applied to various DSSS communication systems, with improve static state or the multipath channel that slowly declines on decoding performance.

Description of drawings

Fig. 1 (a) and 1 (b) are the schematic diagrames that illustrates respectively according to the preferred embodiment of transmitter and receiver of the present invention, and for example, this embodiment can be used for the DSSS/CCK communication that IEEE 802.11b WLAN is used.

Fig. 2 illustrates the schematic diagram that comprises preposition, head and net load, is used for the DSSS/CCK data packet structure that WLAN uses.

Fig. 3 illustrates the flow chart that can be used to carry out each step of filter coefficient estimation according to one embodiment of present invention.

Fig. 4 is the flow chart that each step that can be used to carry out the CCK correlation-decision block operation according to one embodiment of present invention is shown.

Fig. 5 illustrates the internal structure of a kind of decision zeedback equalizer (DFE) that can be used to eliminate the follow-up ISI that produces according to the present invention in the multipath channel of DSSS/CCK receiver and the schematic diagram of relevant computing.

Fig. 6 illustrates in order to eliminate follow-up ISI and to estimate in order to carry out current C CK code word, the flow chart of each step of being carried out by DFE shown in Figure 5.

Fig. 7 illustrates according to the present invention to be used to eliminate the structure and relevant computing of a kind of chip decision zeedback equalizer time reversal of the DSSS/CCK receiver of ISI in advance that produces in multipath channel, and this equalizer can be the identical DFE shown in Figure 5 according to preferred embodiment.

Fig. 8 illustrates in order to eliminate in advance ISI and to estimate the flow chart of each step that DFE shown in Figure 7 carries out in order to carry out previous CCK code word.

Fig. 9 is used to eliminate follow-up ISI and the schematic diagram based on the DSSS/CCK receiver of bidirectional turbo ISI canceller of ISI in advance according to one embodiment of present invention, wherein handles by iteration (perhaps, the spy broadcasts), estimates and eliminates follow-up ISI and ISI in advance.

Figure 10 illustrates according to current and previous CCK code word, the flow chart of each step that bidirectional turbo ISI canceller shown in Figure 9 is carried out.

Embodiment

Fig. 1 (a) and 1 (b) are the piece figure that for example can be used for the DSSS/CCK communication system of IEEE 802.11b WLAN.Shown in Fig. 1 (a), at first, position, source (source bit) scrambling in the grouping of the 1 pair of data of scrambler, then, time k (k=0,1 ..., k-1), they are organized as k 8 piece 2 (b (k)={ b ₀(k), b ₁(k) ... b ₇(k) }).Then, according to DQPSK encoder 3 ₁, first to (b ₀(k), b ₁(k)) be mapped to different coding phase angle φ ₁(k), and according to encoder 3 ₂, 3 ₃With 3 ₄Interior natural QPSK coding, other position is to (b ₂(k), b ₃(k)), (b ₄(k), b ₅(k)), (b ₆(k), b ₇(k)) be mapped to φ respectively ₂(k), φ ₃(k) and φ ₄Note that these four angles can get the value in the collection { 0, pi/2, π, 3 pi/2s } respectively.In selector 4,, in these four angles, utilize natural coding angle φ according to following equation ₂(k), φ ₃And φ ₄Produce 64 basic CCK code word c (k)=(c ₀(k), c ₁(k) ..., c ₇(k)):

Phase modulator 5 utilizes different coding angle φ ₁(k) envelope of the basic CCK code word of modulation acquisition is last, determines one of 256 complete CCK code words:

(2)

Utilize multidiameter fading channel 7 (h=(..., 0,0,0.h (0), h (1) ..., h (L-1), 0,0,0 ...)), the code word that convolution 6 sends, then, in adder 8, doping additive white Gaussian background noise.

Shown in Fig. 1 (b), CCK receiver received signal, and following deformation signal sampling effectively is provided:

$r\left(j\right)=\underset{k=0}{\overset{K-1}{\mathrm{\Σ}}}\underset{i=0}{\overset{7}{\mathrm{\Σ}}}{a}_i\left(k\right)h(j-i-8k)+n\left(j\right),j=\mathrm{0,1,2},...\left(3\right)$

At the front end of this receiver, wherein n (f) is variance N ₀The symmetrical compound white Gauss noise of zero average (zero-mean) circle handle.Suppose the channel model according to IEEE 802.11b, the multipath channel coefficient is got exponential decay plural number Gaussian random variable.In addition, suppose and in description of the invention, adopt the quasistatic fading channel that wherein for each transmitted in packets, channel coefficients is fixed, and independently changes for each grouping.

At first, 9 pairs of these received signals of channel matched filter (CMF) are carried out convolution, and this received signal is corresponding to multipath channel impulse response h=time reversal (h* (L-1), the h* (L-2) that produce 8 soft chip value at each CCK mark space, ..., h* (0)) conjugation.In advance, utilize the preposition part of each grouping to estimate the CMF coefficient.As shown in Figure 2, in typical WLAN transmitted in packets, utilize juxtaposed preposition part, head part and net load part, form this packet, wherein preposition part is a sequence known or that detect easily, sends this sequence and helps receiver to carry out detection of packets, carrier wave and time tracking, channel estimating and realize other function.

Get back to Fig. 1 (b), CCK codeword correlator 10 makes soft chip relevant with 64 basic CCK code words of possibility, to produce 64 plural soft metric (complex soft metric), in circulator 11, makes 4 possible phase angles of these 64 plural soft metric rotations, to find the solution φ ₁(k) degree of indeterminacy.Each real part (Re) of 256 decision statistic obtaining is compared, and to determine to produce the code word a (k) of maximum output valve, this maximum output valve is by selector 21 outputs.The codeword decoding that DQPSK decoder 12 and QPSK decoder 13 will be determined is 8, then, and to its descrambling 14, to recover position, 8 source.The DQSK φ that decodes ₁(k) can avoid the 4 phase fuzzy problems relevant with carrier phase recovery.In order to improve the detection performance, can be in CCK be relevant, (EB, energy-bias) elimination 15 or decision feedback equalization technology 16 when the delay expansion of propagation channel is long, can significantly improve performance gain like this to insert energy-bias.

Now, according to one embodiment of present invention, the best DSSS/CCK detector design procedure that adopts the received signal sample sequence r (j) in the equation (3) is described.In this was described, N represented the number of chips in the CCK symbol.For illustrative purposes, specify the wherein situation of N=8, yet those skilled in the art understand that if requirement, N can be another number.Because the multidiameter ratio CCK chip period T under the typical radio lan environment _cLong, and than whole C CK symbol period NT _cShort, therefore, when design CCK detector, can suppose and only utilize 3 symbols that for example, k CCK symbol can be effectively determined in the reception of (k-1), k and (k+1) individual symbol sampling.Therefore, when k symbol detection of research, equation (3) can be rewritten as the sample sequence that blocks that length is 4N-1:

$r^{\left(k\right)}\left(j\right)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{a}_i(k-1)h(j-i-(k-1)N)$

$+\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{a}_i\left(k\right)h(j-i-\mathrm{kN})$

$+\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{a}_i(k+1)h(j-i-(k+1)N)$

$n\left(j\right),$ j＝(k-1)N，(k-1)N+1…，(k+3)N-2 (4)

Note that under above-mentioned supposition situation, when the N of i＜0 or i, h (i) ≈ 0.Although the design of this receiver has for convenience of explanation limited the long channel length for this CCK symbol lengths in this trifle, this design process of equation can expand to the more situation of long channel with direct-passing mode.

A. best single symbol detector

As the first step of detector design, with { a ₁And { a (k-1) } ₁(k+1) } be set to all-zero code sheet sequence temporarily, this means, in detecting processing, both do not had follow-up ISI, ISI goes ahead of the rest again.Note that this supposition guarantees the no ISI condition between the adjacent-symbol, but the ICI between the chip of CCK symbol causes still performance to reduce.Then, at time k, the single symbol detector of maximum likelihood (ML) is selected to be used to maximize m (m0,1,255) of log-likelihood probability and is supposed (hypothetical) symbol a ^[m]:

$\stackrel{\&OverBar;}{\mathrm{\&Lambda;}}(a^{\left[m\right]}=-\frac{1}{{\mathrm{<figure-callout\; id="0"\; label="N"\; filenames="C200380102038E00231.png,C200380102038E00271.png"\; state="\{\{state\}\}">N</figure-callout>}}_0}\underset{j=\mathrm{kN}}{\overset{(k+2)N-2}{\mathrm{\&Sigma;}}}{|r^{\left(k\right)}\left(j\right)-\underset{i=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a_i}^{\left[m\right]}h(j-i-\mathrm{kN})|}^2,---\left(5\right)$

It is equivalent to a ^[m]≡ (a ₀ ^[m], a ₁ ^[m]..., a _N-1 ^[m]), its maximization:

Wherein A},

{ A} and A ^*The conjugation of representing real part, imaginary part and plural A respectively.Now.Note that in i＜0 during i 〉=N, h (i) is 0, when not having in advance ISI or follow-up ISI, we can determine how to realize best canonical detector.About relevant portion (that is, in the equation (6) first), utilize CMF Chip samples sequence { the T that convolution is received ^(k)(kN+j) }, then, N continuous CMF output sampling is relevant with the conjugation of 256 code words.On the contrary, eliminate part (that is, in the equation (6) second), can use looking into of 64 projects, wherein,, can calculate and store each project respectively in the preposition reception period finishing when estimating the CMF coefficient with table about EB.

Note that φ ₁(k) phase uncertainty does not influence the energy bias term in the equation (6).If note that also owing to not occurrence frequency selectivity distortion during the transmission, then the energy of all CCK symbols equates, eliminate so in flat fading or awgn channel, do not need to consider EB.Yet on typical frequency selectivity multipath wireless channel, at receiver front end, the ICI component makes each code word have different signal energies respectively, and therefore, for optimum detection, it is extremely important that EB eliminates (cancellation).

By second of equation (6) handled, can significantly reduce EB and look into assessing the cost with list structure.By the expansion and handle this second EB (m), m=0,1 ..., 63, can obtain:

Wherein

And

${\mathrm{\&rho;}}_a(m;i)\stackrel{\mathrm{\&Delta;}}{=}\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a}_j^{\left[m\right]}{a}_{j-1}^{{\left[m\right]}^{*}},i=-N+1,...,N-1---\left(9\right)$

The aperiodicity coefficient correlation of representing multipath channel and m code word respectively.Can ignore equation (7) second, because for all CCK code words, ρ _a(m; 0) gets same value.(usually, utilize a ^[m], a ^[m+64], a ^[m+128]And a ^[m+192] Represent 4 φ ₁M on duty basic CCK code word (m=0,1 ..., 63) 4 different code words producing).Therefore, eliminate preferential 64 (N-1) CCK of storage in advance codeword coefficients ρ in order to realize EB _a(m; 0), m=0,1 ..., 63, i=1,2 ..., N-1 then, calculates (N-1) channel coefficients ρ _h(i), i=1,2 ..., N-1 during reception is preposition, when finishing the CMF estimation, obtains 64EB value EB (m), m=0, and 1 ..., 63.

In Fig. 1 (b), Fig. 1 (b) shows CMF and has inserted the series connection structure of the CCK correlation-decision of EB arrester, handles according to the optimum signal symbol of equation (6), and it determines the code word of transmission.If desired,, can omit the EB arrester, but cost is to reduce decoding performance slightly in order to simplify realization.

For the realization of the receiver shown in Fig. 1 (b), need to estimate 3 groups of coefficients, that is, and CMF coefficient, DFE coefficient and EB coefficient.Fig. 3 illustrates the process of estimating these coefficients.At first, when receiver utilizes energy measurement or other method to detect packet preamble to arrive (piece 30), receiver makes the received signal relevant (piece 31) of known preamble and input.By to each chip time on a plurality of prime notation (perhaps half-chip time) skew accumulative total correlated results, can determine CMF coefficient { h (i) }, then, export its ( piece 32 and 33).Then, utilize the aperiodicity of CMF coefficient relevant, calculate DFE coefficient { ρ _h(i) }, shown in equation (8).For a plurality of prime notation, relevant by the received signal that makes input with the CMF coefficient of estimation, to each chip time (half-chip time) skew, also can measure DFE coefficient (piece 34).At last, utilize DFE coefficient { ρ _h(i) } 35 with CCK code word coefficient correlation { ρ _h(m; I) } inner product between is calculated the EB coefficient, shown in equation 7 (piece 36 and 37), wherein utilizes m CCK code word { a in the equation 9 in advance _l ^[m]Aperiodicity relevant, calculate { ρ _h(m; I) } (piece 38 and 39).

Fig. 4 illustrates the operation that embeds the correlation-decision of receiver shown in Fig. 1 (b).At first, storage is corresponding to 8 long input sample sequences of the noisy chips of CCK symbol, as the soft estimate (piece 40) of the CCK code word of receiving.Then, make the input sample sequence respectively with 256 CCK code words relevant (inner product) (piece 41), then, corresponding correlated results optionally deducts the energy bias term (piece 42) of each CCK code word.Then, select to produce the hard estimated value (piece 43 and 44) of the CCK code word of maximum output valve as the CCK code word of receiving.

By they being organized as 64 collection with 4 elements of same base CCK code word, can effectively realize 256 kinds of relevant and MAXIMUM SELECTION processing: at first, carry out between input sample and 64 the basic CCK code words 64 relevant, utilize 4 probable values of envelope symbol to take advantage of each correlated results respectively, then, get the real part of multiplication result.Select in every group maximum in 4 real parts as remaining (survivor) of this group, then, deduct corresponding energy-bias.At last, with 64 remaining comparing, then, select to produce of the hard estimation (hard estimate) of the CCK code word of maximum remaining value as the CCK code word of receiving.

B. the follow-up ISI arrester of interpolation

In the many symbol transmission of reality were used, best single symbol detector that the trifle of front is described no longer was best, because reckon without the ISI component between the adjacent-symbol when this detector of design.The follow-up ISI that previous symbol produces and systematic function is reduced the ISI in advance that the arrival symbol produces.By adjusting previous no ISI supposition, this trifle solves follow-up ISI and eliminates problem, so that symbol { a on the horizon _l(k+1) } be all-zero code sheet sequence, with identical in equation (3).In advance the mitigation process of ISI more is difficult to solve the problem in the DSSS/CCK communication, and it is crucial suggestion of the present invention, this mitigation process of explanation separately in the trifle below.

In order to quantize and to handle the relevant follow-up ISI of non-zero of component that obtains, replace r by utilizing equation (4) by the detection in the equation (6) ^(k)(kN+j), launch equation (6) first, wherein, current sign { a is set to all full null sequences _l(k) }, symbol { a at hand _lAnd additive noise n (j) (k+1) }.Then, the channel coefficient correlation { ρ that determines for equation (8) _h(n) }, utilize following formula to represent to launch the result:

In the superincumbent equation, can see, adopt feedback filter and the previous CCK chip sequence that detects

Before the CCK correlator, can eliminate follow-up ISI fully.Fig. 1 (b) illustrates for (perhaps the having eliminated follow-up ISI's) chip that will improve tolerance and delivers to the CCK correlator, from each soft chip value y _i(k) deduct the DFE of corresponding follow-up ISI item:

${\mathrm{\&upsi;}}_i^{\mathrm{past}}\left(k\right)=\left\{\begin{array}{c}\underset{n=i+1}{\overset{N-1}{\mathrm{\&Sigma;}}}{\tilde{a}}_{N+i-n}(k-1){\mathrm{\&rho;}}_h\left(n\right),i=\mathrm{0,1},...,N-2\\ 0,i=N-1\end{array}\right.---\left(11\right)$

$z_i\left(k\right)=y_i\left(k\right)-{\mathrm{\&upsi;}}_i^{\mathrm{past}}\left(k\right),i=\mathrm{0,1},...,N---\left(12\right)$

Fig. 5 illustrates internal structure and the operation of DFE.When sign determination is finished, utilize last N-1 chip at (k-1) $({\tilde{a}}_{N-1}(k-1),{\tilde{a}}_{N-2}(k-1),...,{\tilde{a}}_1(k-1))$ Its coefficient of initialization is set to (ρ _h(1), ρ _h(2) ..., ρ _h(N-1)) the N-1 memory of DFE.Then, in each chip clock, from left to right, make storage chip displacement N time (i=0,1 ..., N-1), output will be from importing soft chip value y _i(k) the corresponding follow-up ISI υ that deducts _i ^Past(k).Utilization is by subtraction z _i(k), i=0,1 ..., the improvement soft metric that N-1 obtains is determined k sign determination.

Fig. 6 summary illustrates follow-up ISI and eliminates process and current C CK codeword estimation process.At first, chip time index l is set to 0 (piece 60), then, the hard estimated value of previous CCK code word is loaded into DFE shown in Figure 3 goes up (piece 61).(hard estimated value and soft estimate about the CCK code word please refer to Fig. 4).Then, subtract the current output (piece 62) of DFE, then, store this result, as i the input sample (piece 63) of correlation-decision corresponding to i input sample of i noise CMF output valve.Then, utilize a sampling, displacement DFE then, presents 0, as the new input sample (piece 64) of DFE.Make chip time index l increase progressively 1 (piece 65), and if l less than 8, then this process is returned 62 (pieces 66).Otherwise the correlation-decision block operation of utilizing Fig. 4 to describe is determined the soft estimate and the hard estimated value of current C CK code word then, to finish this operation.Piece (67).

C. the ISI that goes ahead of the rest time reversal eliminates

As second step of optimal detector design of the present invention, there is not the nothing supposition in advance in the trifle of front, and with all symbol { a _i(k-1) }, { a _i(k) }, { a _i(k+1) } be set to the non-zero chips sequence.Because when determining current sign, can not reliably estimate ISI in advance, so can will make and all possible { a of symbol at hand _i ^[m](k+1): m=0,1 ..., the hypothesis detection method of the decision statistic queuing of 256} association is applied to optimum detection.Yet, suppose the individual decision statistic of detection methods request 65,536 (perhaps, 256 * 256), make them in fact can not carry out the CCK codeword detection.

As a kind of selection, between CMF and CCK correlator, can adopt to be used to suppress in advance the filtering of going ahead of the rest of the suboptimum of ISI.Yet, to introduce filtering in advance and destroy the single symbol detector scheme of best CCK, this scheme must make CMF, CCK correlator and the cascade of EB arrester.In addition, if do not adopt very complicated spectrum factorization method or coefficient adaptive method, filtering causes noise to strengthen usually in advance, and because make the distortion of symmetrical CMF output sample sequence, time tracking (time tracking) performance is reduced.Therefore, traditional ISI mitigation process in advance can not be applied to the packet communication system based on DSSS/CCK, and a kind of new method of our needs, and this method can effectively be eliminated ISI in advance, and does not influence the structure of the single symbol detector of best CCK.

In order to design precursor cancellation scheme, the ISI in advance that the identical mode of mode that the present invention carries out with last trifle quantizes to produce during the k symbol detection.By supposing { a _iAnd { a (k-1) } _i(k) } all be all-zero code sheet sequence and in channel under the situation of not additional AWGN, launch equation (6) first, we have obtained and the relevant component of ISI in advance:

Now, by carefully equation (13) and equation (10) being compared, we find, ISI and follow-up ISI have symmetric relation between mutually in advance, therefore, utilize and carry out the same DFE that uses when follow-up ISI eliminates, also can eliminate the ISI that goes ahead of the rest.More particularly,, and take series processing time reversal, can realize according to the present invention that then ISI eliminates, rather than follow-up ISI eliminates in advance if we load the follow-up ISI DFE of the conjugation of the chip with following symbol.

Fig. 7 illustrates relevant DFE structure and detailed process, wherein symbol time and chip time respectively with the order [K-1 ..., k+1, k, k-1 ..., 0] and [N-1 ..., i+1, i, i-1 ..., 0] order carry out.When finishing (k+1) symbol detection, utilize the symbol of determining

Its coefficient of conjugation initialization of N-1 chip be set to (ρ _h(1), ρ _h(2) ..., ρ _h(N-1)) the N-1 memory of DFE.Then, in each chip clock, from left to right, make storage chip displacement N time (i=N-1, N-2 ..., 0), then, the conjugation of getting corresponding output is as the ISI item of going ahead of the rest:

${\mathrm{\&upsi;}}_i^{\mathrm{pre}}\left(k\right)=\left\{\begin{array}{c}{\left(\underset{n=N-1}{\overset{N-1}{\mathrm{\&Sigma;}}}{\tilde{a}}_{n-(N-1)}(k+1){\mathrm{\&rho;}}_h\left(n\right)\right)}^{*},i=N-1,N-2,...,1\\ 0,i=0\end{array}\right.---\left(14\right)$

From importing soft chip value y _i(k) deduct this follow-up ISI item.Utilization is by subtraction w _i(k), i=N-1, N-2 ..., the 0 improvement soft metric that obtains is by time reversal, and it is fed to the CCK correlator, to determine k sign determination.

EB eliminates and follow-up ISI eliminates although attempted to carry out in tradition (legacy) wlan system, and for DSSS/CCK radio communication context, only inserting in advance in the present invention, ISI eliminates.

Fig. 8 summarizes the process that ISI eliminates and previous CCK code word is estimated in advance that illustrates.At first, chip time index i is set to predetermined value, and for example, 8 (pieces 80) then, are loaded into DFE shown in Figure 7 (piece 81) with the conjugation of the hard estimated value of current C CK code word.(hard estimated value and soft estimate about the CCK code word please refer to Fig. 4).Then, make chip time index i 1 (piece 82) that successively decrease.Then, subtract the current output of DFE from the i input sample, this i input sample will be stored this result, as the i input sample (piece 84) of correlation-decision corresponding to the noisy chips (piece 83) of the soft estimate of previous CCK code word.

Continue sampling of DFE displacement, then, present 0, as the new input sample (piece 85) of DFE.If i is greater than 0, then this process is returned piece 82 (piece 86).Otherwise, utilize the operation of correlation-decision shown in Figure 4, determine the improvement soft estimate and the hard estimated value of previous CCK code word, then, finish this process (piece 87).In this process, note that before correlation-decision block operation, need carry out the chip time reversal of 8 long input sample sequences.

D. bidirectional turbo ISI canceller

Up to the present, we to the structure according to best DSSS/CCK detector of the present invention, that is, all component models with best single symbol detector of EB arrester, follow-up ISI arrester and the ISI arrester of going ahead of the rest time reversal are studied.Explanation now can be synthesized whole system effectively to utilize the mode of all component models.When synthesizing these parts, utilize ISI removing method and iteration (perhaps the spy broadcasts) signal processing in advance based on tentative judgement, can find integrated solution.

Fig. 9 is based on the piece figure of the DSSS/CCK detector of BTIC.At time k, the follow-up ISI value (υ that utilizes follow-up ISI DFE 90 to produce in the equation (11) ₀ ^Past(k), υ ₁ ^Past(k) ..., υ _N-1 ^Past(k)), then, in subtracter 91, utilize CMF output (y ₀(k), y ₁(k) ..., y _N-1(k)) subtract it, to produce soft metric (z ₀(k), z ₁(k) ..., z _N-1(k)) (with reference to figure 5).Soft metric is delivered to the CCK correlation-decision 92 shown in Fig. 1 (b), these CCK correlation-decision 92 tentative definite k CCK code words $({\tilde{a}}_0\left(k\right),{\tilde{a}}_1\left(k\right),...,{\tilde{a}}_{N-1}\left(k\right))$ 93。Then, the conjugation of tentative codeword chips is stored into the ISI value (υ in advance of (k-1) CCK symbol _N-1 ^Pre(k-1), υ _N-2 ^Pret(k-1) ..., υ ₀ ^Pre(k-1)) (with reference to figure 7).At last, in subtracter 95, make soft metric (z time reversal in time k-1 storage _N-1(k-1), z _N-2(k-1) ..., z ₀(k-1)) subtract ISI value in advance, to produce sequence time reversal of improving soft metric:

$u_i(k-1)=z_i(k-1)-{\mathrm{\&upsi;}}_1^{\mathrm{pre}}(k-1),i=N-1,N-2,...,0.---\left(15\right)$

Then, at piece 96, make tolerance sequence (u _N-1(k-1), u _N-2(k-1) ..., u ₀(k-1)) time reversal, then, it is delivered to the CCK correlation-decision once more, produce (k-1) individual improvement (refined) CCK code word $({\hat{a}}_0(k-1),{\hat{a}}_1(k-1),...,{\hat{a}}_{N-1}(k-1)).$ Note that and improve soft metric sequence ISI and follow-up ISI in advance, postpone but cost is a symbol time, unless tentative judgement is wrong.(with reference to equation (12) and equation (15)).

In order to improve the detection performance, have the follow-up ISI DFE that improves the CCK codeword chips by reloading, eliminate by restarting follow-up ISI, then, restart ISI elimination in advance, in each symbol detection time, iteration entire process.After finishing the iteration of pre-determined number, with the ultimate sequence (z of soft metric at time k ₀(k), z ₁(k) ..., z _N-1And tentative decision codeword chips (k)) $({\tilde{a}}_0\left(k\right),{\tilde{a}}_1\left(k\right),...,{\tilde{a}}_{N-1}\left(k\right))$ Store in the memory, for using when the time k+1.Proceed whole spy and broadcast processing, up to all net load CCK symbols are decoded.

Figure 10 summarizes the operation that the BTIC between estimation current C CK code word and the previous CCK code word is shown.At first, by the payload signal of reception and the correlation between the CMF, obtain 8 noisy chips (piece 100) corresponding to current C CK code word.Utilize the DFE output of the hard estimated value of previous CCK code word,, from the noisy chips sequence, eliminate follow-up ISI (piece 110) by process shown in Figure 6.Store this result, hard estimated value and soft estimate as current C CK code word it would be desirable, this current CCK code word does not have follow-up ISI (piece 120).

Utilization by process shown in Figure 8, is eliminated ISI (piece 130,140,150) in advance in the DFE of chip hard estimated value time reversal of the 120 current C CK code words that obtain output from the soft estimate of previous CCK code word.Store this result, as hard estimated value of the improvement of previous CCK code word and soft estimate, it would be desirable, this previous CCK code word had not both had follow-up ISI, and ISI (piece 160) does not go ahead of the rest again.

If number of iterations equals predetermined value (piece 170), then, previous CCK code word is carried out final decision (piece 180) by being taken at the hard estimated value of the previous CCK code word that piece 120-160 obtains.Then, the hard estimated value of previous code word and soft estimate are set to current C CK code word (piece 185).Otherwise, utilize improved hard estimated value to upgrade the hard estimated value of previous CCK code word, then, this process proceeds to piece 200.

At last, make CCK symbol time index k increase progressively 1, then, the hard estimated value of previous CCK code word and soft estimate are set to the hard estimated value and the soft estimate of current C CK code word, and this is the preliminary step that next CCK code word is judged.

According to top description, other modifications and variations of the present invention understand it is conspicuous for those skilled in the art.Therefore, although only understand specific embodiment of the present invention specifically at this,, obviously, under the situation that does not break away from essential scope of the present invention, can carry out various modifications to it.

Claims (22)

1, a kind of method that is used for reducing at receiver distorted signals comprises:

Obtain chip sequence from the signal that receives;

According to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word, produce interference eliminated item between follow symbol;

From chip sequence, eliminate between follow symbol and disturb, to produce chip tolerance;

According to described chip tolerance, determine current complementary code keying code word;

According to chip estimated value time reversal of current complementary code keying code word, produce intersymbol interference in advance and eliminate item; And

According to chip estimated value time reversal of current complementary code keying code word, from previous complementary code keying code word, eliminate intersymbol interference in advance.

2, method according to claim 1 wherein obtains chip sequence and comprises:

Utilize the signal of the coefficient convolution reception of channel matched filter.

3, method according to claim 1, wherein eliminate between follow symbol to disturb and comprise:

According to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word, produce interference eliminated item between follow symbol; And

Chip sequence subtracts interference eliminated item between follow symbol, to produce described chip tolerance.

4, method according to claim 1, wherein eliminate between follow symbol to disturb and comprise:

Complementary code keying chip sequence according to previous detection is provided with the decision zeedback equalizer coefficient;

By in each chip clock,, produce distracter between follow symbol with decision zeedback equalizer coefficient displacement pre-determined number;

Chip sequence subtracts distracter between follow symbol, to produce described chip tolerance.

5, method according to claim 1 wherein by described chip tolerance is input to the complementary code keying correlator, produces current complementary code keying code word.

6, method according to claim 1, wherein eliminate intersymbol interference in advance and comprise:

Calculate the conjugation of the chip value of current complementary code keying code word;

According to this conjugation the decision zeedback equalizer coefficient is set;

By in each chip clock,, produce intersymbol interference item in advance with decision zeedback equalizer coefficient displacement pre-determined number; And

From chip tolerance, deduct intersymbol interference item in advance corresponding to previous complementary code keying code word.

7, method according to claim 1, wherein received signal is the signal that produces in direct sequence spread spectrum/complementary code keying wireless communication system.

8, method according to claim 1, this method further comprises:

Equilibrium is used to produce the interior signal energy of codeword correlator bank of current complementary code keying code word and previous complementary code keying code word.

9, method according to claim 1, this method further comprises:

(a) obtain to eliminate the improved previous complementary code keying code word that produces after the intersymbol interference in advance from previous complementary code keying code word;

(b) make previous complementary code keying code word equal improved previous complementary code keying code word; And

(c), carry out interference eliminated and intersymbol interference elimination in advance between follow symbol according to the previous complementary code keying code word that obtains at (b).

10, method according to claim 9, this method further comprises:

Repeating step (a) one (c) pre-determined number.

11, a kind of system that is used for reducing distorted signals on receiver comprises:

Channel matched filter is used for producing chip sequence according to the signal that receives;

Decision zeedback equalizer is used for producing interference eliminated item between follow symbol according to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word, and eliminates between follow symbol from chip sequence and disturb, to produce chip tolerance; And

The complementary code keying correlation-decision, be used for according to described chip tolerance, produce current complementary code keying code word, wherein according to the conjugate of the chip value of next symbol, decision zeedback equalizer produces intersymbol interference in advance and eliminates item, and according to chip estimated value time reversal of current complementary code keying code word, decision zeedback equalizer is eliminated intersymbol interference in advance from previous complementary code keying code word.

12, system according to claim 11, wherein by producing interference eliminated item between follow symbol according to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word, and subtract between follow symbol the interference correction item by chip sequence and produce described chip tolerance, decision zeedback equalizer is eliminated between follow symbol and is disturbed.

13, system according to claim 11 wherein passes through: according to previous detection complementary code keying chip sequence, the decision zeedback equalizer coefficient is set; Make decision zeedback equalizer coefficient displacement pre-determined number in each chip clock, produce distracter between follow symbol; And subtract distracter between this follow symbol by chip sequence, and producing described chip tolerance, decision zeedback equalizer is eliminated between follow symbol and is disturbed.

14, system according to claim 11 wherein passes through: the conjugation of calculating the chip value of following symbol; According to this conjugation the decision zeedback equalizer coefficient is set; By in each chip clock,, produce intersymbol interference item in advance with decision zeedback equalizer coefficient displacement pre-determined number; And subtracting intersymbol interference item in advance corresponding to the chip tolerance of previous complementary code keying code word, decision zeedback equalizer is eliminated intersymbol interference in advance.

15, system according to claim 11, wherein receiver is direct sequence spread spectrum/complementary code keying wireless communication receiver.

16, system according to claim 11, this system further comprises:

The energy-bias arrester is used for the signal energy in the balanced codeword correlator bank.

17, a kind of two-way spy broadcasts the intersymbol interference arrester, comprising:

Single symbol detector is used for producing chip sequence according to received signal;

Interference eliminator between follow symbol is used for producing interference eliminated item between follow symbol according to the previous detection chip sequence that is used to form previous complementary code keying code word, and disturbs between chip sequence elimination follow symbol, to produce chip tolerance; And

The intersymbol interference arrester is used for producing intersymbol interference in advance and eliminating item, to eliminate intersymbol interference in advance from previous complementary code keying code word according to utilizing described chip to measure chip estimated value time reversal of the current complementary code keying code word that produces in advance.

18, two-way spy according to claim 17 broadcasts the intersymbol interference arrester, and wherein single symbol detector comprises RAKE receiver.

19, two-way spy according to claim 17 broadcasts the intersymbol interference arrester, comprising:

Channel matched filter is used for producing chip sequence according to received signal; And

Codeword correlator bank is used for producing current complementary code keying code word according to described chip tolerance.

20, two-way spy according to claim 19 broadcasts the intersymbol interference arrester, and wherein single symbol detector further comprises the energy-bias arrester, with the signal energy in the balanced codeword correlator bank.

21, a kind of receiver comprises:

Decision zeedback equalizer is used to produce the decision zeedback equalizer coefficient set;

The first feedback arrester is used to eliminate between the follow symbol that formerly symbol produces and disturbs;

The second feedback arrester, be used to eliminate the intersymbol interference in advance that tail symbol produces, wherein the first feedback arrester and the second feedback arrester use the decision zeedback equalizer coefficient set that is produced according to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word by decision zeedback equalizer respectively, and the decision zeedback equalizer coefficient set that produces according to the conjugate of the chip value of next symbol by decision zeedback equalizer, the described decision zeedback equalizer coefficient set that produces according to the previous detection complementary code keying chip sequence that is used to form previous complementary code keying code word by decision zeedback equalizer and disturbed between follow symbol and intersymbol interference in advance to eliminate by time reversal according to the decision zeedback equalizer coefficient set that the conjugate of the chip value of next symbol produces by decision zeedback equalizer.

22, receiver according to claim 21, wherein the first feedback arrester and the second feedback arrester are included at least one decision zeedback equalizer.

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