CN100524829C - Method and structure for operating memory device on control gate edge - Google Patents

Abstract

The charge trapping memory device and method of the present invention utilize edge-induced effects to increase the second bit operation window. The edge-induced effect occurs in the region under the word line such that when hole injection is used for the memory device, hole charges are stored in the charge trapping layer, which is orthogonal to the word line, and are stored along the edge of the word line. In one embodiment, the virtual ground array includes a charge trapping layer disposed between two dielectric layers such that there is no charge trapping layer over the source and drain regions. After hole injection is applied to the virtual ground array, hole charges are stored along the edge of each word line because the electric field is larger at the edge of the word line compared to the non-edge portion.

Description

Method and structure for operating a memory device on a control gate edge

related application

This application claims priority to U.S. Provisional Patent Application No. 60/805,448, the filing date of which is 2006/6/21, the inventor is Chao-I Wu, and the title of the invention is "Method and Structure for Operating Memory Devices on Fringes of Control Gate ".

technical field

The present invention relates generally to electrically programmable and erasable memories, and more particularly to methods and apparatus for increasing memory operation intervals and reducing second-bit effects in multi-bit operations of cells.

Background technique

Electrically programmable and erasable non-volatile memory technologies based on charge storage structures, known as electrically erasable programmable read-only memory (EEPROM) and flash memory, are used in many current applications. The design of flash memory is based on an array of memory cells that can be independently programmed and read. Sense amplifiers in flash memory are used to determine data values, or values stored in non-volatile memory. In a typical sensing mechanism, the current through the memory cell is sensed and compared to a reference current in a current sense amplifier.

Various memory cell structures are used in EEPROM and flash memory. As the volume of integrated circuits shrinks, the research energy in this field is gradually focused on the memory cell structure based on the charge trapping dielectric layer, because its process can be reduced in size and relatively simple. The memory cell structure based on the charge trapping dielectric layer includes a structure called "N-bit memory". The memory cell structure stores data by trapping charges in a charge trapping dielectric layer, such as silicon nitride. After the negative charge is trapped, the threshold voltage of the memory cell will rise. The threshold voltage of the memory cell is lowered by removing negative charges from the charge trapping layer.

NROM devices use a relatively thick base oxide, greater than, for example, 3 nanometers thick, typically between about 5 and 9 nanometers, to avoid charge loss. The technique used to erase cells is not direct tunneling, but band-to-band tunneling-induced hot hole injection (BTBTHH). However, hot hole injection causes damage to the oxide, leading to charge loss in high-threshold-voltage cells and charge accumulation in low-threshold-voltage cells. During the programming and erasing cycles, the erasing time must be gradually increased, because the charge in the charge trapping structure will gradually accumulate and be difficult to erase. Charge accumulation occurs because the hole injection point and the electron injection point do not overlap each other, so some electrons remain after the erase pulse. In addition, after the block erase operation of the N-bit memory, the erase speed of each cell will be different due to process variation (eg, channel length difference). The difference in erase speed will result in a large _Vt distribution in the erased state, making some cells hard to erase and some cells over erased. Therefore, the target threshold voltage interval (Vtwindow) is closed after each program and erase cycle, resulting in poor endurance. This phenomenon will become more serious as process technology continues to be miniaturized.

In conventional floating gate devices, one bit of charge is stored in a conductive floating gate. The invention of the NROM cell provides a two-bit flash cell that stores charge in an oxide-nitride-oxide (ONO) dielectric layer. In a typical structure of an NROM memory, a nitride layer is used as a trapping material and is disposed between a top oxide layer and a bottom oxide layer. In the nitride layer of the ONO structure, charges can be trapped on the left or right side of the NROM cell. The "secondary effect" affects the operating range and thus becomes a problem. The second bit effect is caused by the interaction of left and right bits. Therefore, it would be desirable to provide a method and apparatus that can increase the storage operating range of a charge trapping memory, thereby greatly reducing the second bit effect.

Contents of the invention

The charge trapping memory device and method increase the operation range of the second bit through the edge-induced effect. The marginal induction effect occurs in the area under the word line, so that when the hole injection method is applied to the memory device, the hole charge is stored in the charge trapping layer, which is orthogonal to the word line, and the hole charge is along the word line. edge storage. In a first embodiment of the charge trapping memory, the virtual ground array includes a charge trapping layer disposed between two dielectric layers such that there is no charge trapping layer above the source and drain regions. After hole injection is applied to the virtual ground array, hole charges are stored along the edge of each word line because the electric field is larger at the edge of the word line compared to the non-edge portion. The hole charge along the edge will cause the threshold voltage Vt of the channel to decrease. Typical device operation of virtual memory arrays is governed by low threshold voltages. In a second embodiment of the charge trapping memory, the virtual ground array includes a charge trapping layer extending above the source and drain regions. Additional hole charges are injected into the charge trapping layer extending over the source and drain regions.

In a third embodiment of the charge trapping memory, the virtual ground array includes a charge trapping layer disposed between two dielectric layers such that there is no charge trapping layer above the source and drain regions. The virtual ground array includes a plurality of word lines, wherein each word line includes two edges and a non-edge portion between the two edges. Each word line has two threshold voltages, the first threshold voltage (Vt _fringe ) is related to the two edges of the word line, and the second threshold voltage (Vt _non-fringe ) is related to the non-edge portion of the word line. The edge threshold voltage Vt _fringe is typically lower than Vt _non-fringe . In a fourth embodiment of the charge trapping memory, the virtual ground array includes a charge trapping layer extending above the source and drain regions. Additional hole charge injection into the charge trapping layer is injected into the charge trapping layer extending over the source and drain regions. Similarly, each word line has two threshold voltages, the first threshold voltage (Vt _fringe ) is related to the two edges of the word line, and the second threshold voltage (Vt _non-fringe ) is related to the non-edge portion of the word line. The edge threshold voltage Vt _fringe is typically lower than Vt _non-fringe .

Broadly speaking, a memory device includes a substrate, a charge trapping structure on the substrate (the charge trapping structure extends along a first direction), and a gate extending along a second direction and perpendicular to the charge trapping layer, the gate having The bottom surface is defined by a first edge and a non-edge portion, the first edge is separated from the second edge, and the non-edge portion is located between the first edge and the second edge. The non-edge portion has a first critical voltage, the first and second edges have a second critical voltage, and the second critical voltage value is lower than the first critical voltage value, wherein holes are moved to the charge trapping layer by hole injection, and are located at The grid is arranged under the gate and along the first and second edges.

The present invention describes a way to increase the storage operating interval in a single cell dual bit memory with the first hole injection method, which applies a positive gate voltage +Vg to erase the memory cell to a negative voltage level. The present invention also describes a way to increase the storage operating interval in a single cell dual-bit memory with the first hole injection method, which applies a negative gate voltage -Vg to erase the charge trapping memory to a negative voltage level. Alternatively, the charge trapping memory is erased such that its voltage level is lower than the initial threshold voltage level (Vt(i)). Both methods of charge trapping memory, either erasing to a negative voltage level, or erasing to a level below the initial threshold voltage, can be used prior to the programming step (i.e., a pre-program erase operation), Or after a programming step (ie, a post program erase operation).

In the following three embodiments of the present invention, two kinds of erasing operations are exemplified. The two erase operations include a hole injection erase operation and a hot hole erase operation. In a first embodiment, the charge trapping memory is erased using hole injection, which is erased using positive voltage hole tunneling. In a second embodiment, the charge trapping memory is erased using hole injection, which is erased using negative voltage hole tunneling. In a third embodiment, the charge trapping memory is erased using a bring-to-hot hole operation. A programming technique suitable for the erase operation of the charge trapping memory described above includes channel hot electrons (CHE).

The method of the present invention is applicable to a variety of charge trapping structure memory devices, including but not limited to, including those having a nitride-oxide structure, an oxide nitride oxide structure, a nitride oxide nitride oxide structure, and an oxide nitride structure. A storage device with a compound oxide nitride oxide structure. For example, in an MNOS memory device, the charge trapping layer is located on the dielectric layer, and there is no dielectric layer on the charge trapping layer. Instead, a polysilicon layer is formed over the charge trapping layer. The nitride oxide structure, which does not include a dielectric layer, allows holes to be injected directly from the polysilicon layer into the charge trapping layer.

Preferably, the present invention increases programming and erasing efficiency in charge trapping memory devices. In addition, the present invention expands the size of the second bit operation interval.

The structure and method of the present invention are described in detail below. The description of the invention is not intended to define the invention, but rather is defined by the claims. Other embodiments, features, viewpoints and advantages of the present invention will be more apparent with reference to the following description, claims and drawings.

Description of drawings

1 is a structural diagram showing a charge trapping memory cell according to a first embodiment of the present invention, which includes a nitride-oxide charge storage structure without a top dielectric layer, thereby illustrating erasure caused by a hole injection method. operation, which injects holes from the gate terminal;

2 is a structural schematic diagram showing a charge trapping memory including an ONO charge trapping structure and a selected top dielectric layer to allow hole injection from the gate terminal in a second embodiment of the present invention;

3 is a structural schematic diagram, which shows a charge trapping memory unit including an ON charge trapping structure but not including a bottom dielectric layer in a third embodiment of the present invention, so as to allow hole injection from the substrate;

4 is a structural schematic diagram showing a charge trapping memory including an ONO charge trapping structure and having a selected bottom dielectric layer to allow hole injection from the substrate according to a fourth embodiment of the present invention;

Fig. 5A is a structural schematic diagram, which shows the top view of the virtual ground array of the first embodiment of the present invention before the hole charge injection method, which is applied in MONS memory; Fig. 5B is a perspective view showing the virtual ground array in the X1 direction Figure 5, which does not have a charge trapping layer above the source and drain junctions; FIG. 5C is a perspective view showing the virtual ground array in the Y1 direction, which has a charge trapping layer on the edge of the word line;

Fig. 6A is a structural schematic diagram showing the result of the virtual ground array of the first embodiment after hole charge injection; Fig. 6B is a perspective view in the X2 direction showing that the charges of the virtual ground array are stored in the charge trapping layer; Fig. 6C is a perspective view showing the virtual ground array of the present invention in the Y2 direction, wherein there is a charge trapping layer on the edge of the word line;

7A is a top view showing the virtual ground array of the second embodiment of the present invention before hole charge injection is implemented in the MNOS memory; FIG. There is a charge trapping layer on the drain junction; FIG. 7C is a perspective view showing the virtual ground array of the present invention in the Y1 direction, which has a charge trapping layer on the edge of the word line;

Fig. 8A is a top view of the dummy ground array according to the second embodiment of the present invention after hole charge injection has been performed; Fig. 8B is a perspective view along the X2 direction of the dummy array of the present invention, wherein the hole charges are stored in the charge trapping layer Middle; FIG. 8C is a schematic diagram showing the virtual ground array of the present invention along the Y2 direction, wherein the charge trapping layer is located above the edge of the word line;

9 is a schematic structural diagram showing a virtual ground array according to a third embodiment of the present invention, before implementing hole charge injection on the MNOS memory as the asymmetric threshold voltage level of the word line;

FIG. 10 is a structural schematic diagram showing a virtual ground array according to a fourth embodiment of the present invention, before implementing hole charge injection on the MNOS memory as the asymmetric threshold voltage level of the word line;

Fig. 11A is a schematic diagram of the structure, which shows the programming of the left bit in the MNOS structure; Fig. 11B is a corresponding graph of the single-unit double-bit operation interval, which illustrates the second bit effect of the right bit;

FIG. 12 is an exemplary graph illustrating an edge-induced operation of a second bit interval after hole injection.

Detailed ways

The structural embodiments and methods of the present invention will be described below with reference to FIGS. 1-12 . It is to be understood that the invention is not limited to the disclosed embodiments, but that other features, elements, methods and forms can be used to practice the invention. Similar elements in different embodiments are generally designated with similar reference numerals.

FIG. 1 shows a first embodiment of a charge trapping memory cell 100 comprising a nitride-oxide (NO) charge trapping structure 120 without a top dielectric layer. Erase operation by injecting holes. The charge trapping memory unit 100 includes a p-type substrate 110 , and a source region 112 is separated from a drain region 114 with a channel 116 therebetween. The term "hole injection" may also be referred to as "hole tunneling". The nitride-oxide trapping structure 120 has a charge trapping layer on a dielectric layer 122 , and the dielectric layer 122 is on the p-type substrate 110 . In this embodiment, the NO charge trapping structure 120 does not have a top oxide structure. Gate 130 is located over charge trapping layer 124 in charge trapping structure 120 . A variety of materials can be used to form the gate 130, including n-type polysilicon, p-type polysilicon, and metal.

In this embodiment, a positive gate voltage +Vg 160 is applied to the gate 130 to erase the charge trapping memory cell 100 to a negative voltage level, or to a level below the initial threshold voltage, to A large memory operation interval is achieved in the charge trapping memory cell 100 having a left memory storage side 124 - 1 on the left of the charge trapping layer 124 and a right memory storage side 124 - r on the right of the charge trapping layer 124 . The erasing method can be performed before the programming step (ie, pre-program erase operation), or after the programming step (ie, post-program erase operation).

When a high bias voltage is applied to the gate terminal of the gate 130 , holes 170 are injected from the gate terminal (as indicated by arrows 150 a , 150 b ) into the charge trapping layer 124 . As exemplary voltage levels, gate voltage Vg 160 applies a positive voltage of 16 volts, while drain voltage Vd 162 of 0 volts, source voltage Vs 164 of 0 volts, and substrate voltage Vsub 166 of 0 volts are applied. The combination of these voltages will perform hole tunneling and erasing on the charge-trapping memory cell 100 , thereby lowering its threshold voltage to a negative value (-Vt), thereby increasing the memory operation interval and reducing the second bit effect.

The NO charge trapping structure 120 in the charge trapping memory unit 100 is designed in a schematic manner. The charge-trapping memory cell 100 includes an NO charge-trapping memory structure 120 that does not have a top oxide, thereby allowing holes to directly enter the charge-trapping structure 120 without the presence of a top oxide. The NO charge trapping structure 120 in the charge trapping memory cell 100 can be used in a memory such as metal oxide nitride oxide semiconductor (MNOS) or silicon nitride oxide semiconductor (SNOS). Other combinations of charge trapping structures, such as Oxide Nitride Oxide (ONO), or Oxide Nitride Oxide Nitride Oxide (ONONO) stacks, etc., can also be used in the present invention without departing from the spirit of the present invention .

2 is a structural schematic diagram showing a second embodiment of a charge trapping memory 200 comprising an oxide-nitride-oxide (ONO) charge trapping structure 220 with a top dielectric layer selected to allow access from the gate terminal inject holes. The charge trapping memory unit 200 includes a p-type substrate 210 including a source region 212 and a drain region 214 separated by a channel 216 . The ONO charge trapping structure 220 has a top dielectric layer 226 on the charge trapping layer 224 , and the charge trapping layer is on the bottom dielectric layer 222 , and the bottom dielectric layer 222 is disposed on the p-type substrate 210 . The gate 230 is located on the top dielectric layer 226 of the charge trapping structure 220 . Various materials can be used for the gate 230, including n-type polysilicon, p-type polysilicon, and metal.

In this embodiment, a positive gate voltage +Vg 260 is applied to the gate 230 to erase the charge trapping memory cell 200 to a negative voltage level, or to a level below the initial threshold voltage, to store the charge A large storage operation interval is generated in the capture storage unit 200 . The memory cell 200 has a left memory storage side 224 - 1 on the left of the charge trapping layer 224 and a right memory storage side 224 - r on the right of the charge trapping layer 224 . This erase method can be performed before the programming step (ie, a pre-program erase operation), or after the programming step (ie, a post-program erase operation).

When a high bias voltage is applied to the gate terminal of the gate 230, holes 270 are injected from the gate terminal into the charge trapping layer 224, as indicated by arrows 250a, 250b. The thickness of the top dielectric layer 226 can be made thin enough to allow holes to tunnel through the top dielectric layer 226 . As exemplary voltage levels, the gate voltage Vg 260 applies a positive voltage of 16 volts, while the drain voltage Vd 262 of 0 volts, the source voltage Vs 264 of 0 volts, and the substrate voltage Vsub 266 of 0 volts are applied. The combination of these voltages will perform hole tunneling and erasing on the charge-trapping memory cell 200 , thereby lowering its threshold voltage to a negative value (-Vt), thus increasing the memory operation interval and reducing the second bit effect.

The ONO charge trapping structure 220 in the charge trapping memory unit 200 is designed as shown in the drawing. The ONO charge trapping structure 220 in the charge trapping memory unit 200 can be used in memories such as metal oxide nitride oxide semiconductor (MONOS) or silicon oxynitride semiconductor (SONOS). Other combined charge trapping structures, such as oxide Nitride Oxide Nitride Oxide Oxide (ONONO) stacks, etc., can also be used in the present invention without departing from the spirit of the present invention.

3 is a structural schematic diagram showing a third embodiment of a charge trapping memory cell 300, which includes an oxide nitride (ON) charge trapping structure 320 without an underlying dielectric layer to allow hole injection from the substrate. The charge trapping memory unit 300 includes a p-type substrate 310 including a source region 312 and a drain region 314 separated by a channel 316 . The NO charge trapping structure 320 includes a dielectric layer 324 on the charge trapping layer 322 , and the charge trapping layer is on the p-type substrate 310 . The ON charge trapping structure 320 has a bottom dielectric layer in this embodiment. The gate 330 is located on the charge trapping layer 322 in the charge trapping structure 320 . A variety of different materials can be used for the gate 330, including n-polysilicon, p-type polysilicon, and metal.

In this embodiment, a negative gate voltage -Vg 360 is applied to the gate 330 to erase the charge trapping memory cell 300 to a negative voltage level, or to a level lower than the initial threshold voltage, to store the charge A large storage operation interval is generated in the capture storage unit 300 . The memory cell 300 has a left memory storage side 322 - 1 on the left of the charge trapping layer 322 and a right memory storage side 322 - r on the right of the charge trapping layer 322 . This erase method can be performed before the programming step (ie, a pre-program erase operation), or after the programming step (ie, a post-program erase operation).

When a high bias voltage is applied to the gate terminal of the gate 330, holes 370 are injected from the substrate into the charge trapping layer 322, as indicated by arrows 350a, 350b. As an exemplary voltage level, a gate voltage -Vg 360 is applied with a positive voltage of -16 volts, while a drain voltage Vd 362 of 0 volts, a source voltage Vs 364 of 0 volts, and a substrate voltage Vsub 366 of 0 volts are applied. The combination of these voltages will perform hole tunneling and erasing on the charge-trapping memory cell 300, thereby lowering its threshold voltage to a negative value (-Vt), thus increasing the memory operation interval and reducing the second bit effect.

The ON charge trapping structure 320 in the charge trapping memory unit 300 is designed as shown in the figure. The ON charge trapping structure 320 in the charge trapping memory unit 300 does not have a bottom dielectric layer, allowing holes to directly enter the charge trapping structure 320 without being blocked by the bottom oxide. The ON charge trapping structure in the charge trapping memory cell 300 can be used in memory such as metal oxide nitride semiconductor (MONS) or silicon nitride oxide semiconductor (SNOS). Other combinations of charge trapping structures, such as ONO structure, or oxide nitride oxide nitride oxide (ONONO) stacking, etc., can also be used in the present invention without departing from the spirit of the present invention.

FIG. 4 shows a fourth embodiment of a charge trapping memory cell 400 comprising an ONO charge trapping structure 420 with a bottom dielectric layer selected to allow hole injection from the substrate. The charge trapping memory unit 400 includes a p-type substrate 410 including a source region 412 and a drain region 414 separated by a channel 416 . The ONO charge trapping structure 420 on the p-type substrate has a top dielectric layer 424 on the charge trapping layer 422 , and the charge trapping layer is on the bottom dielectric layer 426 . The gate 430 is located on the top dielectric layer 424 of the charge trapping structure 420 . Various materials can be used for the gate 430, including n-type polysilicon, p-type polysilicon, and metal.

In this embodiment, a negative gate voltage -Vg 460 is applied to the gate 430 to erase the charge trapping memory cell 400 to a negative voltage level, or to a level lower than the initial threshold voltage, to store the charge A large storage operation interval is generated in the capture storage unit 300 . The memory cell 300 has a left memory storage side 422 - 1 on the left of the charge trapping layer 422 and a right memory storage side 422 - r on the right of the charge trapping layer 422 . This erase method can be performed before the programming step (ie, a pre-program erase operation), or after the programming step (ie, a post-program erase operation).

When a high bias voltage is applied to the gate terminal of the gate 430, holes 470 are injected from the substrate into the charge trapping layer 422, as indicated by arrows 450a, 450b. The thickness of the bottom dielectric layer 426 can be made thin enough to allow hole tunneling through the bottom dielectric layer 426 . As an exemplary voltage level, a negative voltage of -16 volts is applied to the gate voltage -Vg 460, while a drain voltage Vd 462 of 0 volts, a source voltage Vs 464 of 0 volts, and a substrate voltage Vsub 466 of 0 volts are applied . The combination of these voltages will perform hole tunneling and erasing on the charge-trapping memory cell 400, thereby lowering its threshold voltage to a negative value (-Vt), thus increasing the memory operation interval and reducing the second bit effect.

The ONO charge trapping structure 420 in the charge trapping memory unit 400 is designed as shown in the drawing. The ONO charge trapping structure 420 in the charge trapping memory unit 400 can be used in a memory such as a metal oxide nitride oxide semiconductor (MONOS) or a silicon oxynitride semiconductor (SONOS).

Other combined charge trapping structures, such as oxide nitride oxide nitride oxide (ONONO) stacks, etc., can also be used in the present invention without departing from the spirit of the present invention. Representative materials for the dielectric layers 122, 222, 226, 324, 424, 426 include silicon dioxide and silicon oxynitride with a thickness of about 5 to 10 nanometers, although other similar high dielectric constant materials can also be used, such as alumina. Representative materials for the bottom dielectric layer include silicon dioxide and silicon oxynitride with a thickness between 3 and 10 nm, and other similar high dielectric constant materials can also be used. Representative materials for charge trapping structures include silicon nitride with a thickness between 3 and 30 nm, and other high dielectric constant materials including metal oxides such as aluminum oxide, hafnium oxide, and cerium oxide can also be used. The charge trapping structure can be a discrete set of capsules or particles of charge trapping material, or a continuous layer as shown. The charge trapping structure 120 can trap charges such as electrons or holes.

FIG. 5A shows a top view of the virtual ground array 500 of the first embodiment before the hole charge injection method is implemented in the MNOS memory. The virtual ground array 500 includes a plurality of horizontally extending word lines (gates) WL1 510, WL2 512 and WL3 514, as indicated by arrow X1 502. The width of each of WL1 510, WL2 512 and WL3 514 is indicated by reference Wg 518. The virtual ground array 500 also includes a plurality of bit lines BL1 520, BL2 522, and BL3 524, and has a first charge trapping part 521 between the bit lines BL1 520, BL2 522, and has a first charge trapping part 521 between the bit lines BL2 522, BL3 524. The second charge trapping portion 523, the two portions extend along the vertical direction, as indicated by the arrow Y1 504. The length of each charge trapping portion 521, 523 is indicated by the reference Lg 529. The first charge trapping portion 521 and the second charge trapping portion 523 are part of the charge trapping layer. At the intersection of the first charge trapping part 521 and the first, second and third word lines WL1 510, WL2 512 and WL3 514, there is a first dielectric strip 525 and a second dielectric strip 526 extending vertically in the first charge trapping part 521 on both sides. At the intersection of the second charge part 523 and the first, second and third word lines WL1 510, WL2 512 and WL3 514, there is a third dielectric strip 527 and a fourth dielectric strip 528 extending perpendicularly to the second charge trapping part 523 on both sides.

The first word line WL1 510 has a first edge 530, a second edge 532, and a non-edge area 531. In the embodiment of the present invention, the non-edge area 531 is indicated as a position away from the first edge 530 and the second edge 532 and substantially close to the center, that is, between the first edge 530 and the second edge 532 . The second word line WL2 512 has a first edge 540, a second edge 542, and a non-edge area 541. In the embodiment of the present invention, the non-edge area 541 is indicated as a position away from the first edge 540 and the second edge 542 and substantially close to the center, that is, between the first edge 540 and the second edge 542 . The third word line WL3 514 has a first edge 550, a second edge 552, and a non-edge region 551. In the embodiment of the present invention, the non-edge area 551 is indicated as a position away from the first edge 550 and the second edge 552 and substantially close to the center, that is, between the first edge 550 and the second edge 552 . The virtual ground array 500 has no edge-induced effect because hole charge injection has not been applied to the virtual ground array 500 .

5B is a perspective view showing a virtual ground array 500 in the X1 direction 502 without a charge trapping layer above the source and drain junctions. The virtual ground array 500 includes a substrate 560 having a source region (n+) 562 and a drain region (n+) 564 separated by a channel length Lg 529 therein. In this embodiment, the charge trapping layer 568 does not extend to the bottom to the left to align with the left side of the substrate, nor does it extend to the bottom to the right to align with the right side of the substrate. Instead, the charge trapping layer 568 has a first dielectric block 565 on the left side and a second dielectric block 567 on the right side. The bottom surface of the first dielectric block 565 is in contact with the top surface of the source region 562 , so there is no charge trapping layer, as indicated by the dotted circle 570 . The bottom surface of the second dielectric block 567 is in contact with the top surface of the drain region 564 , so there is no charge trapping layer, as shown by the dotted circle 572 . The dielectric layer 566 extends between the first and second dielectric blocks 565 , 567 and under the charge trapping layer 568 .

FIG. 5C is a perspective view showing the dummy ground array 500 in the Y1 direction 504 with the charge trapping layer 568 above the edge of the word line. As viewed from the Y1 direction 504 , the bottom surfaces of the first word line WL1 510 and the second word line WL2 512 are in contact with the charge trapping layer 568 . The upper surface of the charge trapping layer 568 contacts the first and second edges 530 , 532 of the first wordline 510 and the first and second edges 540 , 542 of the second wordline 512 .

FIG. 6A shows the result of the virtual ground array 500 of the first embodiment after the hole charge injection method is implemented. When hole charge injection is performed, hole charges are stored along the edge of each word line because the edge has a larger electric field compared to the center of each word line. A plurality of hole charges 630 are stored along the first edge 530 of the first word line WL1510 and intersect with the first charge trapping portion 521 and the second charge trapping portion 523 . In more detail, a plurality of hole charges 632 are stored along the second edge 532 of the first word line WL1 510, and intersect with the first charge trapping portion 521 and the second charge trapping portion 523. For the second word line WL2512 , a plurality of hole charges 640 are stored along the first edge 540 of the second word line WL2512 , and intersect the first charge trapping portion 521 and the second charge trapping portion 523 . A plurality of hole charges 642 are stored along the second edge 542 of the second word line WL2 512 and intersect with the first charge trapping portion 521 and the second charge trapping portion 523 . For the third word line WL3 514, a plurality of hole charges 650 are stored along the first edge 550 of the third word line WL3 514, and intersect the first charge trapping portion 521 and the second charge trapping portion 523. A plurality of hole charges 652 are stored along the second edge 552 of the third word line WL3 514, and intersect with the first charge trapping portion 521 and the second charge trapping portion 523. The first edge 530 and the second edge 532 of the first word line WL1 510, as well as the edges of other word lines, strengthen the drain induced barrier lowering effect (DIBL, drain induced barrier lowering) to generate a larger second edge. Bit operation range.

FIG. 6B is a perspective view showing the virtual ground array 500 in the X2 direction 602 , where hole charges 630 are stored on the charge trapping layer 568 . The hole charge 630 causes fringing or induces the channel 563 to achieve a lower threshold voltage level. The induced channel 563 activates the virtual ground array 500, which in turn causes the source and drain regions 562, 564 to be in a conductive state. Threshold voltage Vt typically controls the operation of elements of virtual ground array 500 .

6C is a perspective view showing the virtual ground array 500 in the Y2 direction 604, where the charge trapping layer is located on the edge of the word line. As indicated by the Y2 direction 604, the bottom surfaces of the first word line WL1 510 and the second word line WL2 512 are in contact with the charge trapping layer 568. The upper surface of the charge trapping layer is in contact with the first and second edges 530 , 532 of the first wordline 510 , and is in contact with the first and second edges 540 , 542 of the second wordline 512 . The non-edge region 531 located in the charge trapping layer and below the first word line 510 does not store hole charges. Similarly, the non-edge region 541 located in the charge trapping layer and located below the second word line 512 also does not store hole charges.

FIG. 7A is a structural diagram showing a virtual ground array 700 of the second embodiment before the hole injection method is implemented in the MNOS memory. The virtual ground array 700 includes a plurality of horizontally extending word lines (gates) WL1 710, WL2 712 and WL3 714, as indicated by arrow X1 702. The width of each of WL1 710, WL2 712 and WL3 714 is indicated by reference Wg 718. The virtual ground array 700 also includes a plurality of bit lines BL1 720, BL2 722, and BL3 724, and has a first charge trapping part 721 between the bit lines BL1 720, BL2 722, and has a first charge trapping part 721 between the bit lines BL2 722, BL3 724. The second charge trapping portion 723, the two portions extend along the vertical direction, as indicated by the arrow Y1 704. The length of each charge trapping portion 721, 723 is indicated by the reference Lg 728. The first charge trapping portion 721 and the second charge trapping portion 723 are part of the charge trapping layer.

The first word line WL1 710 has a first edge 730, a second edge 732, and a non-edge area 731. In other embodiments, the non-edge area 731 is indicated as a position away from the first edge 730 and the second edge 732 and substantially close to the center, that is, between the first edge 730 and the second edge 732 . The second word line WL2 712 has a first edge 740, a second edge 742, and a non-edge area 741. In other embodiments, the non-edge area 741 is indicated as a position away from the first edge 740 and the second edge 742 and substantially close to the center, that is, between the first edge 740 and the second edge 742 . The third word line WL3 714 has a first edge 750, a second edge 752, and a non-edge area 751. In other embodiments, the non-edge area 751 is indicated as a position away from the first edge 750 and the second edge 752 and substantially close to the center, that is, between the first edge 750 and the second edge 752 . The virtual ground array 700 has no edge-induced effect because hole charge injection has not been applied to the virtual ground array 700 .

7B is a perspective view showing a virtual ground array 700 in the X1 direction 702 with a charge trapping layer over the source and drain junctions. The virtual ground array 700 includes a substrate 760 having a source region (n+) 762 and a drain region (n+) 764 separated by a channel length Lg 728 therein. In this embodiment, the dielectric layer 766 is located on the substrate 760 , the charge trapping layer is located on the dielectric layer 766 , and the gate 710 is located on the charge trapping layer 768 . In this embodiment, 768 extends over source region 762 , as indicated by dashed circle 770 , and extends over drain region 764 , as indicated by dashed circle 772 .

FIG. 7C shows a perspective view of the virtual ground array 700 in the Y1 direction 704, where the charge trapping layer 768 is located on the edge of the word line. As viewed from the Y1 direction 704, the bottom surfaces of the first word line WL1 710 and the second word line WL2 712 are in contact with the charge trapping layer 768. The top surface of the charge trapping layer 768 is in contact with the first and second edges 730 , 432 of the first word line 710 , and is in contact with the first and second edges 740 , 742 of the second word line 712 .

FIG. 8A is a top view of the virtual ground array 700 of the second embodiment after implementing hole and charge injection. When hole charge injection is performed, hole charges are stored along the edge of each word line because the edge has a larger electric field compared to the center of each word line. A plurality of hole charges 830 are stored along the first edge 730 of the first word line WL1 710, and intersect with the first charge trapping portion 721 and the second charge trapping portion 723. Hole charges are also stored along the other edges of the word line. In more detail, a plurality of hole charges 832 are stored along the second edge 732 of the first word line WL1 710, and intersect with the first charge trapping portion 721 and the second charge trapping portion 723. For the second word line WL2 712, a plurality of hole charges 840 are stored along the first edge 740 of the second word line WL2 712, and intersect the first charge trapping portion 721 and the second charge trapping portion 723. A plurality of hole charges 842 are stored along the second edge 742 of the second word line WL2 712, and intersect with the first charge trapping portion 721 and the second charge trapping portion 723. For the third word line WL3 714, a plurality of hole charges 850 are stored along the first edge 750 of the third word line WL3 714 and intersect the first charge trapping portion 721 and the second charge trapping portion 723. A plurality of hole charges 852 are stored along the second edge 752 of the third word line WL3 714, and intersect with the first charge trapping portion 721 and the second charge trapping portion 723.

FIG. 8B shows a perspective view of the virtual ground array 700 in the X2 direction 802 , where holes 830 are stored in the charge trapping layer 768 . The hole charge 830 creates a fringe or induces a channel for a lower threshold voltage level. The induced channel 763 activates the virtual ground array 700, which in turn causes the source and drain regions 762, 764 to be turned on. Threshold voltage Vt typically controls the operation of elements of virtual ground array 700 .

8C shows a perspective view of the virtual ground array 700 in the Y2 direction 804, where the charge trapping layer is located on the edge of the word line. As shown in the Y2 direction 804, the bottom surfaces of the first word line WL1 710 and the second word line WL2 712 are in contact with the charge trapping layer 768. The upper surface of the charge trapping layer is in contact with the first and second edges 730 , 732 of the first wordline 710 , and is in contact with the first and second edges 740 , 742 of the second wordline 712 . The non-edge region 731 located in the charge trapping layer and below the first word line 710 does not store hole charges. Similarly, the non-edge region 741 located in the charge trapping layer and located below the second word line 712 also does not store hole charges.

FIG. 9 is a block diagram showing a top view of a virtual ground array 700 before hole charge injection is implemented on the MNOS memory, where the holes are injected as an asymmetric threshold voltage level along the word line. The virtual ground array 900 includes a plurality of horizontally extending word lines (gates) WL1 910, WL2 912 and WL3 914. The width of each of WL1 910, WL2 912 and WL3 914 is indicated by reference Wg 918. The virtual ground array 900 also includes a plurality of bit lines BL1 920, BL2 922, and BL3 924, and has a first charge trapping part 921 between the bit lines BL1 920, BL2 922, and has a first charge trapping part 921 between the bit lines BL2 922, BL3 924. The second charge trapping portion 923, the two portions extend along the vertical direction. The length of each charge trapping portion 921, 923 is indicated by reference Lg 929. The first charge trapping portion 921 and the second charge trapping portion 923 are part of the charge trapping layer. At the intersection of the first charge trapping portion 921 and the first, second, and third word lines WL1 910, WL2 912, and WL3 914, there are first dielectric strips 925 and second dielectric strips 926 extending perpendicular to the first charge trapping both sides of section 921. At the intersection of the second charge trapping portion 923 and the first, second, and third word lines WL1 910, WL2 912, and WL3 914, there are third dielectric strips 927 and fourth dielectric strips 928 extending perpendicularly to the first charge trapping both sides of section 923.

The first word line WL1 910 has a first edge 930 (shown as a dotted square) and a second edge 932 (shown as a dotted square), and a non-edge area 931 (shown as a solid line). In the embodiment of the present invention, the non-edge area 931 is indicated as a position away from the first edge 930 and the second edge 932 and substantially close to the center, that is, between the first edge 930 and the second edge 932 . The second word line WL2 912 has a first edge 940 (shown as a dotted square), a second edge 942 (shown as a dotted square), and a non-edge area 941 (shown as a solid line). In the embodiment of the present invention, the non-edge area 941 is indicated as a position away from the first edge 940 and the second edge 942 and substantially close to the center, that is, between the first edge 940 and the second edge 942 . The third word line WL3 914 has a first edge 950 (shown as a dotted square), a second edge 952 (shown as a dotted square), and a non-edge area 951 (shown as a solid line). In the embodiment of the present invention, the non-edge area 951 is indicated as a position away from the first edge 950 and the second edge 952 and substantially close to the center, that is, between the first edge 950 and the second edge 952 . The virtual ground array 900 has no edge-induced effect because hole charge injection has not been applied to the virtual ground array 900 .

Each word line WL1 910 , WL2 912 , WL3 914 has two threshold voltage levels, the edge threshold voltage level is represented by Vt _fringe , and the non-edge threshold voltage level is represented by Vt _non-fringe . In some embodiments, the fringes 930, 932 are related to the fringe threshold voltage Vt _fringe , while the non-fringe region 931 is related to the non-fringe threshold voltage Vt _non-fringe . Typically, lower threshold voltage levels will control device operating characteristics. To operate virtual ground array 900 at the edge of a word line, the edge threshold voltage Vt _fringe is lower than the non-edge threshold voltage Vt _non-fringe .

FIG. 10 is a structural diagram showing a top view of a virtual ground array 1000 before hole charge injection is implemented on the MNOS memory, where the holes are injected as an asymmetric threshold voltage level along the word lines. The virtual ground array 1000 includes a plurality of horizontally extending word lines (gates) WL1 1010, WL2 1012 and WL3 1014. The width of each WL1 1010, WL2 1012 and WL3 1014 is indicated by the reference Wg 1018. The virtual ground array 1000 also includes a plurality of bit lines BL1 1020, BL2 1022, and BL3 1024, and has a first charge trapping part 1021 between the bit lines BL1 1020, BL2 1022, and has a first charge trapping part 1021 between the bit lines BL2 1022, BL3 1024. The second charge trapping portion 1023, the two portions extend along the vertical direction. The length of each charge trapping portion 1021, 1023 is denoted by reference Lg 10210. The first charge trapping portion 1021 and the second charge trapping portion 1023 are part of the charge trapping layer.

The first word line WL1 1010 has a first edge 1030 (shown as a dotted square) and a second edge 1032 (shown as a dotted square), and a non-edge area 1031 (shown as a solid line). In the embodiment of the present invention, the non-edge area 1031 represents a position away from the first edge 1030 and the second edge 1032 and substantially close to the center, that is, between the first edge 1030 and the second edge 1032 . The second word line WL2 1012 has a first edge 1040 (shown as a dotted square), a second edge 1042 (shown as a dotted square), and a non-edge area 1041 (shown as a solid line). In the embodiment of the present invention, the non-edge area 1041 represents a position away from the first edge 1040 and the second edge 1042 and substantially close to the center, that is, between the first edge 1040 and the second edge 1042 . The third word line WL31014 has a first edge 1050 (shown as a dotted square), a second edge 1052 (shown as a dotted square), and a non-edge area 1051 (shown as a solid line). In the embodiment of the present invention, the non-edge area 1051 represents a position away from the first edge 1050 and the second edge 1052 and substantially close to the center, that is, between the first edge 1050 and the second edge 1052 . The virtual ground array 1000 has no edge-induced effect because hole charge injection has not been applied to the virtual ground array 1000 .

Each word line WL1 1010 , WL2 1012 , WL3 1014 has two threshold voltage levels, the edge threshold voltage level is represented by Vt _fringe , and the non-edge threshold voltage level is represented by Vt _non-fringe . In some embodiments, the fringes 1030, 1032 are related to the fringe threshold voltage Vt _fringe , while the non-fringe region 1031 is related to the non-fringe threshold voltage Vt _non-fringe . Typically, lower threshold voltage levels will control device operating characteristics. In order to operate the virtual ground array 1000 at the edge of a word line, the edge threshold voltage Vt _fringe is lower than the non-edge threshold voltage Vt _non-fringe .

Figure 11A is a structural diagram showing the programming of the left bit (Bit-L) in the MNOS structure, while Figure 11B is the corresponding single-unit double-bit operation interval, which illustrates the second bit effect, that is, the right bit What happens at the bit (Bit-R). The second bit effect occurs in charge-trapping memories that use single-cell two-bit operations (ie, left and right bits). When one of the two bits is programmed, even if only one bit is programmed, the threshold voltage of the other bit may increase accordingly. The programming of the left bit is shown in FIG. 11A with charge 1110 indicated at 1112 on the left. Although only the left bit 1112 is programmed, the programming of the left bit 1112 also causes the threshold voltage of the right bit 1114 to increase, as shown in FIG. 11B . Curve 1120 shows that the threshold voltage of the right bit 1114 increases as the left bit 1112 is programmed. This phenomenon is called the second place effect. An ideal curve without second-bit effects would show that continuous programming of the left bit increases the threshold voltage of the left bit, but leaves the threshold voltage of the right bit unaffected, allowing the threshold voltage of the right bit to remain substantially stable .

FIG. 12 is an exemplary graph diagram 1200 illustrating a second bit interval of a virtual ground array using a hole injection edge induced operation. The second bit interval is defined as the difference between the right bit threshold voltage Vt(r) 1210 and the left bit threshold voltage Vt(1) 1220 . As shown in FIG. 12, the threshold voltage of the left bit varies by about 6.0 volts, while that of the right bit varies by about 1.4 volts. Therefore, in the second bit interval in this example, the variation of Vt(r) 1210 is subtracted from the variation of Vt(1) 1220, that is, 6.0−1.5=4.5 volts. The graph 1200 is only for illustration and not for limiting the present invention, and the operating range of 4.5 volts is an ideal parameter.

For the hole injection method and the second bit effect of a charge trap memory that can store multiple bits in a single cell, please refer to US Patent Application No. _11/614,905, entitled "Methods and Structures for Expnading a Memory Operation Window and Reducing a Second BitEffect", whose inventors are the same as the present invention, and incorporated by reference in this case.

Those skilled in the art should not need additional information to develop the methods and systems of the present invention, but may be able to obtain some useful information by reading general references in the relevant field.

While the invention has been described with reference to preferred embodiments, it will be understood that the inventive concept is not limited to the details described. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. In particular, according to the structure and method of the present invention, all combinations of components substantially the same as those of the present invention to achieve substantially the same results as the present invention do not depart from the scope of the present invention. Accordingly, all such alternatives and modifications are intended to come within the scope of the invention as defined in the appended claims and their equivalents. Any patent applications mentioned above, as well as printed versions, are hereby incorporated by reference in this case.

Claims (8)

1. A storage device, comprising: Substrate; a charge trapping structure on the substrate, the charge trapping structure extending in a first direction; and The gate extends in a second direction and intersects with the charge trapping structure, the gate has a bottom surface defined by a first edge and a second edge, wherein the first edge and the second edge separated by a non-edge portion having a first threshold voltage, the first and second edges having a second threshold voltage, wherein holes are moved to the charge trapping structure by hole injection, and placed under the gate and arranged along the first and second edges of the gate, so that the second threshold voltage is lower than the first threshold voltage. 2. The device of claim 1, wherein the holes are stored in a charge trapping structure under and aligned with first and second edges of the gate. 3. The device of claim 1, wherein said hole injecting step comprises applying a positive gate voltage to erase said memory device to a negative voltage level by moving holes from the gate to said The charge trapping structure is completed. 4. The device of claim 1, wherein said hole injecting step comprises applying a negative gate voltage to erase said memory device to a negative voltage level by moving holes from the substrate to said The charge trapping structure is completed. 5. The device of claim 1, wherein the charge trapping structure comprises a charge trapping layer overlying a dielectric layer. 6. The device of claim 1, wherein the charge trapping structure includes a top dielectric layer overlying the charge trapping layer, and the charge trapping layer overlies the bottom dielectric layer. 7. The apparatus of claim 1, further comprising a first dielectric portion and a second dielectric portion, the charge trapping structure being disposed between the first and second dielectric portions. 8. A storage processing structure, comprising: more than one bit line extending in a first direction and parallel to each other; More than one word line extends along the second direction and intersects the charge trapping layer, the word line has a bottom surface defined by a first edge and a second edge, wherein the first edge and the second edge an edge is separated by a non-edge portion, the non-edge portion has a first threshold voltage, the first and second edges have a second threshold voltage, wherein holes are moved to the charge trapping layer by hole injection, And the holes are placed under each of the word lines and arranged along the first and second edges of each of the word lines, so the second threshold voltage value is lower than the first threshold voltage; and The charge trapping layer is disposed under the one or more word lines and is in contact with the bottom surface of each of the word lines.

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