CN100523978C - Apparatus array and its manufacturing method - Google Patents

Abstract

The present invention provides apparatus and methods for arranging devices with a reduced area between adjacent devices. In an exemplary embodiment, display devices 100 in an array 85 are provided, wherein a gap 123 between the display devices 100 is reduced to less than or equal to one-eighth of a pixel pitch. Exemplary embodiments use solder wires 125 to provide an electrical connection of an active area of the display to components on the display backplane, thereby reducing overhang areas and gaps between display devices in an interconnected array.

Description

Device array and method of manufacturing the same

technical field

The present invention relates to apparatus and methods for arranging devices into an interconnected array. More specifically, the present invention relates to an array of interferometric modulator devices with a minimized protrusion area between each device to produce a large format image.

Background technique

Display devices may be attached to each other by tiling, which involves placing multiple display devices next to each other to form a larger system. Tiling is especially useful for building larger displays, and in situations where the largest display that can be produced is smaller than the desired display size. For example, a billboard or other signage is often too large to be made from a single sheet of glass. Also, the price to make a large sheet of glass can be quite high. Thus, tiling can be used as a low-cost alternative by making one large display from several smaller displays.

Once complete, the tiled display essentially functions as one large display. For example, it can produce a single complete image. Because it is tiled, the array has the added advantage of allowing the separation of multiple images when it is desired to produce different discrete images on what appears to be a single display screen.

Generally, when display devices are tiled into an array, there is a void area between the display area of one device and the display area of an adjacent device. When the void area is perceived by the viewer, this void area will limit the image quality of large displays.

Contents of the invention

One embodiment of the invention is an array of devices comprising:

A first device comprising: a package including a substrate, a first active area, and an electrical connection area, wherein the electrical connection area is configured to provide electrical communication with the first active area, wherein the The width of the electrical connection area is less than 1 millimeter; a sealing ring surrounding the first active area; a base plate bonded to the sealing ring to form the package, wherein the electrical connection area is disposed between the sealing member and between an edge of the substrate; and a second device including a second active area and positioned adjacent to the electrical connection area of the first device.

Another embodiment of the present invention is a method of manufacturing a display device array, which includes: providing a first display device, which includes: a display package including a substrate, a first active area and an electrical connection area, wherein the electrical connection area configured to provide electrical communication with the first active area; a seal ring surrounding the first active area; a base plate bonded to the seal ring to form the display package; wherein The electrical connection area is disposed between the seal and an edge of the substrate; providing a second display device including a second active area; and placing the first display device and the second display device Together, the active area of the second display device is adjacent to the electrical connection area of the first display device, wherein the width of the electrical connection area is less than or equal to 1 mm.

Yet another embodiment of the present invention is a method for manufacturing a display device array: a first display device is provided, which includes: a display package including a substrate, a first active area, and an electrical connection area, wherein the an electrical connection area configured to provide electrical communication with the first active area; a seal ring surrounding the first active area; a base plate bonded to the seal ring to form the display package; wherein the electrical a connection region is disposed between the seal and an edge of the substrate; a second display device including a second active region is provided; and the first display device and the second display device are positioned between Together, the active area of the second display device is adjacent to the electrical connection area of the first display device, wherein the width of the electrical connection area is less than or equal to 1 mm.

An additional embodiment is an array of devices comprising: a first device comprising: a transmissive member for transmitting light therethrough; a first device for modulating light transmitted through the transmissive member A movable member; electrical connection member for providing electrical communication with said first movable member, wherein said electrical connection member has a width of less than 1 mm; sealing member for surrounding said first movable member with a sealing layer a cover member for forming a package of the transmission member, the first movable member, and the sealing member, wherein the electrical connection member is disposed between the sealing member and an edge of the transmission member in a region; and a second device comprising a second movable member for reflecting light and positioned adjacent to said electrical connection member of said first device.

Description of drawings

1 is an isometric view depicting a portion of an embodiment of an interferometric modulator display with a movable reflective layer of a first interferometric modulator in a released position and a movable reflective layer of a second interferometric modulator. The reflective layer is moved to an actuated position.

2 is a system block diagram illustrating an embodiment of an electronic device incorporating a 3x3 interferometric modulator display.

3 is a graph of movable mirror position versus applied voltage for an exemplary embodiment of the interferometric modulator of FIG. 1 .

Figure 4 illustrates a set of row and column voltages that can be used to drive an interferometric modulator display.

FIG. 5A illustrates an exemplary frame of display data in the 3×3 interferometric modulator display of FIG. 2 .

FIG. 5B illustrates an exemplary timing diagram for row and column signals that may be used to write the frame shown in FIG. 5A.

FIG. 6A is a cross-sectional view of the device shown in FIG. 1 .

Figure 6B is a cross-sectional view of an alternate embodiment of an interferometric modulator.

Figure 6C is a cross-sectional view of another alternative embodiment of an interferometric modulator.

7 is a cross-sectional view of a basic package structure for a MEMS device.

Figure 8 is an exploded view of an embodiment of a display in which a printed circuit bracket is soldered to a backplate.

FIG. 9 is an exemplary embodiment of a display device with a reduced footprint.

FIG. 10 is an exploded view of an exemplary embodiment of a display device with a reduced footprint.

11A and 11B are diagrams showing an embodiment of tiling of the display.

12A and 12B are system block diagrams illustrating an embodiment of a visual display device including a plurality of interferometric modulators.

Detailed ways

One embodiment of the invention is a large display consisting of a plurality of individual display devices. The individual display devices are placed next to each other in a method known as tiling, so that they form one large display. In this embodiment, the edges between each individual display device are minimized so that the viewer is not aware of the edges when looking at the large display.

The following detailed description is directed to certain specific embodiments of the present invention. However, the invention can be implemented in many different ways. In this description, reference will be made to the drawings in which like parts are numbered throughout. As will be apparent from the following description, the present invention can be implemented in any device configured to display an image in motion (eg, video) or still (eg, still image) and in the form of text or pictures. More specifically, it is contemplated that the present invention may be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, GPS Receivers/navigators, video cameras, MP3 players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), cockpits Controllers and/or displays, camera view displays (e.g., a vehicle's rear-view camera display), electronic photographs, electronic billboards or signage, projectors, architectural structures (e.g., brick layout), packaging, and aesthetic structures (e.g., , an image display of a piece of jewelry). Microelectromechanical systems (MEMS) devices similar in structure to those described herein may also be used in non-display applications such as electronic switching devices.

Figure 1 illustrates an interferometric modulator display embodiment including an interferometric MEMS display element. In these devices, the pixels are either in a bright state or a dark state. In the bright ("on" or "open") state, the display element reflects most of the incident visible light to the user. When in the dark ("off" or "closed") state, the display element reflects little incident visible light to the user. Depending on the embodiment described, the light reflective properties of the "on" and "off" states may be reversed. MEMS pixels can be configured to reflect primarily selected colors, allowing color to be displayed in addition to black and white.

1 is an isometric view depicting two adjacent pixels within a series of pixels of a visual display, where each pixel includes a MEMS interferometric modulator. In some embodiments, an interferometric modulator display includes a row/column array of interferometric modulators. Each interferometric modulator includes a pair of reflective layers positioned at a variable and controllable distance from each other to form an optical resonant cavity having at least one variable dimension. In an embodiment, one of the reflective layers is movable between two positions. In a first position, referred to herein as a released state, the movable layer is placed at a relatively large distance from the partially fixed reflective layer. In the second position, the movable layer is positioned closer adjacent the partially reflective layer. Incident light reflected from the two layers interferes constructively or destructively, depending on the position of the movable reflective layer, producing a total reflective or non-reflective state for each pixel.

The pixel array portion shown in Figure 1 comprises two adjacent interferometric modulators 12a and 12b. In the interferometric modulator 12a on the left, a movable highly reflective layer 14a is illustrated in a released position a predetermined distance from a fixed partially reflective layer 16a. In the interferometric modulator 12b on the right, the movable highly reflective layer 14b is illustrated in an actuated position adjacent to the fixed partially reflective layer 16b.

The fixed layers 16a, 16b are conductive, partially transparent, and partially reflective, and may be made, for example, by depositing one or more layers each of chromium and indium tin oxide on a transparent substrate 20 . These layers are then patterned into parallel strips and may form row electrodes in a display device as described further below. The movable layers 14a, 14b may be formed as a deposited metal layer or layer(s) deposited on top of the pillars 18 (orthogonal to the row electrodes 16a, 16b) and intervening layers deposited between the pillars 18. A series of parallel strips of sacrificial material. When the sacrificial material is etched away, the deformable metal layer is separated from the fixed metal layer by a defined air gap 19 . A highly conductive reflective material such as aluminum can be used for the deformable layer, and the strips can form column electrodes in a display device.

If no voltage is applied, the chamber 19 remains between the layers 14a, 16a and the deformable layer is in a mechanically relaxed state as illustrated by pixel 12a of FIG. 1 . However, when a potential difference is applied to a selected row and column, the capacitance formed at the intersection of the row and column electrodes at the corresponding pixel is charged, and electrostatic forces pull these electrodes together. If the voltage is high enough, the movable layer is deformed and forced against the fixed layer (a dielectric material not illustrated in the figure can be deposited on the fixed layer) as shown in the pixel 12b on the right in FIG. to prevent short circuits and control spacing). This action is the same regardless of the polarity of the applied potential difference. In this way, row/column actuation that can control reflective versus non-reflective pixel states is similar in many respects to row/column actuation used in conventional LCD and other display technologies.

Pentium

 Pro、8051、

Power 

或任何专用微处理器，例如数字信号处理器、微控制器或可编程门阵列。如此项技术中的常规情形，处理器21可经配置以执行一个或一个以上的软件模块。除执行操作系统外，所述处理器可经配置以执行一个或一个以上的软件应用程序，其中包括网页浏览器、电话应用程序、电子邮件程序或任何其他软件应用程序。2-5B illustrate an exemplary process and system for using an array of interferometric modulators in a display application. 2 is a system block diagram illustrating an embodiment of an electronic device that may incorporate aspect(s) of the present invention. In the exemplary embodiment, the electronic device includes a processor 21, which can be any general-purpose single-chip or multi-chip microprocessor, such as ARM,

Pentium

Pro, 8051,

power

Or any special purpose microprocessor such as a digital signal processor, microcontroller or programmable gate array. As is conventional in the art, processor 21 may be configured to execute one or more software modules. In addition to executing an operating system, the processor may be configured to execute one or more software applications, including a web browser, telephony application, email program, or any other software application.

In one embodiment, the processor 21 may also be configured to communicate with an array controller 22 . In one embodiment, the array controller 22 includes a row driver circuit 24 and a column driver circuit 26 that provide signals to the pixel array 30 . A cross-section of the array illustrated in Figure 1 is shown by line 1-1 in Figure 2 . For MEMS interferometric modulators, the row/column excitation protocol can take advantage of the hysteresis properties of these devices illustrated in FIG. 3 . It may require, for example, a 10 volt potential difference to cause the movable layer to deform from a released state to an actuated state. However, when the voltage is reduced from that value, the movable layer retains its state as the voltage drops below 10 volts. In the exemplary embodiment of FIG. 3, the movable layer cannot fully release until the voltage drops below 2 volts. Thus, in the example illustrated in FIG. 3 there is a voltage range of about 3V to 7V in which there is a window of applied voltage in which the device is stably in the released or actuated state. This is referred to herein as the "hysteresis window" or "stability window". For a display array having the hysteresis characteristic of Figure 3, the row/column excitation protocol can be designed such that during row gating, the pixels in the strobed row to be actuated are exposed to a voltage difference of about 10 volts and are to be released The pixels are exposed to a voltage difference close to 0 volts. After gating, the pixel is exposed to a steady state voltage difference of about 5 volts so that it remains in whatever state the row strobe left it in. After writing, in the example described, each pixel sees a potential difference within a "stability window" of 3-7 volts. This property makes the pixel design illustrated in FIG. 1 stable in a pre-existing actuated or released state under the same applied voltage conditions. Since each pixel of the interferometric modulator is essentially a capacitor formed by the fixed reflective layer and the movable reflective layer whether in the actuated state or the released state, the stable state can be maintained with almost no power consumption A voltage within the hysteresis window of . If the applied potential is fixed, substantially no current flows into the pixel.

In a typical application, a display frame may be generated by determining the set of column electrodes according to the desired set of actuated pixels in the first row. Thereafter, a row pulse is applied to the row 1 electrode to actuate the pixels corresponding to the determined column line. Thereafter, the determined set of column electrodes is changed to correspond to the desired set of actuated pixels in the second row. Thereafter, a pulse is applied to the row 2 electrodes to actuate the appropriate pixels in row 2 according to the determined column electrodes. Row 1 pixels are unaffected by the Row 2 pulse and remain in the state they were set to during the Row 1 pulse. This process can be repeated in a sequential fashion for the entire series of rows to produce frames. Generally, the frames are refreshed and/or updated with new display data by continuously repeating this process at some desired number of frames per second. Various protocols for driving the row and column electrodes of an array of pixels to form a display frame are also well known and may be used in conjunction with the present invention.

4, 5A and 5B illustrate possible excitation protocols for generating display frames on the 3x3 array shown in Fig. 2 . FIG. 4 illustrates a possible set of column and row voltage potentials that may be used for a pixel exhibiting the hysteresis curve of FIG. 3 . In the embodiment shown in FIG. 4, energizing a pixel includes setting the appropriate column to -V _bias and the appropriate row to +ΔV, which may correspond to -5 volts and +5 volts, respectively. Releasing the pixel is accomplished by setting the appropriate column to +V _bias and the appropriate row to the same +ΔV, resulting in a zero volt potential difference across the pixel. In those rows where the row voltage remains at 0 volts, the pixel is stable in whatever state it was originally in, regardless of whether the column _{is biased} at +V or -V.

5B is a timing diagram showing a series of row and column signals applied to the 3x3 array shown in FIG. 2 that result in the display arrangement illustrated in FIG. 5A in which the actuated pixels are non-reflective. The pixels can be in any state prior to writing the frame illustrated in Figure 5A, and in this example, all rows are at 0 volts and all columns are at +5 volts. With these applied voltages, all pixels are stable in their existing actuated or released states.

In the frame shown in FIG. 5A, pixels (1,1), (1,2), (2,2), (3,2) and (3,3) are activated. To achieve the excitation, during the "line time" of row 1, columns 1 and 2 are set to -5 volts and column 3 is set to +5 volts. This did not change the state of any pixels, as all remained within the 3-7 volt stability window. Thereafter, row 1 is strobed with a pulse that rises from 0 volts to 5 volts and then falls back to 0 volts. This activates pixels (1,1) and (1,2) and releases pixel (1,3). No other pixels in the array are affected. To set row 2 as desired, set column 2 to -5 volts, and set columns 1 and 3 to +5 volts. Thereafter, the same strobe applied to row 2 will actuate pixel (2,2) and release pixels (2,1) and (2,3). Likewise, no other pixels in the array are affected. Row 3 is similarly set by setting columns 2 and 3 to -5 volts and column 1 to +5 volts. The row 3 strobe pulse sets row 3 pixels as shown in FIG. 5A. After writing a frame, the row potentials are 0, and the column potentials can remain at +5 volts or -5 volts, and thereafter the display is stable in the arrangement shown in Figure 5A. It should be understood that the same procedure described can be used for arrays of tens or hundreds of rows and columns. It should also be understood that the timing, sequence, and potentials of the voltages used to perform row and column excitations can vary widely within the general principles described above, and that the above examples are exemplary only, and that any method of excitation voltages may be used in the present invention .

The details of the construction of interferometric modulators operating according to the principles described above can vary widely. For example, Figures 6A-6C illustrate three different embodiments of moving mirror structures. FIG. 6A is a cross-sectional view of the embodiment of FIG. 1 in which a strip 14 of metallic material is deposited on orthogonally extending supports 18 . In FIG. 6B , the movable reflective material 14 is only attached to the corners of the support, on tethers 32 . In FIG. 6C , the movable reflective material 14 is suspended from a deformable layer 34 . This embodiment is beneficial because the structural design and used materials for the reflective material 14 can be optimized with regard to optical properties and the structural design and used materials of the deformable layer 34 can be optimized with regard to desired mechanical properties. The production of various types of interferometric devices is described in a number of publications including, for example, US Published Application No. 2004/0051929. Various well-known techniques can be used to produce the structures described above, involving a series of material deposition, encapsulation and etching steps.

A movable part of a MEMS device, such as an array of interferometric modulators, preferably has a protected space in which to move. Packaging techniques for MEMS devices are described in more detail below. A schematic diagram of a basic package structure for a MEMS device such as an array of interferometric modulators is illustrated in FIG. 7 . As shown in FIG. 7, a basic package structure 70 includes a substrate 72 on which an array of interferometric modulators 76 is formed, and a floor cover or "mask" 74. As shown in FIG. The cover 74 is also referred to as a "back plate".

The substrate 72 and the base plate 74 are bonded together by a sealant 78 to form the package structure 70 such that the interferometric modulator array 76 is packaged by the substrate 72 , the base plate 74 and the sealant 78 . This forms a chamber 79 between the base plate 74 and the substrate 72 . Seal 78 may be a non-hermetic seal, such as a conventional epoxy-based adhesive. In other embodiments, the seal 78 can be polyisobutylene (sometimes called ^butyl rubber, otherwise known as PIB), O-rings, polyurethane, thin-film metal solder, liquid spin-on-glass, solder, polymer, or plastic. In other embodiments, seal 78 may be a hermetic seal.

In certain embodiments, encapsulation structure 70 includes a desiccant 80 configured to reduce humidity within chamber 79 . The skilled artisan will understand that a desiccant is not necessary for a hermetically sealed package, but is needed to control the moisture resident within the package. In one embodiment, a desiccant 80 is placed between the interferometric modulator array 76 and the base plate 74 . Desiccants are available in packages with hermetic or non-hermetic seals. In packages with hermetic seals, desiccants are often used to control the moisture resident inside the package. In packages with non-hermetic seals, desiccants may be used to control moisture migration from the environment into the package. In general, any substance that can trap moisture while not interfering with the optical properties of the interferometric modulator array can be used as desiccant 80 . Suitable desiccant materials include, but are not limited to, zeolites, molecular sieves, surface adsorbents, bulk adsorbents, and chemical reactants.

Desiccant 80 can take on different forms, shapes and sizes. In addition to being solid, desiccant 80 may alternatively be in powder form. These powders can be inserted directly into the package or mixed with an adhesive for application. In an alternative embodiment, the desiccant 80 may be formed into a different shape, such as a cylinder or a sheet, before being applied into the package.

Skilled artisans will understand that desiccant 80 can be applied in different ways. In one embodiment, desiccant 80 is deposited as part of interferometric modulator array 76 . In another embodiment, desiccant 80 is applied within package 70 as a spray coating or dip coating.

Substrate 72 can be a translucent or transparent substance on which thin-film, MEMS devices can be built. These transparent substances include, but are not limited to, glass, plastic, and transparent polymers. Interferometric modulator array 76 may include thin film modulators or separable modulators. Those skilled in the art will appreciate that base plate 74 may be formed from any suitable material, such as glass, metal, foil, polymer, plastic, ceramic, or semiconductor material (eg, silicon).

The encapsulation process can be accomplished in a vacuum, at a pressure between a vacuum and a pressure up to and including ambient pressure, or at a pressure above ambient pressure. The encapsulation process can also be accomplished in a varied and controlled high or low pressure environment during the sealing process. It may be advantageous to package interferometric modulator array 76 in a completely dry environment, but it is not required. Similarly, the packaging environment may be an environment of inert gas under ambient conditions. Since the device can be shipped under ambient conditions without affecting the operation of the device, packaging under ambient conditions allows for lower cost handling and allows for more potential variety in equipment selection.

In general, the infiltration of water vapor into the package structure needs to be minimized, and thus the environment inside the package structure 70 is controlled and hermetically sealed to ensure that the environment is constant. An example of a hermetically sealing process is disclosed in US Patent No. 6,589,625, which is incorporated herein by reference in its entirety. When the humidity inside the package exceeds the level at which the surface tension generated by the moisture becomes higher than the restoring force of the movable elements (not shown) in the interferometric modulator array 70, the movable elements (not shown) Components can become permanently adhered to the surface. If the humidity level is too low, the moisture charges to the same polarity as the movable element when the element comes into contact with the coated surface.

As noted above, a desiccant may be used to control the moisture resident within the encapsulation structure 70 . However, with the implementation of the hermetic seal 78 to prevent moisture from entering the interior of the package structure 70 from the surrounding environment, the need for a desiccant can be reduced or eliminated.

The continued reduction in the size of display devices limits the methods available for managing the environment within packaging structure 70 as the space within packaging structure 70 for placement of desiccant 80 decreases. Eliminating the need for a desiccant also allows the encapsulation structure 70 to be thinner, which may be desirable in certain embodiments. In general, within a package containing a desiccant, the lifetime expectation of the packaged device may depend on the lifetime of the desiccant. When the desiccant is completely consumed, the interferometric modulator device may be inoperable due to sufficient moisture entering the packaging structure and damaging the interferometric modulator array.

As previously stated, configurations of the embodiments herein are applicable to display-centric products such as cell phones, laptops, digital cameras, and GPS units. Such devices are display-centric, ie each device relies on a flat-panel display as the primary means of providing information. The display may also participate in input functions. Thus, the display can have an impact on the mechanical, electrical, systems, and aesthetic design of a product, often outweighing the contribution of other parts of the product. The displays are typically constructed of a material, such as glass, which is more brittle than the other materials that make up the product. As a result, the mechanical and product design process tends to center on the performance and features of the display rather than, for example, the processor or battery. Many components in handheld products share a similar footprint. These components include printed circuit (PC) boards, light sources, keypads, batteries, integrated circuits, supplementary or replacement flat panel displays, and other components. Because these components are typically planar, the tools that design them typically produce a similar output in the form of one or more photolithographic masks or other imaging tools. Thus, there is an opportunity for increased integration and increased efficiency in the design process, which can be fully enabled by incorporating functionality into the backplane.

FIG. 8 depicts an embodiment of an interferometric modulator display device 600 shown in exploded view. The device 600 includes a transparent substrate 602 that includes an array of interferometric modulators 604 configured to reflect ambient light entering through the substrate 602 . The array 604 provides a means for modulating light and reflecting it towards a viewer. Transparent substrate 602 may include a glass layer. In an alternate embodiment, transparent substrate 602 may include a layer of transparent polymeric material, or any other suitable substantially transparent material. Thus, transparent substrate 602 provides a means for supporting array 604 . In some embodiments, the transparent substrate 602 may be from about 0.7 mm to 0.5 mm, depending on the manufacturing process and the nature of the product.

The device 600 also includes a driver chip 612 on an extended protrusion 613 of the transparent substrate 602 . Extending the protrusion 613 increases the size of the area occupied by the interferometric modulator display device 600 and thereby increases the gap distance from the interferometric modulator array 604 of any adjacent device 600 . Typically, the extension protrusion 613 has a width between 1.5 millimeters and 2.5 millimeters and is configured to have electrical components such as the driver chip 612 attached thereto. In addition, 1.3 mm to 1.5 mm of the transparent substrate 602 is occupied by the width 615 of the package encapsulation layer to further increase the gap distance between any adjacent arrays of interferometric modulators.

This gap distance limits the image quality of a larger display comprising an array of display devices 600 configured together at adjacent extended tabs 613 due to the interferometric modulators of adjacent display devices 600 The gap distance between 604 can be perceived by the viewer. On the contrary, if the extending protrusion 613 is not adjacent to another display device 600 in the array of display devices 600 , the image quality of the array of display devices 600 will not be limited by the extending protrusion 613 .

In this embodiment, the driver chip 612 is located on the same side of the substrate 602 as the array 604, and it is electrically connected to the array 604 through a trace wire 616a, wherein the driver chip 612 is directly soldered to the trace wire 616a. This method of placing chips is known as chip-on-glass (COG). The driver chip 612 can be electrically connected to an external circuit (not shown) through trace wires 616b connected to a mounting point 624 (eg, flex cable or other polymer film to conductors and insulators or soldered leads). Other die bonding methods may also be used including, but not limited to, flex film/chip-on-foil (COF), tape automated bonding (TAB), or any other flex-type bonding method.

A seal 606, here depicted as a ring seal, is located on the substrate 602 and surrounds the perimeter of the array 604, under which traces 616a and 616c are routed. Seal 606 may be referred to as a seal ring because, in various embodiments, seal 606 completely surrounds array 604 . Seal 606 may be a semi-hermetic seal, such as a conventional epoxy-based adhesive. In other embodiments, seal 606 may be PIB, O-ring, polyurethane, liquid spin-on-glass, solder, polymer, or plastic, among other types of seals. In other embodiments, the seal 606 may be a hermetic seal, such as thin film solder metal or glass frit. In one embodiment, the seal 606 has a width of 1.3 mm to 1.5 mm.

Still referring to FIG. 8 , backplate 608 , together with at least seal 606 and transparent substrate 602 , forms a protective chamber surrounding interferometric modulator array 604 . Although not shown, a desiccant may be provided within the protective chamber to prevent the accumulation of moisture related to the life of the device. Backplane 608 may be made of any suitable material, either transparent or opaque or conductive or insulating. Suitable materials for the backsheet 608 include, but are not limited to, glass (e.g., float glass, 1737, soda lime), plastics, ceramics, polymers, laminates, and metals and foils (e.g., stainless steel (SS302 , SS410), Kovar alloy (Kovar), electroplated Kovar alloy). Contrary to LCDs, which require electrode arrays on both substrates, array 604 resides on only one substrate, allowing backplane 608 to be made of a thinner material and/or a material completely different from that used in transparent substrate 602. production. In one embodiment, the backplate 608 is adapted to prevent moisture from entering the protective chamber and damaging the array 604 . Thus, a component such as backplate 608 provides a means for protecting array 604 from moisture and other environmental contaminants.

The display also includes a printed circuit (PC) bracket 610 on the side of the backplane 608 opposite the transparent substrate 602 . PC bracket 610 may be a PC bracket/component stack-up for a display product such as a personal digital assistant (PDA) or a cell phone. PC bracket 610 may be manufactured separately from backplane 608 and then soldered to the backplane.

In order to reduce the occupied area of the interferometric modulator display device 600, another arrangement for the driver chip 614 is shown, wherein the driver chip 614 is located on the upper side of the PC bracket 610, and is connected by trace wires 616c, 616d, solder Pads 625 and electrical connectors 618 (depicted as soldered leads) are electrically connected to array 604 . Since the driver chip 614 is not located on the substrate 602, the protruding area 619 can be reduced. By reducing the protruding area 619 of the display device 600 , the image quality of a larger display comprising an array of display devices 600 disposed together near at least one protruding portion 619 is improved. This improvement in image quality results from the reduction in the gap distance between the interferometric modulators 604 of adjacent display devices in the array.

The reduced protruding portion 619 of the transparent substrate 602 includes an electrical connection area including a pad 625 (eg, for soldering leads) connected to the trace wire 616c. In an exemplary embodiment, the use of solder leads such as the electrical connector 618 allows the protruding area 619 to be reduced to less than or equal to 1.5 millimeters, including but not limited to 1.25, 1.0, 0.75, 0.5, 0.25, 0.2, 0.1 , 0.075, 0.05, 0.025, 0.01, 0.0075, 0.005, 0.0025, 0.001, 0.0005 and 0.0001 mm.

Using pads 625 and electrical connectors 618 (depicted as solder leads in this embodiment), wires 616c extend from substrate 602 to PC tray 610, where wires 616c are in electrical communication with wires 616d. In this embodiment, wires 616c extend to PC tray 610 in the form of wires 616d (where chip bonding techniques such as COG, TAB, or COF may be used) to place array 604 in contact with a driver chip 614 or other connection to The electrical components of the PC tray 610 are in electrical communication.

Although pads 625 and electrical connectors 618 are illustrated through the use of solder leads, any type of connection arrangement that allows for a reduced protruding area 619 is encompassed by the present invention. For example, one skilled in the art could replace the pads 625 with a flex cable connector and replace the electrical connector 618 with a flex cable, yet still provide a value less than or equal to 5, 4, 3, 2, 1, 0.75, 0.5, 0.25, or 0.1 The reduced protrusion area 619 of mm.

Electrical connectors 618 are mounted to PC bracket 610 and transparent substrate 602 to provide electrical communication between PC bracket 610 and devices on transparent substrate 602 . The driving chip 614 can be electrically connected with external circuits through the trace wires 616e and the interconnection pins 622 . COG, COF or TAB methods can also be used in these examples. PC bracket 610 also provides physical support for additional electronic components 620 (e.g., ICs and passive circuits) that may be connected to external circuitry via external interconnect pins 622 and trace wires 616f, or via The trace wire 616g is connected to the driver chip 614 . Certain of these electronic components, such as driver chips 612 and 614 , provide a means for controlling the state of the modulators within array 604 .

PC bracket 610 may be a single or multi-layer conductive polymer laminate board, which may be fabricated using any suitable technique. It may include one or more polymeric layers that provide structural support and/or insulation for one or more layers including patterned or unpatterned conductors. The conductors provide electrical connections between different components mounted on the surface. Because PC tray 610 may be a multilayer conductive polymer laminate, the interconnection is not limited to traces on the surface of the tray as depicted in FIG. interconnection.

While in the embodiment of FIG. 8 backplane 608 may provide a barrier from moisture transmission sufficient to protect array 604, in an alternate embodiment the function of backplane 608 is performed by bracket 610, allowing backplane 608 to be eliminated. In such embodiments, the bracket may advantageously comprise a material that minimizes or prevents moisture vapor transmission. The skilled artisan will appreciate that PC trays composed of FR4 will transmit water vapor at a relatively high rate. In some alternative embodiments, PC bracket 610 may be formed of or include gold-plated thin-film metal to enhance its impermeability to water. Other suitable materials for bracket 610 include, but are not limited to, ceramic, aluminum nitride, beryllium oxide, and aluminum oxide. The PC tray 610 may be formed from a board or a flexible sheet.

The PC tray 610 is used to support components associated with display operations. PC bracket 610 may be connected to an additional PC bracket that carries components related to the overall operation of the product, or provides physical and electrical support for these components as well. Accordingly, a component such as PC tray 610 provides means for supporting these electronic components. PC cradle 610 may include an electronic interface for use with radio frequency (RF) signals. Skilled artisans will understand that PC bracket 610 can be used not only to protect circuits integrated into the backplane, but also to enhance RF circuit needs as well. For example, a metal shield may be included for RF enhancement or protection. Antenna properties may also be incorporated into the PC cradle 610 or the interferometric modulator array 604, including but not limited to the use of metal backplates or metal covers as cell phone antennas.

Although only six trace wires 616a, c are shown for connecting the driver chips 612 and 614 to the array 604 for simplicity, it should be understood that, depending on the size of the array, more trace wires may be required for the driver chips to control the array 604 status. Similarly, while only three trace wires 616b, e are depicted for connecting the driver chip with external circuitry, certain embodiments may require a different number of input trace wires. Similarly, although trace wires are not depicted in this figure extending to the top or bottom of array 604 (relative to this figure) for simplicity, it will be understood that embodiments of the invention may use The configuration discussed is to provide electrical connections to any portion of the array 604 (eg, from driver circuits to provide row and column signals). Also, although the trace wires 616a,c are depicted as being connected to the array 604, the trace wires 616a,c may be connected to any device within the cavity formed by the annular seal 606.

Trace wires 616a, c (alternately and interchangeably referred to as conductive buses or electrical traces) may comprise electrical traces formed from conductive materials. The traces 616a, c may have a width between about 25 microns (μm) and 1 mm, eg, about 50 microns across both ends, and a thickness between about 0.1 microns (μm) and 1 micron (μm). However, larger or smaller dimensions are possible. In some embodiments, the trace wires 616a, c may comprise metal. Photolithography, electroplating and electroless plating techniques can be used to form trace wires. In some embodiments, metal-based pastes or silver pastes may be used. Other methods and materials can also be used to form the trace wires.

ACF materials can be conveniently employed to provide electrical interconnection between components, and they are commonly used to connect flex film connectors of TAB drivers to the display substrate. However, other connection methods may be used and in place of the exemplary embodiments disclosed in the drawings herein, including but not limited to zebra connectors, flex cables, bump bonds, wire bonds, and micromechanical pressure Conductors (eg, MEMS springs).

9 and 10 depict an exemplary reduced footprint display device 750 . As will be apparent from the following discussion, the reduction in footprint of the device 750 is due in part to a reduction in the size of one or more extension protrusions, such as protrusion 613 seen in FIG. The chip and connector assembly is located outside the protective chamber formed by the sealing ring. These components that were once located on the extension protrusion 613 may be located in the vertical direction of the reduced footprint display device 750 .

Figure 9 shows the device 750 in an assembled state and Figure 10 shows the device 750 in an exploded view. Referring to FIG. 9 , the device 750 includes a transparent substrate 754 sealed to a carrier 770 by a seal ring 764 . In this embodiment, bracket 770 acts as a backplane for device 750 .

Bracket 770 includes a first display circuit 756 electrically connected to a set of external interconnection pins 760 to connect display device 750 to external devices. In addition, a set of interconnecting wires 762b connects display circuitry 756 to a set of pads 773b and connects electrical connections 772 to pads 773b, depicted in this particular embodiment as solder leads. Electrical connections 772 provide electrical connections to internal components of device 750 and extend down to pads 773a on a reduced protrusion area 775 on transparent substrate 754 . Next, wires 762 a extend from pads 773 a on the reduced protrusion area 754 to internal components of the display device 750 . In this embodiment, reduced protrusion area 775 extends from the outer edge of seal ring 764 and the outer edge of substrate 754 . In an exemplary embodiment, the width of the reduced protrusion region 775 is less than 1.5 mm, including but not limited to 1.25, 1.0, 0.75, 0.5, 0.25, 0.2, 0.1, 0.075, 0.05, 0.025, 0.01, 0.0075, 0.005 , 0.0025, 0.001, 0.0005 and 0.0001 mm.

The use of electrical connection means 772 allows for a partial reduction in footprint due to the reduced protruding area 775 compared to the extended protruding area 613 depicted in FIG. 8 . With the reduced protruding area 775, the space between any adjacent display devices 750 in the array of display devices 750 is minimized, thereby improving image quality for larger arrays of display devices 750. For example, if two display devices 750 are placed together in an array such that the reduced protrusion regions 775 of the display devices 750 are adjacent, then the gap between the display devices 750 is smaller than when the protrusion regions are extended, as shown in FIG. 8 The middle extension protruding area 613 is depicted.

Referring to FIG. 10 , an exploded view of a display device 750 is shown, wherein internal components 780 of the display device on a transparent substrate 754 are in electrical communication with pads 761 on a bracket 770 . The pads 761 on the bracket 770 can be used to connect to any device of interest, eg a driver chip or a flex cable that can lead to a printed circuit board (PCB). In this embodiment, internal components 780 of device 750 are connected to wires 762a that can be connected to pads 773a. Pads 773a on substrate 754 are then connected to electrical connections 772 (depicted here as solder leads) which lead to pads 773b on bracket 770 . These pads 773b on the carrier are then connected to pads 761 via wires 762b. In this embodiment, the internal component 780 in electrical communication with the electrical connection 772 and pad 761 may be a component such as an interferometric light modulator, an array of interferometric light modulators, or any other component of interest including (but not limited to) sensing means, lighting means or other display means such as LCD or LED. It should also be understood that some or all of the driver chips may be placed on the lower surface of the carrier 770 and thus inside the sealed cavity formed by the carrier 770 , the transparent substrate 754 and the sealing ring 764 .

Referring to FIG. 11A , a plurality of display devices 80 are arranged in an array that is tiled to form a larger display device 85 . The tiling process involves using multiple display devices to form a larger system. The tiling process is particularly useful for building larger displays and may be applicable where the largest display that can be produced is smaller than the desired display size. For example, billboards or other signage are often too large to be made from a single sheet of glass and the price of making a large sheet of glass can be quite high. Tiling can therefore be used to fill this space and advantageously is a less expensive alternative.

Displays are designed so that individual pixels are barely visible at the distances at which they are typically viewed. Televisions, laptop computers, and other devices are designed to have spatial frequencies of 10 to 20 cpd. Spatial frequencies around 80 cpd are invisible to the best human eye. As a result, a distance between active display areas of about one-eighth to one-tenth of the pixel pitch ensures a spatial frequency greater than 80 cpd for all applications. The pixel pitch is related to the resolution of the display. For example, a 1 pixel per inch (ppi) display has a pixel pitch of 25.4 millimeters. When tiles are constructed correctly, the spacing between active areas should be imperceptible to the eye. For example, if the spacing between active areas is between about one-eighth and one-tenth of a pixel pitch, the gaps between active areas are indistinguishable to the naked eye.

Various types of display technologies can be tiled together into a larger array using the techniques disclosed herein, including but not limited to Liquid Crystal Displays (LCDs), Organic Light Emitting Diodes (OLEDs), Light Emitting Diodes (LEDs) , field emission displays (FED), electrophoretic displays, and MEMS including interferometric light modulators. Additionally, the tiling techniques disclosed herein are applicable to other types of techniques that require minimizing the distance between active regions within an array. For example, the techniques taught herein can be applied to imaging sensors such as X-ray, complementary metal-oxide-semiconductor (CMOS), common channel signaling (CCS), infrared, and ultraviolet (UV) sensors. If the technology is more constrained in the footprint size of the device (x, y dimensions) compared to the vertical dimension (z), then the use of reduced overhang area for interconnects as described in Figures 8-10 can be useful.

As used herein, active area is defined in its broadest general sense, including, but not limited to, the area of the device surrounded by a seal. In some embodiments, the active area is the area surrounded by the annular seal where electrical connection to the active area is required. For example, in some embodiments, an active area is an area of a display device where a viewer of a display device can observe an image, an area of a device where light enters or reflects from or is projected from the device, or other forms of information (such as imaging-sensing information ) into or out of the device area of the device. In another embodiment, the active area is an array of interferometric light modulators of a display device. In another embodiment, the active area is a sensor array of a sensing device.

Referring to FIG. 11A , a top view of a tiled array of 16 display devices 80 is shown. Each display device 80 includes an active area 100, several packaging and interconnection areas 110, an inactive area 101 between the active areas 100 of the array, a backplane 120 on the active area 100, and an electrical connection means 125 (herein are depicted as solder leads). In one embodiment, the active area 100 of each display device 80 is a plurality of interferometric light modulators. The electrical connections 125 connect components within the display device 80 , such as the active area 100 , to electrical components on the backplane 120 . In one embodiment, connecting means connect the array to a driver chip.

In one embodiment, each display device 80 is controlled by its own local driver circuit. In another embodiment, a global driver (not shown) controls each local driver so that all display devices 80 operate in unison. Once complete, the tiled display 85 can function substantially like a tiled display of a large display, eg, it can produce a single complete image. Furthermore, because the tiled display 85 is an array of multiple display devices 80, the array 85 has the added advantage of allowing composite or blended images to be displayed. Thus, in the exemplary embodiment, the array 85 of interferometric modulator display devices 80 are connected by a central controller device (not depicted) which will send the composite or hybrid desired portions of the image to produce a complete composite or blended image on a large tiled array 85. Accordingly, array 85 can display different images on each individual display device 80 . Alternatively, array 85 may display images across the border of adjacent display devices 80 to produce one or more larger images on array 85 .

Tiling of a single display device is particularly useful for producing larger format images, such as billboards and large televisions. In one embodiment, the array 85 of interferometric modulators 80 is controlled by a primary display driver that controls each individual display device (tile) within the array. Thus, a complete large format image can be displayed on the array 85 of interferometric modulator display devices 80 to produce a complete image on, for example, a billboard.

Alternatively, one or more display devices 80 within array 85 may display their respective images. For example, the tiled array 85 shown in FIG. 11A may have four separate images, where each image is displayed across four display devices 80 . Thus, several complete images can be displayed on one tiled array 85, up to the number of display devices 80 used, 16 in FIG. 11A. In an exemplary embodiment, array 85 includes a plurality of display devices 80 including from about 2 to about 20,000 display devices. In another exemplary embodiment, the tiled array 85 may contain from about 2 to about 17,000 display devices 80, including but not limited to 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192 and 16284. In another exemplary embodiment, the tiled array 85 may include from about 2 to about 1024 display devices 80, including but not limited to 4, 8, 16, 32, 64, 128, 256, and 512 . In another exemplary embodiment, the display device includes an interferometric modulator display device.

Referring to FIG. 11A , in one embodiment, the use of bonding wires allows for the reduction of inactive areas 101 between active areas 100 . In one embodiment, by using solder leads 125 to connect the active area 100 to a driver or PCB (not depicted) connected to the backplane 120, the inter-tile area 110 between adjacent display devices 80 is reduced, thereby improving Image quality of tiled array 85.

In embodiments including a reduced inter-tile area 110 and bonding leads 125, the bonding leads include at least one lead, although there may be multiple leads. In use, the solder leads may be attached in any manner effective to minimize the inactive area 101 in the inter-tile area 110 .

When the overhang area is minimized by using certain embodiments and methods described herein, electrical connections between components on a device substrate and components on a backplane above the substrate are attached in a vertical direction rather than a horizontal direction , thereby reducing the space between active areas of the device and improving the image quality of the device.

Referring to FIG. 11A , electrical connections between components on a device substrate and components on a backplane (such as solder leads 125 in FIG. 11A ) can be provided on one or more devices configured to couple to such electrical connections. on the protruding part of the connecting device. For example, as depicted at display device 80 in grid space (A, 1 ) in FIG. 11A , electrical connection device 125 is depicted on a single protrusion 123 . However, electrical connection means may be located on one or more protrusions on a device, such as depicted at grid space (C, 3) in FIG. 11A. Electrical connection means 125 may also be located on adjacent protrusions of display device 80, as depicted by space (D, 2), or on two parallel protrusions of display device 80, as depicted by space (D, 3). Furthermore, the electrical connection means 125 of adjacent display devices 80 may be parallel to each other, such as depicted by spaces (D, 2) and (D, 3). Many other configurations are possible.

Referring to FIG. 11B , an array of four display devices 142 is depicted, each display device having a reduced overhang region 130 where pads 146 connect to internal components of the display device 142 . The pads 146 are connected to bonding leads 144 leading to pads 143 on the backplane 141 . Pads 143 on backplane 141 are also connected to wires 147 that allow connection to other electronic devices such as a driver chip 140 or external interconnect pins/pads 145 . In this embodiment, when pads 146 are present on protrusions 130 that are not adjacent to another display device 142, as depicted for display devices 142 in spaces (B, 1) and (B, 2), Since there are no other display devices 142 adjacent to the protrusion 130, there is no need to reduce the protrusion 130. As long as the protrusions 130 are reduced for protrusions 130 adjacent to other display devices 142, such as in the display devices 142 at spaces (A,1) and (A,2), then the space between the active display areas is reduced And the image quality of the arrayed display device is improved.

12A and 12B are system block diagrams illustrating an embodiment of a display device 2040 . The display device 2040 can be, for example, a cellular phone or cell phone. However, the same components of display device 2040, or slight variations thereof, are also illustrative of various types of display devices, such as televisions or portable media players.

The display device 2040 includes a housing 2041 , a display 2030 , an antenna 2043 , a speaker 2045 , an input device 2048 and a microphone 2046 . The housing 2041 is typically fabricated by any of various manufacturing processes known to those skilled in the art, including injection molding and vacuum forming. Additionally, the housing 2041 may be made of any of a variety of materials including, but not limited to, plastic, metal, glass, rubber, and ceramic, or combinations thereof. In one embodiment, the housing 2041 includes a removable portion (not shown) that is interchangeable with other removable portions of a different color or containing different logos, pictures or symbols.

Display 2030 of exemplary display device 2040 may be any of a variety of displays, including bi-stable displays as described herein. In other embodiments, display 2030 includes a flat panel display, such as a plasma, EL, OLED, STN LCD or TFT LCD as described above; or a non-flat panel display, such as a CRT or other, as is well known to those skilled in the art Electron tube device. However, for purposes of describing this embodiment, display 2030 comprises an interferometric modulator display, as described herein.

Components of one embodiment of an exemplary display device 2040 are schematically illustrated in FIG. 12B. The illustrated exemplary display device 2040 includes a housing 2041 and may include additional components at least partially sealed within the housing 2041 . For example, in one embodiment, exemplary display device 2040 includes a network interface 2027 including an antenna 2043 coupled to a transceiver 2047 . The transceiver 2047 is connected to a processor 2021 connected to conditioning hardware 2052 . The conditioning hardware 2052 may be configured to condition a signal (eg, filter the signal). Conditioning hardware 2052 is connected to a speaker 2045 and a microphone 2046 . The processor 2021 is further connected to an input device 2048 and a drive controller 2029 . The driver controller 2029 is coupled to a frame buffer 2028 and the array driver 2022 , and the array driver 2022 is coupled to a display array 2030 . A power supply 2050 provides power to all components according to the design requirements of that particular exemplary display device 2040 .

The network interface 2027 includes an antenna 2043 and a transceiver 2047 so that the exemplary display device 2040 can communicate with one or more devices through a network. In one embodiment, the network interface 2027 may also have some processing functions to relieve the requirements on the processor 2021 . The antenna 2043 is any antenna known to those skilled in the art for transmitting and receiving signals. In one embodiment, the antenna transmits and receives RF signals according to IEEE 802.11 standards, including IEEE 802.11(a), (b) or (g). In another embodiment, the antenna transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna is designed to receive CDMA, GSM, AMPS or other known signals for communication within a wireless cellular telephone network. Transceiver 2047 pre-processes signals received from antenna 2043 so that they may be received by processor 2021 and further processed. Transceiver 2047 also processes signals received from processor 2021 so that they can be transmitted from exemplary display device 2040 via antenna 2043 .

In an alternate embodiment, the transceiver 2047 may be replaced by a receiver. In another alternative embodiment, the network interface 2027 can be replaced by an image source that can store or generate image data to be sent to the processor 2021 . For example, the image source may be a digital video disc (DVD) or a hard drive containing image data or a software module that generates image data.

The processor 2021 generally controls the overall operation of the exemplary display device 2040 . Processor 2021 receives data, such as compressed image data, from network interface 2027 or an image source, and processes the data into raw image data or into a format that is easily processed into raw image data. Then, the processor 2021 sends the processed data to the drive controller 2029 or to the frame buffer 2028 for storage. Raw data generally refers to information that identifies image features at each location within an image. For example, these image characteristics may include color, saturation, and grayscale.

In one embodiment, the processor 2021 includes a microprocessor, a CPU or a logic unit for controlling the operation of the exemplary display device 2040 . Conditioning hardware 2052 typically includes amplifiers and filters for transmitting signals to speaker 2045 and receiving signals from microphone 2046 . Conditioning hardware 2052 may be a discrete component within exemplary display device 2040, or may be incorporated within processor 2021 or other components.

The drive controller 2029 receives the raw image data generated by the processor 2021 directly from the processor 2021 or from the frame buffer 2028 , and properly reformats the raw image data for high-speed transmission to the array driver 2022 . Specifically, the drive controller 2029 reformats the raw image data into a data stream having a raster-like format such that it has a time sequence suitable for scanning the entire display array 2030 . Then the drive controller 2029 sends the formatted information to the array driver 2022 . Although a driver controller 2029 (eg, an LCD controller) is typically associated with the system processor 2021 as a separate integrated circuit (IC), these controllers can be implemented in a variety of ways. It can be embedded in the processor 2021 as hardware, embedded in the processor 2021 as software, or fully integrated with the array driver 2022 in the form of hardware.

Typically, the array driver 2022 receives formatted information from the driver controller 2029 and reformats the video data into a set of parallel waveforms that are applied to the x-y pixel matrix from the display multiple times per second hundreds and sometimes thousands of leads.

In one embodiment, drive controller 2029, array driver 2022, and display array 2030 are suitable for any type of display described herein. For example, in one embodiment, the drive controller 2029 is a conventional display controller or a bi-stable display controller (eg, an interferometric modulator controller). In another embodiment, the array driver 2022 is a conventional driver or a bi-stable display driver (eg, an interferometric modulator display). In one embodiment, a driver controller 2029 is integrated with the array driver 2022 . This embodiment is common in highly integrated systems such as cellular phones, watches, and other small area displays. In yet another embodiment, the display array 2030 is a typical display array or a bi-stable display array (eg, a display including an array of interferometric modulators).

Input device 2048 allows a user to control the operation of exemplary display device 2040 . In one embodiment, the input device 2048 includes a keypad (eg, QWERTY keyboard or telephone keypad), a button, a switch, a touch screen, a pressure sensitive or heat sensitive film. In one embodiment, the microphone 2046 is an input device for the exemplary display device 2040 . Voice commands may be provided by the user to control the operation of the exemplary display device 2040 when the microphone 2046 is used to input data into the device.

Power supply 2050 may include various energy storage devices well known in the art. For example, in one embodiment, the power source 2050 is a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In another embodiment, the power source 2050 is a renewable energy source, a capacitor, or a solar cell including plastic solar cells and solar cell paint. In another embodiment, the power supply 2050 is configured to receive power from a wall outlet.

As noted above, in some implementations, control programmability resides in a driver controller, which may be located at several locations in the electronic display system. In some cases, control programmability exists in array driver 2022 . Those skilled in the art will appreciate that the optimization scenarios described above may be implemented with any number of hardware and/or software components and in various configurations.

While the foregoing detailed description has shown, described, and pointed out the novel features of the invention as applied to various embodiments, it should be understood that those skilled in the art may make further modifications to the illustrated devices or devices without departing from the spirit of the invention. Various omissions, substitutions and changes are made in the form and details of processing. It should be understood that the invention may be implemented in a form that does not provide all of the features and benefits described herein, because certain features may be used or implemented independently of other features.

Claims (36)

1. A device array comprising: A first device comprising: A package comprising a first substrate, a first active area, and a first electrical connection area, wherein the first electrical connection area is configured to provide a connection between the first active area and another component electrical connection; a sealing ring surrounding said first active area; a base plate bonded to the seal ring to form the package, and a conductor for providing electrical communication from said base plate to said first electrical connection area; and A second device comprising a second substrate, a second active area, and a second electrical connection area, the second device being positioned adjacent to the first electrical connection area of the first device place, Wherein the first electrical connection region extends from the sealing ring to an edge of the first substrate closest to the second device, and the distance between the edge and the second device is less than or equal to 1 mm. 2. The device array of claim 1, wherein the first electrical connection area is configured to provide electrical communication with the first active area via a solder wire. 3. The device array of claim 1, wherein a distance between the first active area and the second active area is less than or equal to one-eighth of a pixel pitch. 4. The device array of claim 1, wherein the first and second devices are display devices. 5. The device array of claim 4, wherein the display device array comprises at least one interferometric light modulator. 6. The device array of claim 5, wherein the first active area and the second active area each comprise at least one interferometric light modulator. 7. The device array of claim 4, wherein the display device array is configured to display a single image. 8. The device array of claim 4, wherein the display device array is configured to display multiple images simultaneously. 9. The device array of claim 4, wherein the display device comprises at least one of the following: a liquid crystal display, an organic light emitting diode, a light emitting diode, a field emission display, an electrocolor display, or an electrophoretic monitor. 10. The device array of claim 1, wherein each of the first and second devices comprises one of the following imaging sensing devices: an X-ray sensor, a CMOS sensor, a common A channel signaling sensor, an infrared sensor or an ultraviolet sensor. 11. The device array of claim 1 , wherein the first electrical connection region extends from the seal ring to an edge of the first substrate closest to the second device, the edge being connected to the The distance of the second means is less than or equal to 0.75 mm. 12. The device array of claim 1 , wherein the first electrical connection region extends from the seal ring to an edge of the first substrate closest to the second device, the edge being connected to the The distance of the second means is less than or equal to 0.5 mm. 13. The device array of claim 1 , wherein the first electrical connection region extends from the seal ring to an edge of the first substrate closest to the second device, the edge being connected to the The distance of the second means is less than or equal to 0.25 mm. 14. The device array of claim 1 , wherein the first electrical connection region extends from the seal ring to an edge of the first substrate closest to the second device, the edge being connected to the The distance of the second means is less than or equal to 0.1 mm. 15. The device array of claim 1, wherein the backplane comprises a printed circuit board. 16. The device array of claim 1, further comprising: a processor in electrical communication with the first active region, the processor configured to process image data; and A storage device in electrical communication with the processor. 17. The device array of claim 16, further comprising a driver circuit configured to send at least one signal to the first active area. 18. The device array of claim 17, further comprising: A controller configured to send at least a portion of the image data to the driver circuit. 19. The device array of claim 16, further comprising an image source module configured to send the image data to the processor. 20. The device array of claim 19, wherein the image source module comprises at least one of a receiver, transceiver and transmitter. 21. The device array of claim 16, further comprising an input device configured to receive input data and communicate the input data to the processor. 22. A method of manufacturing an array of display devices comprising: A first display device is provided, comprising: A display package comprising a first substrate, a first active area, and a first electrical connection area, wherein the first electrical connection area is configured to be provided between the first active area and another component electrical connection; a sealing ring surrounding said first active area; a base plate bonded to the seal ring to form the display package; and a conductor for providing electrical communication from said base plate to said first electrical connection area; and providing a second display device comprising a second substrate, a second active region and a second electrical connection region; and placing the first display device and the second display device together such that the second active area of the second display device is adjacent to the first electrical connection area of the first display device , wherein the first electrical connection region extends from the sealing ring to an edge of the substrate closest to the second device, the distance between the edge and the second device being less than or equal to 1 mm. 23. The method of claim 22, wherein a distance between the first active area and the second active area is less than or equal to one-eighth of a pixel pitch. 24. The method of claim 22, wherein the first electrical connection area is configured to provide electrical communication via a solder wire. 25. The method of claim 22, wherein the array of display devices comprises at least one interferometric light modulator. 26. The method of claim 25, wherein each of the first active area and the second active area comprises at least one interferometric light modulator. 27. An array of display devices made according to the method of claim 22. 28. A device array comprising: A first device comprising: a first transmission member for transmitting light therethrough; a first movable member for modulating light transmitted through said first transmission member; a first electrical connection member for providing electrical communication between said first movable member and another component; a sealing member for surrounding said first movable member; a covering member for forming the first transmission member, the first movable member, and the sealing member into a package; and an electrical connection member for providing electrical communication from said cover member to said first electrical connection member; and A second device comprising a second transmissive member for transmitting light therethrough, a second movable member for reflecting light, and a second electrical connection member, said second device being positioned in relation to said adjacent to the electrical connection member of the first device, wherein the first electrical connection member extends between the sealing member and the edge of the first transmissive member closest to the second device, the The distance between the edge and the second device is less than or equal to 1 mm. 29. The device array of claim 28, wherein the first transmissive member comprises a transparent substrate. 30. The device array of claim 28, wherein the first movable member comprises an array of interferometric modulators. 31. The device array of claim 28, wherein the first electrical connection means comprises an electrical connection area of the first device. 32. The device array of claim 28, wherein the sealing member comprises a sealant. 33. The device array of claim 28, wherein the cover member comprises a base plate. 34. The device array of claim 28, wherein the second movable member comprises an array of interferometric modulators. 35. The device array of claim 28, wherein the first electrical connection member is configured to provide electrical communication with the first movable member via a solder lead. 36. The device array of claim 28, wherein a distance between the first movable member and the second movable member is less than or equal to one-eighth of a pixel pitch. 37. The device array of claim 28, wherein the device array comprises an array of display devices.

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