CN100521203C - Display device - Google Patents

Abstract

A display capable of inhibiting a transistor from an instable operation resulting from fluctuation of the potential of a shielding film and suppressing occurrence of a malfunction is provided. This display comprises a first region including a first transistor, a first shielding film provided on the first region, arranged on a region corresponding to the first transistor and supplied with a first potential, a second region including a second transistor and a second shielding film provided on the second region, arranged on a region corresponding to the second transistor and supplied with a second potential.

Description

Display unit

Technical field

The present invention relates to a kind of display unit, especially relate to a kind of transistorized display unit that comprises.

Background technology

Known in the past liquid crystal indicator or organic EL display etc. comprise transistorized display unit.In this existing display unit, in pixel portions transistor is set, simultaneously, transistor is set also in the peripheral circuit portion that is disposed at the pixel portions periphery.In this existing display unit, incide under the transistorized situation when outer light or from the light of the backlight that constitutes display unit, the light of this incident sometimes can be in transistorized active layer stimulated carrier.At this moment, even transistor is being remained under the situation of cut-off state, the charge carrier that also can produce because of excitation flows through faults such as electric current between transistorized source electrode-drain electrode.In order to eliminate this fault, former known following display unit promptly by the transistor that photomask covers pixel portions and peripheral circuit portion is set, prevents that light from inciding transistor.This display unit for example is disclosed in the spy and opens in the flat 10-189999 communique.In addition, in this display unit, because the gate electrode that the photomask of covering transistor plays a part not expect, so under the situation of the potential change of photomask, transistorized threshold voltage change.Therefore, produce faults such as transistorized action instability.Therefore, open in the flat 10-189999 communique, in order to suppress this fault, the current potential of photomask is fixed as earthing potential above-mentioned spy.

Open in the flat 10-189999 communique in the disclosed display unit above-mentioned spy, to the drain region of the transistor that is arranged at pixel portions, provide under the situation of different signal potential with the drain region of the transistor that is arranged at peripheral circuit portion, owing to put on the electric field that the signal potential of drain region produces, even at transistor is under the situation of cut-off state, be arranged on sometimes pixel portions transistor channel region current potential, can change respectively with the current potential of the channel region of the transistor that is arranged on peripheral circuit portion and to be different current potentials.At this moment, applying under the situation of common earthing potential to photomask corresponding to the whole transistors that are arranged on pixel portions and peripheral circuit portion, the potential difference of the channel region current potential of the earthing potential of photomask and the transistor of pixel portions, different with the earthing potential of photomask with the potential difference of the channel region current potential of the transistor of peripheral circuit portion, so the potential difference of the channel region current potential of the transistor of the earthing potential of photomask and pixel portions sometimes, can surpass transistorized threshold voltage with the potential difference either party of the channel region current potential of the transistor of the earthing potential of photomask and peripheral circuit portion.At this moment, even this transistor is being remained under the situation of cut-off state, also have because of earthing potential, fault such as this transistor turns sometimes are provided to photomask.As a result, the problems such as situation that have the action defective that produces display unit.

Summary of the invention

The present invention makes in order to address the above problem, and one object of the present invention is to provide a kind of display unit, and it is unstable because of the potential change of photomask to suppress transistorized action, and, suppress to produce the action defective.

To achieve these goals, the display unit of one aspect of the present invention is characterised in that to possess: the first area, have the function of regulation, and simultaneously, comprise the first transistor; First photomask is arranged in the first area, simultaneously, is disposed in the zone corresponding to the first transistor, is provided first current potential; Second area has the function of regulation, simultaneously, comprises transistor seconds; With second photomask, be arranged in the second area, simultaneously, be disposed in the zone corresponding to transistor seconds, be provided second current potential.

In this display unit on the one hand, as above, provide first current potential by first photomask in being disposed at the zone corresponding with the first transistor, and, second photomask in being disposed at the zone corresponding with transistor seconds provides second current potential, the current potential of first and second photomasks can be separately fixed at first and second current potentials.Thus, because the current potential of first and second photomasks does not change, change along with the potential change of first and second photomasks so can suppress the first and second transistorized threshold voltages.Therefore, can make the first and second transistorized actions stable.In addition, by when first photomask that is arranged at the first area provides first current potential, provide second current potential to second photomask that is arranged at second area, can provide current potential separately to first photomask and second photomask that are arranged in first and second zones that have predetermined function respectively.Thus, for example under the first and second transistorized cut-off states, owing to apply different current potentials respectively to the first and second transistor drain zones, the current potential that is contained in the channel region of the first transistor in the first area becomes under the situation of different value with the current potential that is contained in the channel region of the transistor seconds in the second area, regulate first current potential that offers first photomask by current potential, can make potential difference between the channel region of first photomask and the first transistor be no more than the threshold voltage of the first transistor corresponding to the channel region of the first transistor.In addition, regulate second current potential that offers second photomask, can make potential difference between the channel region of second photomask and transistor seconds be no more than the threshold voltage of transistor seconds by current potential corresponding to the channel region of transistor seconds.Therefore because can be suppressed under first and second photomasks provide the situation of first current potential and second current potential respectively, by the time the first transistor and transistor seconds also become conducting state, so can suppress the action failure of display unit.In addition, by first photomask that offers first current potential is set in having the first area of predetermined function, simultaneously, second photomask that second current potential is provided is set in having the second area of predetermined function, with photomask is set in each transistor, simultaneously provides the situation of regulation current potential to compare separately to each of this photomask, can make to photomask provides the quantity such as wiring of current potential to reduce, and therefore, can suppress the space with regard to this part and increase.Thus, can suppress display unit maximizes.

With regard to the display unit of above-mentioned one side, the first area that preferably comprises the first transistor comprises first circuit part with predetermined function, and the second area that comprises transistor seconds comprises the second circuit portion with predetermined function.Constitute if so, then with regard to regard to the first transistor being set in having first circuit part of predetermined function and having the display unit that transistor seconds is set in the second circuit portion of predetermined function, can be easily provide current potential separately to being arranged on first circuit part that has predetermined function respectively and first photomask in the second circuit portion and second photomask.

At this moment, preferred first circuit part comprises the pixel portions with the first transistor, second circuit portion comprises peripheral circuit portion, be arranged on the periphery of the display part that comprises pixel portions, has transistor seconds, first photomask comprises the pixel portions photomask that is disposed at the first transistor below that comprises in the pixel portions, and second photomask comprises the peripheral circuit portion photomask that is disposed at the transistor seconds below that comprises in the peripheral circuit portion.Constitute if so, then for example under the first and second transistorized cut-off states, when owing to apply different potentials respectively to the first and second transistor drain zones, be contained in the current potential of the channel region of the first transistor in the pixel portions, with the current potential of the channel region that is contained in the transistor seconds in the peripheral circuit portion be under the situation of different value, regulate first current potential that offers the pixel portions photomask by current potential, can make potential difference between the channel region of pixel portions photomask and the first transistor be no more than the threshold voltage of the first transistor corresponding to the channel region of the first transistor.In addition, regulate second current potential that offers the peripheral circuit portion photomask by current potential, can make potential difference between the channel region of peripheral circuit portion photomask and transistor seconds be no more than the threshold voltage of transistor seconds corresponding to the channel region of transistor seconds.Thus, with regard to pixel portions and peripheral circuit portion, can be suppressed at respectively under pixel portions photomask and peripheral circuit portion photomask provide the situation of first and second current potentials respectively, by the time first and second transistors also become conducting state.

With regard to the formation that comprises above-mentioned pixel portions photomask, first current potential that preferably offers the pixel portions photomask be with the gate electrode that puts on corresponding the first transistor on the identical current potential of current potential.Constitute if so, then apply under the situation of the regulation current potential that the first transistor is become cut-off state at the gate electrode to the first transistor, first current potential that puts on the pixel portions photomask also becomes the current potential that the first transistor is become cut-off state.Thus, can be suppressed at by apply the afore mentioned rules current potential to gate electrode when the first transistor of pixel portions remained cut-off state, the first transistor is because of providing the first current potential conducting to the pixel portions photomask.In addition, by apply to the pixel portions photomask with the gate electrode that puts on corresponding the first transistor on first current potential of current potential same potential, can make the pixel portions photomask also play the use of the grid of the first transistor, so can use the gate electrode of the first transistor and pixel portions photomask both sides to drive the first transistor.Thus, the driving force of the first transistor is improved.

At this moment, preferred pixel portion photomask is electrically connected on the gate electrode of the first transistor.Constitute if so, then can be easily to the pixel portions photomask apply with the gate electrode that puts on corresponding the first transistor on the identical current potential of current potential.

With regard to the formation that comprises above-mentioned pixel portions photomask, first current potential that preferably offers the pixel portions photomask be with one of the source region that puts on corresponding the first transistor and drain region on the identical current potential of current potential.Constitute if so, then the current potential of the channel region of the first transistor is the current potential that puts in the variation voltage range of the current potential on one of source region and drain region, and be with put on one of this source region and drain region on the corresponding current potential of current potential.Thus, by applying to the pixel portions photomask and the first identical current potential of current potential on one of the source region that puts on the first transistor and drain region, the potential difference between the channel region of pixel portions photomask and the first transistor can be controlled in the voltage range of regulation.Thus, if the potential difference between the channel region of pixel portions photomask and the first transistor is controlled in the voltage range of cut-off region of the first transistor, then can easily suppress since to the pixel portions photomask apply first current potential, the first transistor conducting when the first transistor of pixel portions ends.

At this moment, preferred pixel portion photomask is electrically connected on one of the source region of the first transistor and drain region.Constitute if so, then can be easily to the pixel portions photomask apply with one of the source region that puts on the first transistor and drain region on the identical current potential of current potential.

With regard to the formation that above-mentioned first circuit part comprises pixel portions, preferred pixel portion comprises the p channel transistor, and first current potential that offers the pixel portions photomask of the p channel transistor below that is disposed at pixel portions is the positive side current potential that puts on the drain region of p channel transistor.Constitute if so, then the current potential of the channel region of p channel transistor is corresponding to the current potential in the prescribed limit of the positive side current potential of drain region.Thus, by apply to the pixel portions photomask with the drain region that puts on the p channel transistor on the first identical current potential of positive side current potential, the potential difference between the channel region of pixel portions photomask and p channel transistor can be controlled in the voltage range of regulation.Thus, if the potential difference between the channel region of pixel portions photomask and p channel transistor is controlled in the voltage range of cut-off region of p channel transistor, then can easily control because of first current potential (positive side current potential) is provided to the pixel portions photomask, when the p of pixel portions channel transistor ends, the p channel transistor conducting of pixel portions.

With regard to the formation that above-mentioned first circuit part comprises pixel portions, preferred pixel portion comprises a plurality of the first transistors, at least one of a plurality of the first transistors of pixel portions plays switch element, and configuration pixel portions photomask is with the below of the first transistor that covered the switch element effect at least.Constitute if so, then for example by configuration pixel portions photomask, below with the first transistor that only covered the switch element effect, with the first transistor that plays the switch element effect and the first transistor that does not play the switch element effect separately below dispose the pixel portions photomask respectively situation compare, can suppress to be used for to provide the wiring of current potential to twine and complicate to the pixel portions photomask.In addition, provide picture signal owing to controlling to pixel portions by the first transistor that plays the switch element effect, so if below the first transistor that plays the switch element effect configuration pixel portions photomask, then can suppress to produce leakage current, offer the fault of signal potential variation of the picture signal of pixel portions because of rayed.In addition, form as the first transistor that plays the switch element effect as the crystallizing layer of active layer the time, using laser to carry out under the situation of crystallization of crystallizing layer, even if because laser is reduced by the crystallinity of the reflection of pixel portions photomask, crystallizing layer (active layer), the characteristic that plays the first transistor of switch element effect also is difficult to depend on the crystallinity of crystallizing layer (active layer), descends so can reduce the characteristic of the first transistor of switch element effect.Therefore, if configuration pixel portions photomask is with the below of the first transistor that only covered the switch element effect, then but the limit suppresses to be used for to provide the wiring of current potential to twine to the pixel portions photomask and complicates, and the limit suppresses to come display image corresponding to the gray scale beyond the gray scale of the signal potential of picture signal.

With regard to the formation that above-mentioned first circuit part comprises pixel portions, preferred first circuit part comprises a plurality of pixel portions with the first transistor, is covered the below of a plurality of pixel portions the first transistor separately by a pixel portions photomask.Constitute if so, then with regard to first circuit part, with a plurality of the first transistors are being provided with the pixel portions photomask one by one, provide the situation of regulation current potential to compare respectively to these a plurality of pixel portions photomasks simultaneously, can make to the pixel portions photomask provides the quantity of the wiring etc. of current potential to reduce.Thus, the part that the quantity that can connect up reduces suppresses first circuit part and increases, and maximizes so can suppress display unit.

With regard to the formation that above-mentioned second circuit portion comprises peripheral circuit portion, preferred peripheral circuit portion comprises the p channel transistor at least, and the peripheral circuit portion photomask is configured in the below of p channel transistor at least.Constitute if so, then for example comprise under the situation of n channel transistor and p channel transistor in peripheral circuit portion, by disposing the peripheral circuit portion photomask only to cover the below of p channel transistor, with n channel transistor and p channel transistor separately below dispose the peripheral circuit portion photomask respectively situation compare, can suppress to be used for to the periphery circuit part's photomask provides the wiring of current potential to twine to complicate.Here, it is bigger than p channel transistor that the general n channel transistor constitutes carrier mobility, has the grid width littler than the grid width of p channel transistor thus.Thereby the n channel transistor is difficult to cause the misoperation that produces to active layer incident because of light with little this part of grid width.Therefore, even if do not dispose the peripheral circuit portion photomask below the n channel transistor, it is unstable that the action of peripheral circuit portion also is not easy to become.Therefore, if configuration peripheral circuit portion photomask is only covering the below of p channel transistor, but then the limit suppresses to be used for to the periphery circuit part's photomask and provides the wiring of current potential to twine to complicate, and the action that the limit suppresses peripheral circuit portion becomes unstable.

At this moment, preferred peripheral circuit portion also comprises the n channel transistor except that the p channel transistor, and the peripheral circuit portion photomask is configured in the below of n channel transistor and p channel transistor.Constitute if so, then can suppress the n channel transistor of peripheral circuit portion and p channel transistor both sides' action and become unstable.

With regard to the display unit of above-mentioned one side, preferably also possesses the first grid dielectric film of the first transistor with first thickness; First dielectric film is arranged between the first transistor and first photomask, has second thickness more than 3 times of first thickness of first grid dielectric film; Second grid dielectric film with transistor seconds of the 3rd thickness; With second dielectric film, be arranged between the transistor seconds and second photomask, have the 4th thickness more than 3 times of the 3rd thickness of second grid dielectric film.Constitute if so, then under the situation of the gate electrode that first photomask (second photomask) plays a part not expect, owing to formed first dielectric film (second dielectric film) of gate insulator membrane interaction with big thickness, so applying under the situation of first current potential (second current potential) to first photomask (second photomask), the channel region of the first transistor (transistor seconds) also is difficult to be subjected to the influence of the current potential of first photomask (second photomask).At this moment, by put on first current potential (second current potential) on first photomask (second photomask) offer the first transistor (transistor seconds) channel region effective voltage for when the gate electrode of the first transistor (transistor seconds) applies with first current potential (second current potential) same potential, offer channel region voltage roughly 1/3.Thus, can reduce the threshold voltage variation that applies the first transistor (transistor seconds) that first current potential (second current potential) causes to first photomask (second photomask).

At this moment, the preferred first grid dielectric film and first dielectric film are made of same material, and the second grid dielectric film and second dielectric film are made of same material.Constitute if so, then can make easily first current potential (second current potential) that puts on first photomask (second photomask) offer the first transistor (transistor seconds) channel region effective voltage for when the gate electrode of the first transistor (transistor seconds) applies with first current potential (second current potential) same potential, offer channel region voltage roughly 1/3.

With regard to the display unit of above-mentioned one side, preferred first current potential provides the current potential to the centre of the positive side current potential of the gate electrode of the first transistor and minus side current potential, and second current potential provides the current potential to the centre of the positive side current potential of the gate electrode of transistor seconds and minus side current potential.In addition, above-mentioned positive side current potential is meant the high potential that puts on the holding wire, and simultaneously, the minus side current potential is meant the electronegative potential that puts on the holding wire.In addition, the middle in fact current potential that also comprises positive side current potential and minus side current potential in the current potential of above-mentioned centre.Constitute if so, be under the situation of one of p channel transistor or n channel transistor then at first and second transistors, also can be easily will offer in the voltage range of cut-off region that potential difference between the channel region of first photomask of first current potential and the first transistor is controlled at the first transistor, simultaneously, will apply in the voltage range of cut-off region that potential difference between the drain region of second photomask of second current potential and transistor seconds is controlled at transistor seconds.Thus, be under the situation of one of p channel transistor and n channel transistor at the first transistor and transistor seconds, first and second transistor turns in the time of also can easily suppressing to end.In addition, by first and second current potentials are made as respectively the positive side current potential that offers the first and second transistorized gate electrodes and minus side current potential in fact in the middle of current potential, can use the positive side current potential and the minus side current potential that offer the first and second transistorized gate electrodes respectively, easily generate first and second current potentials.

At this moment, preferably also possess current potential generative circuit portion, be used to generate the intermediate potential of positive side current potential and minus side current potential.Constitute if so, then can easily generate the intermediate potential of positive side current potential and minus side current potential by current potential generative circuit portion.

Provide to the positive side current potential of the gate electrode of the first transistor and the intermediate potential of minus side current potential with regard to above-mentioned first current potential, second current potential provides the formation to the intermediate potential of the positive side current potential of the gate electrode of transistor seconds and minus side current potential, and at least one side of preferred first area and second area comprises n channel transistor and p channel transistor both sides.Constitute if so, then comprise under n channel transistor and p channel transistor both sides' the situation in the first area, apply the positive side current potential of gate electrode of the n channel transistor (p channel transistor) that offers the first area and the intermediate potential of minus side current potential by first photomask to the n channel transistor that is disposed at the first area and p channel transistor below, can easily the potential difference between the channel region of first photomask and n channel transistor be controlled in the voltage range of cut-off region of n channel transistor, simultaneously, the potential difference between the channel region of first photomask and p channel transistor is controlled in the voltage range of cut-off region of p channel transistor.In addition, comprise at second area under n channel transistor and p channel transistor both sides' the situation, apply the positive side current potential of gate electrode of the n channel transistor (p channel transistor) that offers second area and the intermediate potential of minus side current potential by second photomask to the n channel transistor that is disposed at second area and p channel transistor below, can easily the potential difference between the channel region of second photomask and n channel transistor be controlled in the voltage range of cut-off region of n channel transistor, simultaneously, the potential difference between the channel region of second photomask and p channel transistor is controlled in the voltage range of cut-off region of p channel transistor.

With regard to the display unit of above-mentioned one side, the first area that preferably comprises the first transistor is arranged on pixel portions with the second area that comprises transistor seconds, first photomask is configured in the below of the first transistor in the first area that is contained in pixel portions, and second photomask is configured in the below of the transistor seconds in the second area that is contained in pixel portions.Constitute if so, for example with regard to the cut-off state of the first transistor and transistor seconds, become under the situation of the value that has nothing in common with each other at the first transistor and the transistor seconds channel region current potential separately that apply different current potentials respectively because of drain region, be contained in the pixel portions to the first transistor and transistor seconds, regulate first current potential that offers first photomask by current potential, can make potential difference between the channel region of first photomask and the first transistor be no more than the threshold voltage of the first transistor corresponding to the channel region of the first transistor.In addition, regulate second current potential that offers second photomask, can make potential difference between the channel region of second photomask and transistor seconds be no more than the threshold voltage of transistor seconds by current potential corresponding to the channel region of transistor seconds.Thus, with regard to pixel portions, can be suppressed under first photomask and second photomask provide the situation of first current potential and second current potential respectively, by the time the first transistor and transistor seconds become conducting state.

At this moment, the first transistor of preferred first area and the transistor seconds of second area have the conduction type that has nothing in common with each other.Constitute if so, then comprise under the situation of the first transistor with the conduction type that has nothing in common with each other and transistor seconds in pixel portions, regulate first current potential that offers first photomask by current potential, can make potential difference between the channel region of first photomask and the first transistor be no more than the threshold voltage of the first transistor corresponding to the channel region of the first transistor.In addition, regulate second current potential that offers second photomask, can make potential difference between the channel region of second photomask and transistor seconds be no more than the threshold voltage of transistor seconds by current potential corresponding to the channel region of transistor seconds.

With regard to the display unit of above-mentioned one side, preferred first area comprises the pixel portions with the first transistor and has first peripheral circuit portion of the first transistor, second area comprises second peripheral circuit portion with transistor seconds, first photomask is configured in the first transistor that is contained in pixel portions and is contained in the below of the first transistor of first peripheral circuit portion, and second photomask is configured in the below of the transistor seconds that is contained in second peripheral circuit portion.Constitute if so, then for example under the cut-off state of the first transistor and transistor seconds, applying different potentials respectively because of drain region to the first transistor and transistor seconds, be contained in the current potential of the channel region of the first transistor in the pixel portions and first peripheral circuit portion, with the current potential of the channel region that is contained in the transistor seconds in second peripheral circuit portion be under the situation of different value, regulate first current potential that offers first photomask by current potential, can make potential difference between the channel region of first photomask and the first transistor be no more than the threshold voltage of the first transistor corresponding to the channel region of the first transistor.In addition, regulate second current potential that offers second photomask, can make potential difference between the channel region of second photomask and transistor seconds be no more than the threshold voltage of transistor seconds by current potential corresponding to the channel region of transistor seconds.Thus, with regard to pixel portions, first peripheral circuit portion and second peripheral circuit portion, can be suppressed under first photomask and second photomask provide the situation of first current potential and second current potential respectively, by the time the first transistor and transistor seconds become conducting state.

Description of drawings

Fig. 1 schematically illustrates the plane graph that the integral body of the liquid crystal indicator of first embodiment of the invention constitutes.

Fig. 2 is the circuit diagram of pixel portions of the liquid crystal indicator of first execution mode shown in Figure 1.

Fig. 3 is near the sectional view of the structure the n channel transistor of pixel portions of liquid crystal indicator of expression first execution mode shown in Figure 1.

Fig. 4-Fig. 7 is the voltage oscillogram of action of n channel transistor of pixel portions that is used to illustrate the liquid crystal indicator of first embodiment of the invention.

Fig. 8 is the figure of I-E characteristic of n channel transistor of pixel portions of the liquid crystal indicator of expression first embodiment of the invention.

Fig. 9-Figure 11 is the sectional view of manufacture process of n channel transistor of pixel portions that is used to illustrate the liquid crystal indicator of first embodiment of the invention.

Figure 12 is near the sectional view of the structure the n channel transistor of pixel portions of liquid crystal indicator of expression second embodiment of the invention.

Figure 13 is the voltage oscillogram of action of n channel transistor of pixel portions that is used to illustrate the liquid crystal indicator of second embodiment of the invention.

Figure 14 is the figure of I-E characteristic of n channel transistor of pixel portions of the liquid crystal indicator of expression second embodiment of the invention.

Figure 15 is near the sectional view of the structure the n channel transistor of pixel portions of liquid crystal indicator of expression third embodiment of the invention.

Figure 16 is the voltage oscillogram of action of n channel transistor of pixel portions that is used to illustrate the liquid crystal indicator of third embodiment of the invention.

Figure 17 is the figure of I-E characteristic of n channel transistor of pixel portions of the liquid crystal indicator of expression third embodiment of the invention.

Figure 18 is the circuit diagram of pixel portions of the organic EL display of four embodiment of the invention.

Figure 19-the 22nd is used to illustrate the voltage oscillogram of action of n channel transistor of pixel portions of the organic EL display of four embodiment of the invention.

Figure 23 is the figure of I-E characteristic of n channel transistor of pixel portions of the organic EL display of expression four embodiment of the invention.

Figure 24-Figure 27 is the voltage oscillogram of action of p channel transistor of pixel portions that is used to illustrate the organic EL display of four embodiment of the invention.

Figure 28 is the figure of I-E characteristic of p channel transistor of pixel portions of the organic EL display of expression four embodiment of the invention.

Figure 29 is the voltage oscillogram of action of n channel transistor of pixel portions that is used to illustrate the organic EL display of fifth embodiment of the invention.

Figure 30 is the figure of I-E characteristic of n channel transistor of pixel portions of the organic EL display of expression fifth embodiment of the invention.

Figure 31 is the voltage oscillogram of action of p channel transistor of pixel portions that is used to illustrate the organic EL display of fifth embodiment of the invention.

Figure 32 is the figure of I-E characteristic of p channel transistor of pixel portions of the organic EL display of expression fifth embodiment of the invention.

Figure 33 is the voltage oscillogram of action of n channel transistor of pixel portions that is used to illustrate the organic EL display of sixth embodiment of the invention.

Figure 34 is the figure of I-E characteristic of n channel transistor of pixel portions of the organic EL display of expression sixth embodiment of the invention.

Figure 35 is the voltage oscillogram of action of p channel transistor of pixel portions that is used to illustrate the organic EL display of sixth embodiment of the invention.

Figure 36 is the figure of I-E characteristic of p channel transistor of pixel portions of the organic EL display of expression sixth embodiment of the invention.

Figure 37 is the forming circuit figure of the cmos circuit that comprises in the peripheral circuit of liquid crystal indicator of expression eighth embodiment of the invention.

Figure 38 is the figure of the I-E characteristic of the cmos circuit that comprises in the peripheral circuit of liquid crystal indicator of expression eighth embodiment of the invention.

Figure 39 be the expression current potential that puts on photomask, with correlation diagram corresponding to the relation of the threshold voltage vt h of the p channel transistor of this photomask and n channel transistor.

Figure 40 is the plane graph that the integral body of the organic EL display of expression ninth embodiment of the invention constitutes.

Figure 41 is the circuit diagram of pixel portions of the organic EL display of the 9th execution mode shown in Figure 40.

Figure 42 is the circuit diagram of the peripheral circuit diagram (analog switch) of the organic EL display of the 9th execution mode shown in Figure 40.

Figure 43 is the plane graph that the integral body of the organic EL display of expression tenth embodiment of the invention constitutes.

Figure 44 is the plane graph that the integral body of the organic EL display of expression eleventh embodiment of the invention constitutes.

Figure 45 is the plane graph that the integral body of the organic EL display of expression twelveth embodiment of the invention constitutes.

Embodiment

Below, with reference to accompanying drawing embodiments of the present invention are described.

(first execution mode)

The formation of the liquid crystal indicator of first execution mode at first, is described with reference to Fig. 1-Fig. 3.

The liquid crystal indicator of first execution mode possesses display panels 1 and is assemblied in external circuit portion 2 on the display panels 1 as shown in Figure 1.Display panels 1 comprises display part 3 and is arranged on the H series driver 4 and the V series driver 5 of display part 3 peripheries.In addition, in display part 3, be configured to a plurality of pixel portions 6 rectangular.In each pixel portions 6, the switch element portion 7 of configuration as the n channel transistor 8 of switch element is set.In addition, each pixel as shown in Figure 2, comprise counter electrode 11 shared in each pixel portions 6 of auxiliary capacitor 9, pixel electrode 10, pixel electrode 10 configurations relatively and be configured in pixel electrode 10 and counter electrode 11 between liquid crystal 12.In addition, pixel portions 6 is examples of ' first area ' of the present invention and ' first circuit part ', and n channel transistor 8 is examples of ' the first transistor ' of the present invention.

In addition, on the gate electrode 8a of n channel transistor 8, be connected with gate line.Apply positive side current potential Vdd and minus side current potential Vbb through this gate line to the gate electrode 8a of n channel transistor 8.In addition, when the drain region of n channel transistor 8 8b was connected on the drain line, source region 8c was connected in the electrode and the pixel electrode 10 of auxiliary capacitor 9.In addition, apply the signal potential Vsig of picture signal to the drain region of n channel transistor 8 8b through drain line.In addition, another electrode of auxiliary capacitor 9 and counter electrode 11 are connected on the shared common potential Vcom of each pixel portions 6.

In addition, as shown in Figure 1, in display part 3, be provided with display part photomask 13.The pixel portions lightproof area 13a that this display part photomask 13 is formed by the mode according to the below of the switch element portion 7 that covers pixel portions 6 and constitute according to the cancellate wiring lightproof area 13b of portion that the mode of covering gate polar curve and drain line below forms.In addition, this pixel portions lightproof area 13a is an example of ' first photomask ' of the present invention and ' pixel portions photomask '.Pixel portions lightproof area 13a is provided with shading to incide to be disposed at the light of n channel transistor 8 of the switch element portion 7 of pixel portions 6, and is integrally formed with the lightproof area 13b of wiring portion.In addition, the lightproof area 13b of wiring portion is provided with shading to incide the light of gate line and drain line.In addition, the regional corresponding regional opening beyond the switch element portion 7 display part photomask 13 and pixel portions 6.Constitute the light of the zone ejaculation display map behind the opening of this display part photomask 13.

In addition, the n channel transistor 8 that comprises in the pixel portions 6 is made of TFT (thin-film transistor), has structure shown in Figure 3.Particularly, on glass substrate 14, be formed with the resilient coating 15 that constitutes by dielectric film with about 300nm thickness.In the regulation zone on this resilient coating 15, be provided with the pixel portions lightproof area 13a of above-mentioned display part photomask 13.This display part photomask 13 is made of the Mo film with about 100nm thickness.In addition, on the pixel portions lightproof area 13a and resilient coating 15 of display part photomask 13, be formed with the dielectric film 16 that constitutes by SiO2 film, to cover pixel portions lightproof area 13a with about 300nm thickness.

In addition, in the regulation zone on dielectric film 16, form crystal silicon film 17 with about 70nm thickness.This crystal silicon film 17 has the function as the active layer of n channel transistor 8.In crystal silicon film 17, be formed with the channel region 8d of n channel transistor 8 and drain region 8b and the source region 8c that clamping channel region 8d is provided with.In addition, in n channel transistor 8, by crystal silicon film 17 is carried out channel doping, the threshold voltage vt h that constitutes n channel transistor 8 becomes the positive voltage of regulation.In addition, the positive threshold voltage vt h of this regulation is set to when the pixel portions lightproof area 13a to display part photomask 13 provides the current potential of 1/2 (Vdd+Vbb), the bottom raceway groove of n channel transistor 8 does not become the value of conducting state.In addition, form by SiO with about 100nm thickness ₂The gate insulating film 18 of the n channel transistor 8 that film constitutes is to cover crystal silicon film 17.

Promptly, in the first embodiment, constitute the pixel portions lightproof area 13a that is arranged on display part photomask 13, and crystal silicon film 17 between the thickness (being about 300nm) of dielectric film 16 be about 3 times of the thickness (about 100nm) of the gate insulating film 18 of n channel transistor 8.In addition, form under the situation of dielectric film 16 at the thickness with about 500nm, produce following fault sometimes, the process required time that promptly forms dielectric film 16 increases, or when film forming, in dielectric film 16, crack etc. because of the stress that in dielectric film 16, produces in the process after it.Shown in this first execution mode, form under the situation of dielectric film 16 at thickness with about 300nm, can suppress to produce above-mentioned fault.In addition, in the zone corresponding to channel region 8d on gate insulating film 18, form the gate electrode 8a that constitutes by metal film with about 150nm thickness.In addition, utilize the crystal silicon film 17, gate insulating film 18 and the gate electrode 8a that are formed with drain region 8b, source region 8c and channel region 8d, form n channel transistor 8 (TFT).

In addition, on gate electrode 8a and gate insulating film 18, cover gate electrode 8a ground is formed with dielectric film 19.In the zone corresponding to the drain region 8b of crystal silicon film 17 and source region 8c of this dielectric film 19 and gate insulating film 18, the plug connector 20a and the 20b that arrive on the dielectric film 19 are set respectively.In addition, drain region 8b constituted through the plug connector 20a of correspondence be connected on the above-mentioned drain line, simultaneously, source region 8c constituted through the plug connector 20b of correspondence be connected on the electrode and pixel electrode 10 of above-mentioned auxiliary capacitor 9.

In addition, in the zone corresponding to the pixel portions lightproof area 13a of display part photomask 13 of dielectric film 16 and gate insulating film 18, be provided with and run through the ground floor plug connector 21 that dielectric film 16 and gate insulating film 18 ground form.This ground floor plug connector 21 is connected to the pixel portions lightproof area 13a of display part photomask 13.In addition, in the zone on gate insulating film 18, the middle wiring layer 22 that is connected on the ground floor plug connector 21 is set corresponding to ground floor plug connector 21.In addition, in the zone corresponding to middle wiring layer 22 of dielectric film 19, form the second layer plug connector 23 that arrives on the dielectric film 19.Wiring layer 22 in the middle of this second layer plug connector 23 is connected in.In addition, in the zone on dielectric film 19, be provided with the wiring layer 24 that is connected on the second layer plug connector 23 corresponding to second layer plug connector 23.This wiring layer 24 constitutes the current potential generative circuit 39a of portion (with reference to Fig. 1) that is connected in external circuit described later portion 2.

In addition, H series driver 4 comprises shift-register circuit 25, sampling transistor (sampling transistor) 26, buffer 27 and DA transducer 28 as shown in Figure 1.In addition, with H series driver 4 adjacency ground configurable clock generator generation circuit 29.Shift-register circuit 25, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 are examples of ' second area ' of the present invention and ' peripheral circuit portion '.These shift-register circuits 25, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 have the n channel transistor that has much the same formation with the n channel transistor 8 of above-mentioned pixel portions 6 respectively.In addition, this n channel transistor is an example of ' transistor seconds ' of the present invention.Wherein, in this n channel transistor, provide positive side current potential Vdd and minus side current potential Vss, simultaneously, provide signal potential Vsig corresponding to each circuit part to the drain region to gate electrode.

In addition, in the first embodiment, be provided with shift-register circuit photomask 30, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34, to cover the below of shift-register circuit 25, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 respectively.This shift-register circuit photomask 30, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 are examples of ' second photomask ' of the present invention and ' peripheral circuit portion photomask '.In addition, utilize shift-register circuit photomask 30, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34, respectively the light of the n channel transistor incident that in each of shift-register circuit 25, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29, is provided with of shading.

In addition, V series driver 5 comprises shift-register circuit 35 and level-conversion circuit 36.This shift-register circuit 35 and level-conversion circuit 36 are examples of ' second area ' of the present invention and ' peripheral circuit portion '.In addition, shift-register circuit 35 and level-conversion circuit 36 have the n channel transistor that has much the same formation with the n channel transistor 8 of above-mentioned pixel portions 6 respectively.In addition, this n channel transistor is an example of ' transistor seconds ' of the present invention.Wherein, in the n channel transistor in being arranged at level-conversion circuit 36, provide positive side current potential Vdd and minus side current potential Vbb to gate electrode, on the other hand, in being arranged at the n channel transistor of shift-register circuit 35, provide positive side current potential Vdd and minus side current potential Vss to gate electrode.

In addition, in the first embodiment, shift-register circuit photomask 37 and level-conversion circuit photomask 38 are set, to cover the below of shift-register circuit 35 and level-conversion circuit 36 respectively.This shift-register circuit photomask 37 and level-conversion circuit photomask 38 are examples of ' second photomask ' of the present invention and ' peripheral circuit portion photomask '.In addition, utilize this shift-register circuit photomask 37 and level-conversion circuit photomask 38, respectively shading to shift-register circuit 35 and level-conversion circuit 36 separately in the light of n channel transistor incident of setting.

In addition, externally in the circuit part 2, be provided with current potential generative circuit 39a of portion and 39b.A current potential generative circuit 39a of portion has the function of the current potential that generates 1/2 (Vdd+Vbb), and simultaneously, another current potential generative circuit portion 39 has the function of the current potential that generates 1/2 (Vdd+Vss).

Here, in the first embodiment, the current potential generative circuit 39a of portion is connected on display part photomask 13 and the level-conversion circuit photomask 38 through wiring 40a.Thus, constitute the intermediate potential 1/2 (Vdd+Vbb) that positive side current potential Vdd and minus side current potential Vbb are provided to display part photomask 13 and level-conversion circuit photomask 38 from the current potential generative circuit 39a of portion.

In addition, externally in the circuit part 2, variable resistance 41 is set, is connected on the wiring 40a between current potential generative circuit 39a of portion and display part photomask 13 and the level-conversion circuit photomask 38, the current potential that provides from the current potential generative circuit 39a of portion is provided.Utilize this variable resistance 41, can in the scope of pact ± 3V, make the current potential that provides from the current potential generative circuit 39a of portion rise or descend.This is under the situation that threshold voltage vt h is shifted owing to processing differences, by regulating the current potential that offers display part photomask 13, the threshold voltage vt h of the n channel transistor 8 of scalable pixel portions 6 by this variable resistance 41.That is, under the situation that the current potential that utilizes variable resistance 41 to make to offer display part photomask 13 rises, because the current potential of the channel region 8d of the n channel transistor 8 of pixel portions 6 rises, so the threshold voltage vt h of n channel transistor 8 descends.On the other hand, under the situation that the current potential that utilizes variable resistance 41 to make to offer display part photomask 13 descends, because the current potential of the channel region 8d of the n channel transistor 8 of pixel portions 6 descends, so the threshold voltage vt h of n channel transistor 8 rises.

In addition, in the first embodiment, another current potential generative circuit 39b of portion is connected on shift- register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and the clock generating circuit photomask 34 through wiring 40b.The intermediate potential 1/2 (Vdd+Vss) of positive side current potential Vdd and minus side current potential Vss is provided to shift- register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 from the current potential generative circuit 39b of portion thus.

Below, with reference to Fig. 1-Fig. 8, the action of n channel transistor of pixel portions of the liquid crystal indicator of first execution mode is described.In addition, in following action specification, the action of the n channel transistor of the pixel portions in the liquid crystal indicator of some inversion driving (dot inversion driving) mode is described.In addition, will respectively provide potential setting is positive side current potential Vdd: about 7V, minus side current potential Vbb: pact-4V, common potential Vcom: about 3.5V, signal potential Vsig: about 1V～about 6V.In addition, the threshold voltage vt h that establishes the n channel transistor is about 1V.Thus, the voltage (potential difference) of n channel transistor between gate electrode and channel region becomes conducting state when above for about 1V.In addition, the voltage (potential difference) of n channel transistor between gate electrode and channel region becomes cut-off state when following for about 0.5V.

As pie graph 4-waveform prerequisite shown in Figure 7 write the action of picture signal to pixel, at first,, per 3 pixels that are connected on this gate line are carried out write activity successively along first section gate line.Afterwards, if be connected in the end of scan of first section whole pixel on the gate line, then carry out write activity to being connected in per 3 pixels on second section gate line equally to pixel.Thus, the whole pixels that are connected on the gate line that are arranged in the display part are carried out write activity successively.Afterwards, if the end of scan of whole gate lines then repeats same write activity since first section gate line once more.Shown in Fig. 4-Fig. 7 about the voltage waveform of the n channel transistor that is connected in the 3rd pixel in 3 pixels carrying out write activity in first section pixel on the gate line, at first.

In addition, among Fig. 4-Fig. 7,3 initial potential pulses are corresponding to the conduction period of the top raceway groove of n channel transistor, and simultaneously, back 3 potential pulses are corresponding between the off period, and afterwards, per 3 potential pulses are alternately corresponding between conduction period and off period.In addition, 3 potential pulses in above-mentioned conduction period correspond respectively to the write signal to 3 pixels selecting simultaneously when the write activity.In addition, after 3 potential pulses between the above-mentioned off period are illustrated respectively in above-mentioned the 3rd pixel are carried out write activity, to remaining pixel carry out write activity during, put on the voltage on above-mentioned the 3rd pixel.That is, first potential pulse between the off period is illustrated in after above-mentioned the 3rd pixel writes, to be connected in rest of pixels on the identical gate line with this pixel carry out write activity during, put on the voltage on above-mentioned the 3rd pixel.In addition, second and the 3rd potential pulse are illustrated in after the end of scan that is connected in first section gate line on above-mentioned the 3rd pixel, to be connected in pixel on second section and the 3rd section gate line carry out successively write activity during in, put on the voltage on above-mentioned the 3rd pixel.In addition, illustrate among Fig. 4-Fig. 7 between conduction period and off period, each potential pulse during for equal length, but in fact, be during the potential pulse between the off period than during much longer during the potential pulse in conduction period.In addition, among Fig. 4-Fig. 7, be shown between the off period and apply 3 potential pulses, but between this off period, the quantity of the potential pulse that applies is corresponding to the number change that is arranged on the gate line in the display part to pixel.Therefore, in fact owing to generally hundreds of gate lines being set in display part, so between the off period, apply than Fig. 4-much more potential pulse of potential pulse quantity (3) shown in Figure 7 to above-mentioned the 3rd pixel.

At first, the current potential (grid potential Vgate) of the gate electrode 8a of the n channel transistor 8 of input pixel portions 6 (with reference to Fig. 2) is switched to positive side current potential Vdd (about 7V) and minus side current potential Vbb (approximately-4V) as shown in Figure 4 alternately.Afterwards, the signal potential Vsig of the drain region 8b of input n channel transistor 8 is shown in the dotted line of Fig. 4, and current potential changes in the scope of about 1V～about 6V.At this moment, the current potential (Vch) of the channel region 8d of n channel transistor 8 changes in the scope of about 1.0V～about 5.5V in the waveform shown in the chain-dotted line of presentation graphs 4.The current potential Vch of channel region 8d among Fig. 4 represents near the current potential of central portion of channel region 8d.At this moment, the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgd=Vgate-Vsig, gate electrode 8a between the 8b of drain region and voltage (potential difference) Vgc=Vgate-Vch between channel region 8d are by wave form varies shown in Figure 5.

Therefore, grid potential Vgate (with reference to Fig. 4) be positive side current potential Vdd (about 7V) during in, the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgc (with reference to Fig. 5) between the channel region 8d are the voltage of about 1.8V～about 6.0V scope.Promptly, in this period, the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgc (about 1.8V～about 6.0V) between the channel region 8d are the voltage (more than about 1V) of the conducting region of n channel transistor 8, so n channel transistor 8 becomes conducting state.On the other hand, grid potential Vgate (with reference to Fig. 4) be minus side current potential Vbb (approximately-4V) during in, the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgc (with reference to Fig. 5) between the channel region 8d are the voltage of pact-9.5V～pact-5.0V scope.Promptly, in this period, (pact-9.5V～pact-5.0V) is the voltage (potential difference) (about 0.5V is following) of the cut-off region of n channel transistor 8, so n channel transistor 8 becomes cut-off state for the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgc between the channel region 8d.

In addition, in the first embodiment, apply the current potential of 1/2 (Vdd+Vbb) to the pixel portions lightproof area 13a (with reference to Fig. 3) of the display part photomask 13 that covers the setting of n channel transistor 8 ground from the current potential generative circuit 39a of portion (with reference to Fig. 1).Thus, the current potential Vback of the pixel portions lightproof area 13a of display part photomask 13 is fixed on 1/2 (Vdd+Vbb)=about 1.5V as shown in Figure 6.At this moment, effective voltage (potential difference) Vbc between the channel region 8d of pixel portions lightproof area 13a and n channel transistor 8 represents waveform shown in Figure 7.In addition, effective voltage (potential difference) Vbc between the channel region 8d of this pixel portions lightproof area 13a and n channel transistor 8 is the relative voltage with respect to the gate electrode 8a of n channel transistor 8 and voltage (potential difference) Vgc between the channel region 8d.Promptly, because the thickness (being about 300nm) of the dielectric film 16 between pixel portions lightproof area 13a and the crystal silicon film 17 (with reference to Fig. 3) that forms channel region 8d is about 3 times of thickness (about 100nm) of the gate insulating film 18 of n channel transistor 8, so be about 1/3 of the electric field strength that when gate electrode 8a provides same potential, from gate electrode 8a, puts on channel region 8d when the electric field strength that when pixel portions lightproof area 13a provides current potential, from pixel portions lightproof area 13a, puts on channel region 8d.Therefore, 1/3 voltage of the potential difference of the current potential Vback of the pixel portions lightproof area 13a of the photomask of display part shown in Fig. 7 13 and the current potential Vch of channel region 8d (1/3 (Vback-Vch)) is as effective voltage (potential difference) Vbc between pixel portions lightproof area 13a and the channel region 8d.In addition, among Fig. 7, from with above-mentioned the same viewpoint, the current potential Vback and the waveform that puts on 1/3 voltage (1/3 (Vback-Vsig)) of the potential difference of the signal potential Vsig on the 8b of drain region of pixel portions lightproof area 13a also are shown, as the pixel portions lightproof area 13a of display part photomask 13 and effective voltage (potential difference) Vbd between the 8b of drain region.

Effective voltage (potential difference) Vbc between the channel region 8d of pixel portions lightproof area 13a and n channel transistor 8 changes in the scope of pact-1.3V～about 0.2V as shown in Figure 7.Thus, effective voltage (potential difference) Vbc (pact-1.3V～about 0.2V) between pixel portions lightproof area 13a and the channel region 8d is always the voltage (about 0.5V is following) of the cut-off region of n channel transistor 8 as shown in Figure 8.Therefore, under the situation of the current potential that 1/2 (Vdd+Vbb) is provided to pixel portions lightproof area 13a, the bottom raceway groove of n channel transistor 8 is maintained at cut-off state.Thus, by apply to gate electrode 8a minus side current potential Vbb the top raceway groove of n channel transistor 8 is remained on cut-off state during, be suppressed to the pixel portions lightproof area 13a of display part photomask 13 and apply under the situation of current potential of 1/2 (Vdd+Vbb) the bottom raceway groove conducting of n channel transistor 8.Therefore, during this period, suppress between drain region 8b and source region 8c, to flow through electric current through the bottom of n channel transistor 8 raceway groove.

In addition, the n channel transistor that level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 are comprised in is separately also carried out the action the same with the n channel transistor 8 of above-mentioned pixel portions 6.Thus, the top raceway groove of the n channel transistor in will being contained in level-conversion circuit 36 (channel region of gate electrode side) remain on cut-off state during in, being suppressed to level-conversion circuit photomask 38 provides under the situation of current potential of 1/2 (Vdd+Vbb), the bottom raceway groove of n channel transistor (channel region of photomask side) conducting is so suppress to flow through electric current through the bottom raceway groove between the drain region of n channel transistor and source region.In addition, the top raceway groove of the n channel transistor that shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 are comprised in separately remain on cut-off state during in, being suppressed at photomask to correspondence provides under the situation of current potential of 1/2 (Vdd+Vss), the bottom raceway groove conducting of n channel transistor is so suppress to flow through electric current through the bottom raceway groove between the drain region of n channel transistor and source region.

In the first embodiment, as mentioned above, when display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 provide the current potential of 1/2 (Vdd+Vss), thereby, can be with the current potential of display part photomask 13 and level-conversion circuit photomask 38 stuck-at-s/2 (Vdd+Vbb), simultaneously, can be with shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, the current potential of DA transducer photomask 33 and clock generating circuit photomask 34 stuck-at-s/2 (Vdd+Vss).Thus, because display part photomask 13, level-conversion circuit photomask 38, shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, current potential does not change in DA transducer photomask 33 and the clock generating circuit photomask 34, so can suppress the threshold voltage of the n channel transistor 8 of pixel portions 6, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, the threshold voltage of the n channel transistor that DA transducer 28 and clock generating circuit 29 comprise in is separately followed the potential change of these photomasks and is changed.Therefore, the action of the n channel transistor that comprises in separately of action, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and the clock generating circuit 29 that can make the n channel transistor 8 of pixel portions 6 is stable.

In addition, in the first embodiment, when display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), the current potential of 1/2 (Vdd+Vss) is provided to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34, thus, can make voltage (potential difference) Vbc between the channel region of above-mentioned each photomask and corresponding n channel transistor be no more than the threshold voltage vt h of this n channel transistor.Therefore, can be suppressed at when display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 provide under the situation of current potential of 1/2 (Vdd+Vss), the n channel transistor 8 of pixel portions 6, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 n channel transistor separately becomes conducting state.Thus, can be suppressed at the n channel transistor 8 of pixel portions 6 and level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 n channel transistor separately remain on cut-off state during, the said n channel transistor provides the action failure of the caused liquid crystal indicator of current potential conducting because of the photomask to correspondence.

In addition, in the first embodiment, corresponding to display part 3, level-conversion circuit 36, shift- register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29, display part photomask 13 is set respectively, level-conversion circuit photomask 38, shift- register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34, simultaneously, provide current potential respectively to these photomasks, thereby each is provided with photomask with the n channel transistor that comprises in to above-mentioned each circuit part, simultaneously provide the situation of current potential to compare respectively to each photomask, can make to photomask provides the wiring of current potential or the quantity of plug connector to reduce, simultaneously, space (enough and to spare in space) between photomask and the crystal pipe end is increased significantly, maximize so can suppress liquid crystal indicator.

In addition, in the first embodiment, between the pixel portions lightproof area 13a of n channel transistor 8 and display part photomask 13, setting has the dielectric film 16 of about 3 times of thickness of gate insulating film 18 thickness of n channel transistor 8, thereby, under the situation of the gate electrode that pixel portions lightproof area 13a plays a part not expect, because playing the dielectric film 16 of gate insulator membrane interaction forms with big thickness, so under the situation of the current potential that applies 1/2 (Vdd+Vbb) to pixel portions lightproof area 13a, the channel region 8d of n channel transistor 8 is difficult to be subjected to the influence of this current potential.Thus, can reduce the variation of the threshold voltage vt h of the n channel transistor 8 that produces because of the current potential that applies 1/2 (Vdd+Vbb) to pixel portions lightproof area 13a.

Below, with reference to Fig. 1, Fig. 3 and Fig. 9-Figure 11, the manufacture process of n channel transistor of pixel portions of the liquid crystal indicator of first execution mode is described.

At first, as shown in Figure 9, the resilient coating 15 with about 300nm thickness is set on glass substrate 14.Afterwards, use sputtering method, on resilient coating 15, form have about 100nm thickness Mo film (not shown) afterwards, use photoetching technique and etching technique, this Mo film of Butut (patterning).Thus, as shown in Figure 1, in the regulation zone on resilient coating 15, form display part photomask 13, shift- register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33, clock generating circuit photomask 34 and level-conversion circuit photomask 38.In addition, at this moment, form display part photomask 13 and have the pixel portions lightproof area 13a of the switch element portion 7 that covers pixel portions 6 and the cancellate wiring lightproof area 13b of portion of covering gate polar curve and drain line.In addition, the regional corresponding regional opening beyond the switch element portion 7 display part photomask 13 and pixel portions 6 is so that light can pass through.

In addition, as shown in Figure 9, use the CVD method, form have about 300nm thickness by SiO ₂The dielectric film 16 that film constitutes.Afterwards, use the CVD method, on whole of dielectric film 16, form amorphous silicon film (not shown), afterwards, carry out the crystallization of this amorphous silicon film with about 70nm thickness.Particularly, the limit is gone up at heating plate (hot plate) substrate is heated to about 300 degree, and amorphous silicon film is heated thus to the infrared laser of amorphous silicon film irradiation continuous oscillation type in the limit.At this moment, to the display part photomask 13 that is made of the Mo film, shift-register circuit photomask 30 and 37 (with reference to Fig. 1), sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33, clock generating circuit photomask 34 and level-conversion circuit photomask 38 irradiation infrared lasers, these photomasks generate heat by also.Afterwards, be used to heat, further heat amorphous silicon film from this photomask.Thus, amorphous silicon film fusion.

Afterwards, after the irradiation infrared laser, the amorphous silicon film by the cooling fusion carries out crystallization.At this moment, if, then, form bigger crystal along laterally forming column crystal relatively along laterally (being parallel to the direction above the glass substrate 14) to the substrate scan laser.In addition, in the irradiation of the above-mentioned infrared laser of favourable usefulness and be not heated under the situation in zone of the above temperature of fusing point of amorphous silicon film, in this zone, form crystallite.In addition, also can use excimer laser annealing method (ELA) or in the crystallization based on the crystallization method of other energy exposure means.In addition, also can use solid phase crystallization method (SPC).As mentioned above, by the crystallization amorphous silicon film, obtain crystal silicon film (not shown).Afterwards, use photoetching technique and etching technique, this crystal silicon film of Butut, thus formation is as the crystal silicon film 17 of the islandization of the active layer of n channel transistor 8.Afterwards, crystal silicon film 17 is carried out channel doping.

Below, as shown in figure 10, use the CVD method, on dielectric film 16 and crystal silicon film 17, form have about 100nm thickness by SiO ₂The gate insulating film 18 that film constitutes is to cover crystal silicon film 17.Afterwards, after the ground floor plug connector 21 that forms from the pixel portions lightproof area 13a arrival gate insulating film 18 of display part photomask 13, on gate insulating film 18 and ground floor plug connector 21, form metal film (not shown) with about 150nm thickness.Afterwards,, in corresponding to the zone of the channel region 8d of crystal silicon film 17, form gate electrode 8a, simultaneously, form the middle wiring layer 22 that is connected in ground floor plug connector 21 by this metal film of Butut (not shown).

Afterwards, as shown in figure 11, after covering corresponding to the zone outside the zone of crystal silicon film 17 with resist film 50, with this resist film 50 and gate electrode 8a as mask, to crystal silicon film 17 intermediate ion implanted dopants.Thus, in crystal silicon film 17, form drain region 8b and source region 8c, be clipped in the channel region 8d among drain region 8b and the source region 8c.Afterwards, remove resist film 50.

Afterwards, as shown in Figure 3, on gate insulating film 18, cover gate electrode 8a and middle wiring layer 22 ground form dielectric film 19.Afterwards, in the middle of formation is connected in the second layer plug connector 23 of wiring layer 22 and be connected to the drain region 8b of crystal silicon film 17 and plug connector 20a and 20b on the 8c of source region after, on dielectric film 19, form the wiring layer 24 be connected in second layer plug connector 23.As mentioned above, form the n channel transistor 8 of pixel portions 6 of the liquid crystal indicator of first execution mode shown in Figure 3.

(second execution mode)

Below, the formation of the liquid crystal indicator of second execution mode is described with reference to Figure 12.

In second execution mode, different with above-mentioned first execution mode, the gate electrode 48a of the n channel transistor 48 of connection pixel portions 6 and the pixel portions lightproof area 13a of display part photomask 13.In addition, this n channel transistor 48 is examples of ' the first transistor ' of the present invention.Particularly, as shown in figure 12, the gate electrode 48a and the middle wiring layer 42 of the n channel transistor 48 by being connected to form pixel portions 6 are connected the gate electrode 48a of the n channel transistor 48 of the pixel portions lightproof area 13a of display part photomask 13 and pixel portions 6 with middle wiring layer 42 through plug connector 21.In addition, in second execution mode, the pixel portions lightproof area 13a that will be connected with the gate electrode 48a of a plurality of n channel transistors 48 on being connected a gate line be connected other gate line on the electric disconnection of pixel portions lightproof area 13a that is connected of the gate electrode 48a of a plurality of n channel transistors 48.

Thus, in second execution mode, put on current potential Vgate on the gate electrode 48a that is connected in a plurality of n channel transistors 48 on the same gate line and put on equally on the pixel portions lightproof area 13a on the gate electrode 48a that is connected to these a plurality of n channel transistors 48.Therefore, in second execution mode, can make the pixel portions lightproof area 13a of display part photomask 13 play the effect of the gate electrode of n channel transistor 48.The above-mentioned formation in addition of the liquid crystal indicator of second execution mode is the same with the formation of the liquid crystal indicator of above-mentioned first execution mode.In addition, the same with above-mentioned first execution mode, apply the fixed potential of 1/2 (Vdd+Vbb) to the level-conversion circuit photomask of the liquid crystal indicator of second execution mode.In addition, the same with above-mentioned first execution mode, apply the fixed potential of 1/2 (Vdd+Vss) to the shift-register circuit photomask of the shift-register circuit photomask of the H of the liquid crystal indicator of second execution mode series driver, sampling transistor photomask, buffer photomask, DA transducer photomask, V series driver.

Below, with reference to Figure 12-Figure 14, the action of n channel transistor of pixel portions of the liquid crystal indicator of second execution mode is described.

In the n channel transistor 48 (with reference to Figure 12) of the pixel portions 6 of the liquid crystal indicator of this second execution mode, apply and grid potential Vgate, the signal potential Vsig of above-mentioned first execution mode shown in Figure 4 and the same current potential of current potential Vch of channel region 8d to gate electrode 48a, drain region 8b and channel region 8d respectively.Thus, voltage Vgd between the gate electrode 48a of the n channel transistor 48 of second execution mode and the drain region 8b and the voltage Vgc between gate electrode 48a and the channel region 8d represent respectively and the gate electrode 8a of the n channel transistor 8 of first execution mode shown in Figure 5 and the same waveform of voltage Vgc between the voltage Vgd between the 8b of drain region and gate electrode 8a and the channel region 8d.

In addition, in second execution mode, by the gate electrode 48a of connection n channel transistor 48 and the pixel portions lightproof area 13a of display part photomask 13, the current potential identical with the grid potential Vgate on putting on gate electrode 48a put on the pixel portions lightproof area 13a of display part photomask 13.That is, the current potential Vback on the pixel portions lightproof area 13a that puts on display part photomask 13 of this second execution mode is identical with the grid potential Vgate of the n channel transistor 8 of first execution mode shown in Figure 4.In addition, in second execution mode, the gate electrode 48a to n channel transistor 48 apply positive side current potential Vdd during, also apply positive side current potential Vdd to the pixel portions lightproof area 13a of correspondence, simultaneously, the gate electrode 48a to n channel transistor 48 apply minus side current potential Vbb during, also apply minus side current potential Vbb to the pixel portions lightproof area 13a of correspondence.

In addition, effective voltage Vbd=1/3 (Vback-Vsig) between the pixel portions lightproof area 13a of the display part photomask 13 of second execution mode and the drain region 8b of n channel transistor 48 as shown in figure 13, expression narrows down to waveform after 1/3 with the waveform voltage value of the gate electrode 8a of the n channel transistor 8 of first execution mode shown in Figure 5 and voltage (potential difference) Vgd=Vgate-Vsig between the 8b of drain region.In addition, the pixel portions lightproof area 13a of the display part photomask 13 of second execution mode, and the channel region 8d of n channel transistor 48 between effective voltage Vbc=1/3 (Vback-Vch) as shown in figure 13, expression narrows down to waveform after 1/3 with the waveform voltage value of the gate electrode 8a of the n channel transistor 8 of first execution mode shown in Figure 5 and voltage (potential difference) Vgc=Vgate-Vch between the channel region 8d.

Therefore, the top of n channel transistor 48 raceway groove be conducting state during in, the pixel portions lightproof area 13a of the display part photomask 13 of second execution mode, and the channel region 8d of n channel transistor 48 between effective voltage Vbc in the scope of about 0.6V～about 2.0V, change.On the other hand, the top of n channel transistor 48 raceway groove (raceway groove of gate electrode 48a side) be cut-off state during, the pixel portions lightproof area 13a of the display part photomask 13 of second execution mode, and the channel region 8d of n channel transistor 48 between effective voltage Vbc in the scope of pact-3.2V～pact-1.7V, change.Thus, as shown in figure 14, the top of n channel transistor 48 raceway groove be cut-off state during, (pact-3.2V～pact-1.7V) becomes the voltage (about 0.5V is following) of the cut-off region of n channel transistor 48 to effective voltage (potential difference) Vbc between pixel portions lightproof area 13a and the channel region 8d.Therefore, the top raceway groove that is suppressed at n channel transistor 48 be cut-off state during, the bottom raceway groove of n channel transistor 48 (raceway groove of pixel portions lightproof area 13a side) conducting.Thus, suppress between drain region 8b and source region 8c, to flow through electric current through the bottom of n channel transistor 48 raceway groove during this period.

In second execution mode, as mentioned above, the gate electrode 48a of the pixel portions lightproof area 13a by connecting display part photomask 13 and the n channel transistor 48 of corresponding pixel portions 6, provide the identical current potential of current potential Vgate on the gate electrode 48a with the n channel transistor 48 that puts on corresponding pixel portions 6 to the pixel portions lightproof area 13a of display part photomask 13, thereby apply under the situation of minus side current potential Vbb at gate electrode 48a, also apply minus side current potential Vbb to pixel portions lightproof area 13a to n channel transistor 48.Thus, be suppressed at by apply minus side current potential Vbb to gate electrode 48a, make the top raceway groove of n channel transistor 48 remain on cut-off state during, because of the bottom raceway groove conducting that also provides minus side current potential Vbb to cause n channel transistor 48 to pixel portions lightproof area 13a.Therefore, can suppress the generation of the action failure of liquid crystal indicator.

In addition, in second execution mode, by the identical current potential of current potential that applies with gate electrode 48a to corresponding n channel transistor 48 is provided to pixel portions lightproof area 13a, can make pixel portions lightproof area 13a play the gate electrode 48a of n channel transistor 48, so can use the gate electrode 48a of n channel transistor 48 and the pixel portions lightproof area 13a both sides of display part photomask 13 to drive n channel transistor 48.Thus, the driving force of the n channel transistor 48 of pixel portions 6 is improved.Therefore, can write through the high speed that n channel transistor 48 is carried out signal potential Vsig.

The above-mentioned effect in addition of second execution mode is the same with the effect of above-mentioned first execution mode.

(the 3rd execution mode)

Below, the formation of the liquid crystal indicator of the 3rd execution mode is described with reference to Figure 15.

In the 3rd execution mode, different with above-mentioned first execution mode, the drain region 8b of the n channel transistor 58 of connection pixel portions 6 and the pixel portions lightproof area 13a of display part photomask 13.In addition, this n channel transistor 58 is examples of ' the first transistor ' of the present invention.Particularly, as shown in figure 15, on the ground floor plug connector 21 that is connected on the pixel portions lightproof area 13a of display part photomask 13, second layer plug connector 53 is set.In addition, in the zone corresponding to second layer plug connector 53 on dielectric film 19, form wiring layer 54.This wiring layer 54 be connected in second layer plug connector 53 with the drain region 8b of n channel transistor 58 on the plug connector 20a that is connected.Thus, be connected the drain region 8b of n channel transistor 58 and the pixel portions lightproof area 13a of display part photomask 13 through plug connector 20a, wiring layer 54, ground floor plug connector 21 and second layer plug connector 53.In addition, also can directly connect drain region 8b and pixel portions lightproof area 13a by ground floor plug connector 21.

Thus, in the 3rd execution mode, apply the identical current potential of current potential on the drain region 8b with the n channel transistor 58 that puts on pixel portions 6 to the pixel portions lightproof area 13a of display part photomask 13.In addition, in the 3rd execution mode, separately lightproof area 13b of wiring portion and pixel portions lightproof area 13a apply suitable current potential (1/2 (Vdd+Vss)) to the lightproof area 13b of wiring portion.The above-mentioned formation in addition of the liquid crystal indicator of the 3rd execution mode is the same with the formation of the liquid crystal indicator of above-mentioned first execution mode.In addition, the same with above-mentioned first execution mode, apply the fixed potential of 1/2 (Vdd+Vbb) to the level-conversion circuit photomask of the liquid crystal indicator of the 3rd execution mode.In addition, the same with above-mentioned first execution mode, apply the fixed potential of 1/2 (Vdd+Vss) to the shift-register circuit photomask of shift-register circuit photomask, sampling transistor photomask, buffer photomask, DA transducer photomask, clock generating circuit photomask and the V series driver of the H of the liquid crystal indicator of the 3rd execution mode series driver.

Below, with reference to Figure 15-Figure 17, the action of n channel transistor of pixel portions of the liquid crystal indicator of the 3rd execution mode is described.

In the n channel transistor 58 of the pixel portions 6 of the liquid crystal indicator of the 3rd execution mode, apply the current potential the same with signal potential Vsig to gate electrode 8a and drain region 8b respectively with the grid potential Vgate of above-mentioned first execution mode shown in Figure 4.At this moment, the current potential Vch of the channel region 8d of n channel transistor 58 is the same with the current potential Vch of the channel region 8d of first execution mode shown in Figure 4.Thus, voltage Vgd between the gate electrode 8a of the n channel transistor 58 of the 3rd execution mode and the drain region 8b and the voltage Vgc between gate electrode 8a and the channel region 8d represent respectively and the gate electrode 8a of the n channel transistor 8 of first execution mode shown in Figure 5 and the same waveform of voltage Vgc between the voltage Vgd between the 8b of drain region and gate electrode 8a and the channel region 8d.

In addition, in the 3rd execution mode, the drain region 8b by connecting n channel transistor 58 and the pixel portions lightproof area 13a of display part photomask 13 will the current potential identical with the signal potential Vsig on putting on drain region 8b put on the pixel portions lightproof area 13a of display part photomask 13.Thus, the effective voltage Vbd=1/3 (Vback-Vsig) between the drain region 8b of pixel portions lightproof area 13a and n channel transistor 58 is about 0V as shown in figure 16.In addition, the expression of the effective voltage Vbc=1/3 (Vback-Vch) between the channel region 8d of pixel portions lightproof area 13a and n channel transistor 58 waveform shown in Figure 16.

Therefore, the top of n channel transistor 58 raceway groove be conducting state during in, effective voltage (potential difference) Vbc between the pixel portions lightproof area 13a of the display part photomask 13 of the 3rd execution mode and the channel region 8d of n channel transistor 58 changes in the scope of pact-0.3V～about 0.8V.On the other hand, the top of n channel transistor 58 raceway groove be cut-off state during, the pixel portions lightproof area 13a of the display part photomask 13 of the 3rd execution mode, and the channel region 8d of n channel transistor 58 between effective voltage (potential difference) Vbc in the scope of pact-0.7V～about 0.4V, change.Thus, as shown in figure 17, the top of n channel transistor 58 raceway groove be cut-off state during, the effective voltage Vbc between pixel portions lightproof area 13a and the channel region 8d (pact-0.7V～about 0.4V) becomes the voltage (about 0.5V following) of the cut-off region of n channel transistor 58.Therefore, the top raceway groove that is suppressed at n channel transistor 58 be cut-off state during, under the situation of the pixel portions lightproof area 13a that will the current potential identical puts on display part photomask 13 with the signal potential Vsig on putting on drain region 8b, the bottom raceway groove conducting of n channel transistor 58.Thus, suppress between drain region 8b and source region 8c, to flow through electric current through the bottom of n channel transistor 58 raceway groove during this period.

In the 3rd execution mode, as mentioned above, the top raceway groove of the n of pixel portions 6 channel transistor 58 be cut-off state during, the current potential of the channel region 8d of n channel transistor 58 and is the current potential of the current potential (signal potential Vsig) corresponding to drain region 8b in the voltage range that the current potential (signal potential Vsig) of drain region 8b changes.Thus, the drain region 8b of the pixel portions lightproof area 13a by connecting display part photomask 13 and the n channel transistor 58 of corresponding pixel portions 6, provide the identical current potential of signal potential Vsig on the drain region 8b with the n channel transistor 58 that puts on corresponding pixel portions 6 to the pixel portions lightproof area 13a of display part photomask 13, thereby the top of n channel transistor 58 raceway groove be cut-off state during, effective voltage (potential difference) Vbc between the channel region 8d of the pixel portions lightproof area 13a of display part photomask 13 and n channel transistor 58 can be controlled in the scope of pact-0.7V～about 0.4V.Therefore, effective voltage (potential difference) Vbc between the channel region 8d of the pixel portions lightproof area 13a of display part photomask 13 and n channel transistor 58 can be controlled in the voltage range of cut-off region of n channel transistor 58 (below about 0.5V).Thus, can suppress because of the pixel portions lightproof area 13a to display part photomask 13 apply with put on drain region 8b on the identical current potential of signal potential Vsig when the channel cutoff of the top of n channel transistor 58, the bottom raceway groove conducting of n channel transistor 58.Therefore, can suppress the generation of the action failure of liquid crystal indicator.

In addition, in the 3rd execution mode, the pixel portions lightproof area 13a by connecting display part photomask 13 and the drain region 8b of n channel transistor 58, the capacitance that is connected in the drain line on the drain region 8b of n channel transistor 58 has increased the part of the pixel portions lightproof area 13a of display part photomask 13.Thus, when picture signal (signal potential Vsig) is provided to drain line, the electric charge of this picture signal fully can be stored in drain line and be connected in helping in the part as capacitance (electric capacitance) on the drain line.In addition, during n channel transistor 58 is because of sweep signal conducting that regulation is provided from gate line, can provide this abundant charge stored to each pixel through n channel transistor 58.Thus, the image quality of liquid crystal indicator is improved.

The above-mentioned effect in addition of the 3rd execution mode is the same with the effect of above-mentioned first execution mode.

(the 4th execution mode)

Illustrate in the 4th execution mode, the present invention is applicable to example in the organic EL display with reference to Figure 18.

In the organic EL display of the 4th execution mode, as shown in figure 18, by constituting pixel portions 66 as the n channel transistor 68 of switch element, auxiliary capacitor 69, anode 70, negative electrode 71, the organic EL 72 and the p channel transistor 73 that are held between anode 70 and the negative electrode 71.In addition, pixel portions 66 is examples of ' first area ' of the present invention and ' first circuit part ', and n channel transistor 68 and p channel transistor 73 are examples of ' the first transistor ' of the present invention.

In addition, on the gate electrode 68a of n channel transistor 68, be connected with gate line.Apply positive side current potential Vdd and minus side current potential Vbb through this gate line to the gate electrode 68a of n channel transistor 68.In addition, when the drain region of n channel transistor 68 68b was connected on the drain line, source region 68c was connected in the electrode of auxiliary capacitor 69 and the gate electrode 73a of p channel transistor 73.In addition, apply signal potential Vsig through drain line to the drain region of n channel transistor 68 68b.In addition, another electrode to auxiliary capacitor 69 provides positive side current potential PVdd.In addition, when providing positive side current potential PVdd, source region 73c is connected on the anode 70 to the drain region of p channel transistor 73 73b.In addition, provide earthing potential GND (Vcom) shared in each pixel portions 66 to negative electrode 71.

In addition, in the organic EL display of the 4th execution mode, the same display part photomask 13, shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33, clock generating circuit photomask 34 and the level-conversion circuit photomask 38 of liquid crystal indicator with above-mentioned first execution mode shown in Figure 1 is set also.In addition, in the organic EL display of the 4th execution mode, the n channel transistor 68 of covering pixel portions 66 (with reference to Figure 17) and p channel transistor 73 both sides' below are provided with the pixel portions lightproof area 13a of the display part photomask 13 of first execution mode shown in Figure 1.In addition, in the organic EL display of the 4th execution mode, apply the fixed potential of 1/2 (Vdd+Vbb) to the display part photomask 13 and the level-conversion circuit photomask 38 of first execution mode shown in Figure 1.In addition, in the organic EL display of the 4th execution mode, apply the fixed potential of 1/2 (Vdd+Vss) to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and the clock generating circuit photomask 34 of first execution mode shown in Figure 1.The above-mentioned formation in addition of the organic EL display of the 4th execution mode is the same with the formation of the liquid crystal indicator of above-mentioned first execution mode.

Figure 24-Figure 27 is the voltage oscillogram of p channel transistor action of pixel portions of the organic EL display of explanation four embodiment of the invention.Figure 28 is the figure of I-E characteristic of p channel transistor of pixel portions of the organic EL display of expression four embodiment of the invention.Below, with reference to Figure 18-Figure 28, the n channel transistor of pixel portions of organic EL display of four embodiment of the invention and the action of p channel transistor are described.

In addition, in following action specification, the n channel transistor of the pixel portions in the organic EL display of some inversion driving modes and the action of p channel transistor are described.In addition, be the positive side current potential Vdd that offers the gate electrode of n channel transistor with potential setting respectively is provided: about 7.5V, offer the positive side current potential PVdd of the drain region of p channel transistor: about 8V, minus side current potential Vbb: pact-2V, signal potential Vsig: about 3.5V～about 6.5V.In addition, the threshold voltage vt h that establishes the n channel transistor is about 1V, and the threshold voltage vt h of p channel transistor is pact-2.5V.Thus, the voltage of n channel transistor between gate electrode and channel region becomes conducting state when above for about 1V, and the voltage (potential difference) of p channel transistor between gate electrode and channel region is that pact-2.5V becomes conducting state when following.In addition, the voltage of n channel transistor between gate electrode and channel region becomes cut-off state when following for about 0.5V, and the voltage of p channel transistor between gate electrode and channel region is that pact-2.0V becomes cut-off state when above.

At first, the current potential (grid potential Vgate) of the gate electrode 68a of the n channel transistor 68 of input pixel portions 66 is switched to positive side current potential Vdd (about 7.5V) and minus side current potential Vbb (approximately-2V) as shown in figure 19 alternately.Afterwards, the current potential of the signal potential Vsig of the drain region 68b of input n channel transistor 68 changes in the scope of about 3.5V～about 6.5V.At this moment, the current potential Vch of the channel region 68d of n channel transistor 68 changes in the scope of about 3.5V～about 6.8V in expression waveform shown in Figure 19.In addition, the current potential Vch of the channel region 68d among Figure 18 represents near the current potential of central portion of channel region 68d.At this moment, the gate electrode 68a of n channel transistor 68 and the voltage Vgc=Vgate-Vch between the voltage Vgd=Vgate-Vsig between the 68b of drain region, gate electrode 68a and channel region 68d are by wave form varies shown in Figure 20.

Therefore, grid potential Vgate (with reference to Figure 19) be positive side current potential Vdd (about 7.5V) during in, the gate electrode 68a of n channel transistor 68 and voltage (potential difference) Vgc (with reference to Figure 20) between the channel region 68d are the voltage of about 0.7V～about 4V scope.Promptly, in this period, apply from initial condition signal potential Vsig first potential pulse during beyond gate electrode 68a and the voltage Vgc between the channel region 68d (about 1V～about 4V) be the voltage (more than about 1V) of the conducting region of n channel transistor 68, so n channel transistor 68 becomes conducting state.On the other hand, grid potential Vgate (with reference to Figure 19) be minus side current potential Vbb (approximately-2V) during in, the gate electrode 68a of n channel transistor 68 and voltage (potential difference) Vgc (with reference to Figure 20) between the channel region 68d are the voltage of pact-8.5V～pact-5.5V scope.That is, in this period, (pact-8.5V～pact-5.5V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 68 to the voltage Vgc between gate electrode 68a and the channel region 68d, so n channel transistor 68 becomes cut-off state.

In addition, in the 4th execution mode, apply the fixed potential of 1/2 (Vdd+Vbb) to the pixel portions lightproof area 13a of the display part photomask 13 of the n channel transistor 68 ground settings that cover pixel portions 66.Thus, the current potential Vback of the pixel portions lightproof area 13a of display part photomask 13 is fixed on 1/2 (Vdd+Vbb)=about 2.75V as shown in figure 21.At this moment, effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region 68d of effective voltage (potential difference) Vbd=1/3 (Vback-Vsig) between the drain region 68b of pixel portions lightproof area 13a and n channel transistor 68 and pixel portions lightproof area 13a and n channel transistor 68 represents waveform shown in Figure 22 respectively.In addition, the effective voltage Vbc between the channel region 68d of pixel portions lightproof area 13a and n channel transistor 68 changes in the scope of pact-1.4V～pact-0.3V as shown in figure 22.Thus, the effective voltage Vbc between pixel portions lightproof area 13a and the channel region 68d (pact-1.4V～about 0.3V) is always the voltage (about 0.5V is following) of the cut-off region of n channel transistor 68 as shown in figure 23.Therefore, the top raceway groove with n channel transistor 68 remain cut-off state during, be suppressed to the pixel portions lightproof area 13a of display part photomask 13 and apply under the situation of current potential of 1/2 (Vdd+Vbb) the bottom raceway groove conducting of n channel transistor 68.Therefore, during this period, suppress between drain region 68b and source region 68c, to flow through electric current through the bottom of n channel transistor 68 raceway groove.

Below, the current potential (the source potential Vs of grid potential Vgate (Pch)=n channel transistor 68) of the gate electrode 73a of the p channel transistor 73 of input pixel portions 66 as shown in figure 24, changes in the scope of about 3.5V～about 6.5V.Afterwards, apply positive side current potential PVdd (about 8V) to the drain region of p channel transistor 73 73b.At this moment, the current potential Vch of the channel region 73d of p channel transistor 73 represents waveform shown in Figure 24.Thus, voltage (potential difference) Vgc=Vgate (the Pch)-Vch (Pch) between the gate electrode 73a of p channel transistor 73 and voltage (potential difference) Vgd=Vgate (Pch) between the 73b of drain region-Vd (Pch), gate electrode 73a and channel region 73d is by wave form varies shown in Figure 25.In addition, the voltage Vgc between gate electrode 73a and channel region 73d become the conducting region of p channel transistor 73 voltage (below the pact-2.5V) during in, p channel transistor 73 becomes conducting state.On the other hand, the voltage Vgc between gate electrode 73a and channel region 73d become the cut-off region of p channel transistor 73 voltage (more than the pact-2V) during in, p channel transistor 73 becomes cut-off state.

In addition, in the 4th execution mode, apply the current potential of 1/2 (Vdd+Vbb)=about 2.75V to the pixel portions lightproof area 13a of the display part photomask 13 of the p channel transistor 73 ground settings that cover pixel portions 66.Thus, the current potential Vback of the pixel portions lightproof area 13a of the 4th execution mode is fixed on about 2.75V as shown in figure 26.At this moment, effective voltage (potential difference) Vbd=1/3 (Vback-Vd (Pch)) between the drain region 73b of pixel portions lightproof area 13a and p channel transistor 73 as shown in figure 27, becomes pact-1.75V.In addition, effective voltage (potential difference) Vbc=1/3 (Vback-Vch (Pch)) between the channel region 73d of pixel portions lightproof area 13a and p channel transistor 73 is the voltage of the scope of pact-1.75V～pact-0.25V in expression waveform shown in Figure 27.Thus, the (pact-1.75V～pact-0.25V) as shown in figure 28, be always the voltage (more than the pact-2V) of the cut-off region of p channel transistor 73 of effective voltage (potential difference) Vbc between the channel region 73d of pixel portions lightproof area 13a and p channel transistor 73.Therefore, the top raceway groove with p channel transistor 73 remain cut-off state during, be suppressed to the pixel portions lightproof area 13a of display part photomask 13 and apply under the situation of current potential of 1/2 (Vdd+Vbb) the bottom raceway groove conducting of p channel transistor 73.Therefore, during this period, suppress between drain region 73b and source region 73c, to flow through electric current through the bottom of p channel transistor 73 raceway groove.

In the 4th execution mode, as mentioned above, in organic EL display, when display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 provide the current potential of 1/2 (Vdd+Vss), thereby, can be with the current potential of display part photomask 13 and level-conversion circuit photomask 38 stuck-at-s/2 (Vdd+Vbb), simultaneously, can be with shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, the current potential of DA transducer photomask 33 and clock generating circuit photomask 34 stuck-at-s/2 (Vdd+Vss).Thus, because display part photomask 13, level-conversion circuit photomask 38, shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, current potential does not change in DA transducer photomask 33 and the clock generating circuit photomask 34, so can suppress the n channel transistor 68 of pixel portions 66 and the threshold voltage of p channel transistor 73, with level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 separately in the threshold voltage of the n channel transistor that comprises follow the potential change of these photomasks and change.Therefore, with regard to organic EL display, can make the n channel transistor 68 of pixel portions 66 and p channel transistor 73 action, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 separately in the action of the n channel transistor that comprises stable.

In addition, in the 4th execution mode, with regard to organic EL display, when the pixel portions lightproof area 13a of display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 provide the current potential of 1/2 (Vdd+Vss), thus, can make the n channel transistor 68 and the p channel transistor 73 of above-mentioned each photomask and corresponding pixel portions 66, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, voltage (potential difference) Vbc between the n channel transistor that DA transducer 28 and clock generating circuit 29 comprise in separately is no more than said n channel transistor or p channel transistor threshold voltage vt h separately.Therefore, can be suppressed at when display part photomask 13 and level-conversion circuit photomask 38 provide the current potential of 1/2 (Vdd+Vbb), to shift-register circuit photomask 30 and 37, sampling transistor photomask 31, buffer photomask 32, DA transducer photomask 33 and clock generating circuit photomask 34 provide under the situation of current potential of 1/2 (Vdd+Vss), the n channel transistor 68 of pixel portions 66 and the bottom raceway groove of p channel transistor 73, level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, the bottom raceway groove of DA transducer 28 and clock generating circuit 29 n channel transistor separately becomes conducting state.Thus, can be suppressed at the top raceway groove of the n channel transistor 68 of pixel portions 66 and p channel transistor 73, with the top raceway groove of level-conversion circuit 36, shift-register circuit 25 and 35, sampling transistor 26, buffer 27, DA transducer 28 and clock generating circuit 29 n channel transistor separately remain on cut-off state during, the bottom raceway groove of said n channel transistor or p channel transistor provides the action failure of the caused organic EL display of current potential conducting because of the photomask to correspondence.

The above-mentioned effect in addition of the 4th execution mode is the same with the effect of above-mentioned first execution mode.

(the 5th execution mode)

In the 5th execution mode, different with above-mentioned the 4th execution mode, illustrate that pixel portions lightproof area to the display part photomask of organic EL display applies the situation of the current potential identical with the gate electrode of the n channel transistor of respective pixel portion and p channel transistor.

The organic EL display of the 5th execution mode has the pixel portions the same with the pixel portions 66 of the 4th execution mode shown in Figure 180.Wherein, in the 5th execution mode, the n channel transistor 68 of the pixel portions 66 of the 4th execution mode shown in Figure 180 and p channel transistor 73 have the structure that is connected the pixel portions lightproof area 13a of the gate electrode 48a of second execution mode shown in Figure 12 and display part photomask 13 through plug connector 21 with middle wiring layer 42.In addition, in the 5th execution mode, the pixel portions lightproof area 13a that will be connected respectively with the gate electrode of a plurality of n channel transistors 68 (p channel transistor 73) on being connected in a gate line be connected in other gate line on the pixel portions lightproof area 13a that is connected respectively of the gate electrode of a plurality of n channel transistors 68 (p channel transistor 73) carry out electric disconnection.Thus, in the 5th execution mode, to the n channel transistor 68 of the pixel portions 66 of the 4th execution mode shown in Figure 180 and p channel transistor 73 gate electrode 68a separately and 73a, apply identical current potential with the pixel portions lightproof area 13a of corresponding display part photomask 13.The above-mentioned formation in addition of the organic EL display of the 5th execution mode is the same with the formation of the organic EL display of above-mentioned the 4th execution mode.

In addition, the same with above-mentioned the 4th execution mode, apply the fixed potential of 1/2 (Vdd+Vbb) to the level-conversion circuit photomask of the organic EL display of the 5th execution mode.In addition, the same with above-mentioned the 4th execution mode, apply the fixed potential of 1/2 (Vdd+Vss) to the shift-register circuit photomask of shift-register circuit photomask, sampling transistor photomask, buffer photomask, DA transducer photomask, clock generating circuit photomask and the V series driver of the H of the organic EL display of the 5th execution mode series driver.

Below, with reference to Figure 29-Figure 32, the n channel transistor of pixel portions of organic EL display of the 5th execution mode and the action of p channel transistor are described.

In the n channel transistor 68 of the pixel portions 66 of the organic EL display of the 5th execution mode, apply the current potential the same with signal potential Vsig to gate electrode 68a and drain region 68b respectively with the grid potential Vgate of above-mentioned the 4th execution mode shown in Figure 19.Thus, apply the same current potential of current potential Vch with the channel region 68d of the 4th execution mode shown in Figure 19 to the channel region 68d of the n of the 5th execution mode channel transistor 68.Therefore, in the top raceway groove side of the n channel transistor 68 of the pixel portions 66 of the 5th execution mode, carry out and the same action of above-mentioned the 4th execution mode.

In addition, in the 5th execution mode, the gate electrode 68a by connecting n channel transistor 68 and the pixel portions lightproof area 13a of display part photomask 13 put on the current potential Vgate that puts on the gate electrode 68a that is connected a plurality of n channel transistors 68 on the same gate line pixel portions lightproof area 13a on the gate electrode 68a that is connected to these a plurality of n channel transistors 68 equally.That is, the current potential Vback on the pixel portions lightproof area 13a that puts on display part photomask 13 of the 5th execution mode represents the identical waveform of grid potential Vgate with the n channel transistor 68 of the 4th execution mode shown in Figure 19.In addition, in the 5th execution mode, the gate electrode 68a to n channel transistor 68 apply positive side current potential Vdd during, also apply positive side current potential Vdd to the pixel portions lightproof area 13a of correspondence.On the other hand, the gate electrode 68a to n channel transistor 68 apply minus side current potential Vbb during, also apply minus side current potential Vbb to the pixel portions lightproof area 13a of correspondence.In addition, the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode, and the drain region 68b of n channel transistor 68 between effective voltage Vbd=1/3 (Vback-Vsig) as shown in figure 29, expression narrows down to waveform after 1/3 with the waveform voltage value of the gate electrode 68a of the n channel transistor 68 of the 4th execution mode shown in Figure 20 and the voltage Vgd between the 68b of drain region.In addition, the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode, and the channel region 68d of n channel transistor 68 between effective voltage Vbc=1/3 (Vback-Vch) as shown in figure 29, expression narrows down to waveform after 1/3 with the waveform voltage value of the gate electrode 68a of the n channel transistor 68 of the 4th execution mode shown in Figure 20 and the voltage Vgc between the channel region 68d.

Therefore, the top of n channel transistor 68 raceway groove be conducting state during in, the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode, and the channel region 68d of n channel transistor 68 between effective voltage (potential difference) Vbc in the scope of about 0.2V～about 1.3V, change.On the other hand, the top of n channel transistor 68 raceway groove be cut-off state during, effective voltage (potential difference) Vbc between the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode and the channel region 68d of n channel transistor 68 changes in the scope of pact-2.8V～pact-1.8V.Thus, as shown in figure 30, the top raceway groove of the n of the 5th execution mode channel transistor 68 be cut-off state during, (pact-2.8V～pact-1.8V) becomes the voltage (about 0.5V is following) of the cut-off region of n channel transistor 68 to the effective voltage Vbc between pixel portions lightproof area 13a and the channel region 68d.Therefore, the top raceway groove that is suppressed at n channel transistor 68 be cut-off state during, the bottom raceway groove conducting of n channel transistor 68.Thus, suppress between drain region 68b and source region 68c, to flow through electric current through the bottom of n channel transistor 68 raceway groove during this period.

Afterwards, in the p channel transistor 73 of the pixel portions 66 of the organic EL display of the 5th execution mode, apply grid potential Vgate (Pch) and the positive the same current potential of side current potential PVdd with the 4th execution mode shown in Figure 24 to gate electrode 73a and drain region 73b respectively.Thus, apply the same current potential of current potential Vch with the channel region 73d of the 4th execution mode shown in Figure 24 to the channel region 73d of the p of the 5th execution mode channel transistor 73.Therefore, in the top raceway groove side of the p channel transistor 73 of the pixel portions 66 of the 5th execution mode, carry out the action the same with the p channel transistor 73 of above-mentioned the 4th execution mode.

In addition, in the 5th execution mode, by the gate electrode 73a of connection p channel transistor 73 and the pixel portions lightproof area 13a of display part photomask 13, the current potential identical with the grid potential Vgate (Pch) on putting on gate electrode 73a put on the pixel portions lightproof area 13a of display part photomask 13.That is, the current potential Vback on the pixel portions lightproof area 13a that puts on display part photomask 13 of the 5th execution mode represents the identical waveform of grid potential Vgate (Pch) with the 4th execution mode shown in Figure 24.Thus, effective voltage Vbd=1/3 between the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode and the drain region 73b of p channel transistor 73 (Vback-Vd (Pch)) as shown in figure 31, expression narrows down to waveform after 1/3 with the magnitude of voltage of the waveform of the gate electrode 73a of the p channel transistor 73 of the 4th execution mode shown in Figure 25 and the voltage Vgd between the 73b of drain region.In addition, effective voltage Vbc=1/3 between the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode and the channel region 73d of p channel transistor 73 (Vback-Vch (Pch)) as shown in figure 31, expression narrows down to waveform after 1/3 with the magnitude of voltage of the waveform of the gate electrode 73a of the p channel transistor 73 of the 4th execution mode shown in Figure 25 and the voltage Vgc between the channel region 73d.

Therefore, the pixel portions lightproof area 13a of the display part photomask 13 of the 5th execution mode, and the channel region 73d of p channel transistor 73 between effective voltage Vbc as shown in figure 31, in the scope of pact-1.5V～about 0V, change.Thus, shown in figure 32, the effective voltage Vbc between the pixel portions lightproof area 13a of the 5th execution mode and the channel region 73d of p channel transistor 73 (pact-1.5V～about 0V) becomes the voltage (more than the pact-2V) of the cut-off region of p channel transistor 73.Therefore, the top raceway groove that is suppressed at p channel transistor 73 be cut-off state during, the bottom raceway groove conducting of p channel transistor 73.Thus, suppress between drain region 73b and source region 73c, to flow through electric current through the bottom of p channel transistor 73 raceway groove during this period.

In the 5th execution mode, as mentioned above, with regard to organic EL display, the gate electrode 68a of the pixel portions lightproof area 13a by connecting display part photomask 13 and the n channel transistor 68 of corresponding pixel portions 66, provide the identical current potential of grid potential Vgate with the n channel transistor 68 of corresponding pixel portions 66 to the pixel portions lightproof area 13a of display part photomask 13, thereby, be suppressed at by apply to gate electrode 68a top raceway groove that minus side current potential Vbb makes n channel transistor 68 remain on cut-off state during, because of the bottom raceway groove conducting that also provides minus side current potential Vbb to cause n channel transistor 68 to pixel portions lightproof area 13a.Therefore, can suppress the generation of the action failure of organic EL display.

In addition, in the 5th execution mode, with regard to organic EL display, the gate electrode 73a of the pixel portions lightproof area 13a by connecting display part photomask 13 and the p channel transistor 73 of corresponding pixel portions 66, provide the identical current potential of grid potential Vgate with the p channel transistor 73 of corresponding pixel portions 66 to the pixel portions lightproof area 13a of display part photomask 13, thereby, be suppressed at top raceway groove with p channel transistor 73 remain on cut-off state during, the bottom raceway groove conducting of p channel transistor 73.Therefore, can suppress the generation of the action failure of organic EL display.

In addition, in the 5th execution mode, as mentioned above, with regard to organic EL display, the gate electrode 68a (the gate electrode 73a of p channel transistor 73) of the pixel portions lightproof area 13a by connecting display part photomask 13 and the n channel transistor 68 of corresponding pixel portions 66, provide the identical current potential of current potential with the gate electrode 68a (the gate electrode 73a of p channel transistor 73) of the n channel transistor 68 that puts on corresponding pixel portions 66 to the pixel portions lightproof area 13a of display part photomask 13, thereby can make the pixel portions lightproof area 13a of display part photomask 13 play the gate electrode of the n channel transistor 68 (p channel transistor 73) of pixel portions 66.Thus, can use the gate electrode 68a of n channel transistor 68 and the pixel portions lightproof area 13a both sides of display part photomask 13 to drive n channel transistor 68, simultaneously, can use the gate electrode 73a of p channel transistor 73 and the pixel portions lightproof area 13a both sides of display part photomask 13 to drive p channel transistor 73.Thus, the n channel transistor 68 of pixel portions 66 and the driving force of p channel transistor 73 are improved.

In addition, effective voltage Vbc between the pixel portions lightproof area 13a of the 5th execution mode shown in Figure 31 and the channel region 73d of p channel transistor 73 (pact-1.5V～about 0V) is always the voltage (more than the pact-2V) of the cut-off region of p channel transistor 73, but respectively provide current potential if set, make during the top of p channel transistor 73 raceway groove becomes conducting state, voltage Vbc becomes the voltage (pact-2.5V following) of the conducting region of p channel transistor 73, then can easily make the pixel portions lightproof area 13a of display part photomask 13 play the gate electrode of the bottom raceway groove side of p channel transistor 73.

The above-mentioned effect in addition of the 5th execution mode is the same with the effect of above-mentioned first execution mode.

(the 6th execution mode)

In the 6th execution mode, different with above-mentioned the 4th execution mode, illustrate that pixel portions lightproof area to the display part photomask of organic EL display applies the situation of the current potential identical with the drain region of the n channel transistor of corresponding pixel portions and p channel transistor.

The organic EL display of the 6th execution mode has the pixel portions the same with the pixel portions 66 of the 4th execution mode shown in Figure 180.But in the 6th execution mode, the n channel transistor 68 of the pixel portions 66 of the 4th execution mode shown in Figure 180 and p channel transistor 73 have the structure the same with the n channel transistor 58 of the 3rd execution mode shown in Figure 15.Promptly, in the 6th execution mode, the n channel transistor 68 of the pixel portions 66 of the 4th execution mode shown in Figure 180 and p channel transistor 73 have the structure that is connected the pixel portions lightproof area 13a of the drain region 8b of the 3rd execution mode shown in Figure 15 and display part photomask 13 through ground floor plug connector 21, second layer plug connector 53, wiring layer 54 and plug connector 20a.In addition, also can directly connect drain region 8b and pixel portions lightproof area 13a by ground floor plug connector 21.Thus, in the 6th execution mode, to the n channel transistor 68 of the pixel portions 66 of the 4th execution mode shown in Figure 180 and p channel transistor 73 drain region 68b separately and 73b, apply identical current potential with the pixel portions lightproof area 13a of corresponding display part photomask 13.In addition, in the 6th execution mode, separately lightproof area 13b of wiring portion and pixel portions lightproof area 13a apply suitable current potential (1/2 (Vdd+Vss)) to the lightproof area 13b of wiring portion.The above-mentioned formation in addition of the organic EL display of the 6th execution mode is the same with the formation of the organic EL display of above-mentioned the 4th execution mode.

In addition, the same with above-mentioned the 4th execution mode, apply the current potential of 1/2 (Vdd+Vbb) to the level-conversion circuit photomask of the organic EL display of the 6th execution mode.In addition, the same with above-mentioned the 4th execution mode, apply the current potential of 1/2 (Vdd+Vss) to the shift-register circuit photomask of shift-register circuit photomask, sampling transistor photomask, buffer photomask, DA transducer photomask, clock generating circuit photomask and the V series driver of the H of the organic EL display of the 5th execution mode series driver.

Below, with reference to Figure 33-Figure 36, the n channel transistor of pixel portions of organic EL display of the 6th execution mode and the action of p channel transistor are described.

In the n channel transistor 68 of the pixel portions 66 of the organic EL display of the 6th execution mode, apply the current potential the same with signal potential Vsig to gate electrode 68a and drain region 68b respectively with the grid potential Vgate of above-mentioned the 4th execution mode shown in Figure 19.At this moment, apply the same current potential of current potential Vch with the channel region 68d of the 4th execution mode shown in Figure 19 to the channel region 68d of the n of the 6th execution mode channel transistor 68.Thus, in the top raceway groove side of the n channel transistor 68 of the pixel portions 66 of the 6th execution mode, carry out and the same action of above-mentioned the 4th execution mode.

In addition, in the 6th execution mode, the pixel portions lightproof area 13a of the drain region 68b by connecting n channel transistor 68 and corresponding display part photomask 13 puts on the current potential identical with the signal potential Vsig on putting on drain region 68b on the pixel portions lightproof area 13a of display part photomask 13.Thus, the effective voltage Vbd=1/3 (Vback-Vsig) between the pixel portions lightproof area 13a of the display part photomask 13 of the 6th execution mode and the drain region 68b of n channel transistor 68 is about 0V as shown in figure 33.In addition, effective voltage Vbc=1/3 (Vback-Vch) the expression waveform shown in Figure 33 between the pixel portions lightproof area 13a of the 6th execution mode and the channel region 68d of n channel transistor 68 simultaneously, changes under the scope of pact-0.2V～about 0.4V.

Therefore, as shown in figure 34, the effective voltage Vbc between the pixel portions lightproof area 13a of the 6th execution mode and the channel region 68d of n channel transistor 68 (pact-0.2V～about 0.4V) becomes the voltage (about 0.5V is following) of the cut-off region of n channel transistor 68.Thus, in the 6th execution mode, the top raceway groove that is suppressed at n channel transistor 68 be cut-off state during in, under the situation of the pixel portions lightproof area 13a that will the current potential identical puts on display part photomask 13 with the signal potential Vsig on the drain region 68b that puts on n channel transistor 68, the bottom raceway groove conducting of n channel transistor 68.Thus, suppress between drain region 68b and source region 68c, to flow through electric current through the bottom of n channel transistor 68 raceway groove during this period.

Afterwards, in the p channel transistor 73 of the pixel portions 66 of the organic EL display of the 6th execution mode, apply grid potential Vgate (Pch) and the positive the same current potential of side current potential PVdd with the 4th execution mode shown in Figure 24 to gate electrode 73a and drain region 73b respectively.At this moment, apply the same current potential of current potential Vch with the channel region 73d of the 4th execution mode shown in Figure 24 to the channel region 73d of the p of the 6th execution mode channel transistor 73.Thus, in the top raceway groove side of the p channel transistor 73 of the pixel portions 66 of the 6th execution mode, carry out the action the same with the p channel transistor 73 of above-mentioned the 4th execution mode.

In addition, in the 6th execution mode, by the drain region 73b of connection p channel transistor 73 and the pixel portions lightproof area 13a of display part photomask 13, the current potential identical with the positive side current potential PVdd (about 8V) on putting on drain region 73b put on the pixel portions lightproof area 13a of display part photomask 13.Thus, the effective voltage Vbd=1/3 between the drain region 73b of the pixel portions lightproof area 13a of the display part photomask 13 of the 6th execution mode and p channel transistor 73 (Vback-Vd (Pch)) as shown in figure 35, is about 0V.In addition, the waveform that the effective voltage Vbc=1/3 between the pixel portions lightproof area 13a of the 6th execution mode and the channel region 73d of p channel transistor 73 (Vback-Vch (Pch)) expression is shown in Figure 35 simultaneously, changes under the scope of about 0V～about 1.5V.

Therefore, as shown in figure 36, effective voltage (potential difference) Vbc (about 0V～about 1.5V) between the channel region 73d of the pixel portions lightproof area 13a of the 6th execution mode and p channel transistor 73 becomes the voltage (more than the pact-2V) of the cut-off region of p channel transistor 73.Thus, in the 6th execution mode, the top raceway groove that is suppressed at p channel transistor 73 be cut-off state during in, under the situation of the pixel portions lightproof area 13a that will put on corresponding display part photomask 13 with the positive side current potential PVdd same potential on putting on drain region 73b, the bottom raceway groove conducting of p channel transistor 73.Thus, suppress between drain region 73b and source region 73c, to flow through electric current through the bottom of p channel transistor 73 raceway groove during this period.

In the 6th execution mode, as mentioned above, the current potential of the channel region 68d of the n channel transistor 68 of pixel portions 66 and is the current potential of the current potential (signal potential Vsig) corresponding to drain region 68b in the voltage range that the current potential (signal potential Vsig) of drain region 68b changes.Thus, with regard to organic EL display, the drain region 68b of the pixel portions lightproof area 13a by connecting display part photomask 13 and the n channel transistor 68 of corresponding pixel portions 66, provide the identical current potential of signal potential Vsig on the drain region 68b with the n channel transistor 68 that puts on corresponding pixel portions 66 to the pixel portions lightproof area 13a of display part photomask 13, thereby effective voltage (potential difference) Vbc between the channel region 68b of the pixel portions lightproof area 13a of display part photomask 13 and corresponding n channel transistor 68 can be controlled in the scope of pact-0.2V～about 0.4V.Therefore, effective voltage (potential difference) Vbc between the channel region 68b of the pixel portions lightproof area 13a of display part photomask 13 and corresponding n channel transistor 68 can be controlled in the voltage range of cut-off region of n channel transistor 68 (below about 0.5V).Thus, can suppress because of the pixel portions lightproof area 13a to display part photomask 13 apply with put on drain region 68b on the identical current potential of signal potential Vsig when the channel cutoff of the top of n channel transistor 68, the bottom raceway groove conducting of n channel transistor 68.Therefore, can suppress the generation of the action failure of organic EL display.

In addition, in the 6th execution mode, the current potential of the channel region 73d of the p channel transistor 73 of pixel portions 66 is corresponding to the current potential in the prescribed limit of the positive side current potential PVdd of drain region 73b.Thus, with regard to organic EL display, the drain region 73b of the pixel portions lightproof area 13a by connecting display part photomask 13 and the p channel transistor 73 of corresponding pixel portions 66, provide the identical current potential of positive side current potential PVdd on the drain region 73b with the p channel transistor 73 that puts on corresponding pixel portions 66 to the pixel portions lightproof area 13a of display part photomask 13, thereby effective voltage (potential difference) Vbc between the channel region 73d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding p channel transistor 73 can be controlled in the scope of about 0V～about 1.5V.Therefore, effective voltage (potential difference) Vbc between the channel region 73d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding p channel transistor 73 can be controlled in the voltage range of cut-off region of p channel transistor 73 (more than the pact-2V).Thus, can suppress because of the pixel portions lightproof area 13a to display part photomask 13 apply with put on drain region 73b on the identical current potential of positive side current potential PVdd when the channel cutoff of the top of p channel transistor 73, the bottom raceway groove conducting of p channel transistor 73.Therefore, also can suppress the generation of the action failure of organic EL display.

In addition, in the 6th execution mode, the pixel portions lightproof area 13a by connecting display part photomask 13 and the drain region 68b of n channel transistor 68, the electric capacity that is connected in the drain line on the drain region 68b of n channel transistor 68 has increased the part of the pixel portions lightproof area 13a of display part photomask 13.Thus, when picture signal (signal potential Vsig) is provided to drain line, the electric charge of this picture signal fully can be stored in drain line and be connected in the part of contributing as capacitance on the drain line.In addition, during n channel transistor 68 is because of sweep signal conducting that regulation is provided from gate line, can provide this abundant charge stored to the grid of p channel transistor 73 through n channel transistor 68.Thus, the situation little with the electric capacity of drain line is different, the signal potential Vsig that offers the picture signal of drain line fully can be delivered to the grid of p channel transistor 73a, so can control the conducting state (cut-off state) of p channel transistor 73 really corresponding to the signal potential Vsig of picture signal.Therefore, can correctly control the current potential that puts on organic EL display 72 through p channel transistor 73, so the image quality of organic EL display is improved corresponding to picture signal.

The above-mentioned effect in addition of the 6th execution mode is the same with the effect of above-mentioned first execution mode.

(the 7th execution mode)

In the 7th execution mode, different with above-mentioned the 4th execution mode, explanation applies the positive side current potential PVdd that applies to the drain region of p channel transistor to the pixel portions lightproof area of the display part photomask of the p of the pixel portions of organic EL display channel transistor below configuration, simultaneously, the pixel portions lightproof area of the display part photomask that disposes below the n of pixel portions channel transistor applies the situation of the current potential of 1/2 (Vdd+Vbb).

The organic EL display of the 7th execution mode has the pixel portions the same with the pixel portions 66 of the 4th execution mode shown in Figure 180.Wherein, in the 7th execution mode, to the pixel portions lightproof area 13a of the display part photomask 13 of the p channel transistor 73 belows configuration of the pixel portions 66 of the 4th execution mode shown in Figure 180, be connected with the holding wire that positive side current potential PVdd is provided that is connected on the drain region 73b with p channel transistor 73.Thus, in the 7th execution mode, provide positive side current potential PVdd to the pixel portions lightproof area 13a of the display part photomask 13 of the p of pixel portions 66 channel transistor 73 belows configurations.The above-mentioned formation in addition of the organic EL display of the 7th execution mode is the same with the formation of the organic EL display of above-mentioned the 4th execution mode.

In addition, the same with above-mentioned the 4th execution mode, apply the current potential of 1/2 (Vdd+Vbb) to the pixel portions lightproof area 13a of the display part photomask 13 of the lightproof area 13b of wiring portion of the pixel portions 66 of the 7th execution mode and the configuration of n channel transistor 68 belows.In addition, the same with above-mentioned the 4th execution mode, apply the current potential of 1/2 (Vdd+Vbb) to the level-conversion circuit photomask of the organic EL display of the 7th execution mode.In addition, the same with above-mentioned the 4th execution mode, apply the current potential of 1/2 (Vdd+Vss) to the shift-register circuit photomask of shift-register circuit photomask, sampling transistor photomask, buffer photomask, DA transducer photomask, clock generating circuit photomask and the V series driver of the H of the organic EL display of the 7th execution mode series driver.

Below, the n channel transistor of pixel portions of organic EL display of the 7th execution mode and the action of p channel transistor are described.

The n channel transistor 68 of the pixel portions 66 of the organic EL display of the 7th execution mode is by carrying out the n channel transistor 68 duplicate actions with the pixel portions 66 of above-mentioned execution mode 4, the top raceway groove that is suppressed at n channel transistor 68 be cut-off state during, the bottom raceway groove conducting of n channel transistor 68.

In addition, in the p channel transistor 73 of the pixel portions 66 of the 7th execution mode, apply the same current potential of grid potential Vgate (Pch) with the 4th execution mode shown in Figure 24 to gate electrode 73a, simultaneously, apply positive side current potential PVdd (about 8V) to drain region 73b.At this moment, the same waveform of current potential Vch (Pch) of the current potential Vch (Pch) of the channel region 73d of the p channel transistor 73 of the 7th execution mode expression and the channel region 73d of the 4th execution mode shown in Figure 24.Thus, in the top of the p of the 7th execution mode channel transistor 73 raceway groove side, carry out the action the same with the p channel transistor 73 of above-mentioned the 4th execution mode.

In addition, in the 7th execution mode, apply positive side current potential PVdd (about 8V) to the pixel portions lightproof area 13a of the display part photomask 13 of p channel transistor 73 belows configurations.Thus, in the bottom of the p of the 7th execution mode channel transistor 73 raceway groove side, carry out the same action of bottom raceway groove side with the p channel transistor 73 of above-mentioned the 6th execution mode.Thereby the top raceway groove that is suppressed at p channel transistor 73 be cut-off state during, the bottom raceway groove conducting of p channel transistor 73.

In the 7th execution mode, as mentioned above, the current potential of the channel region 73d of p channel transistor 73 becomes corresponding to the current potential in the prescribed limit of the positive side current potential PVdd of drain region 73b.Thus, with regard to organic EL display, apply and the identical current potential of positive side current potential PVdd that applies to the drain region of p channel transistor 73 73b by pixel portions lightproof area 13a, effective voltage (potential difference) Vbc between the channel region 73d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding p channel transistor 73 can be controlled at the voltage range interior (more than the pact-2V) of the cut-off region of p channel transistor 73 to the display part photomask 13 of the p of pixel portions 66 channel transistor 73 belows configurations.Therefore, can easily suppress really since to the pixel portions lightproof area 13a of display part photomask 13 apply positive side current potential PVdd and the p of pixel portions 66 channel transistor 73 by the time, pixel portions 66 73 conductings of p channel transistor.As a result, can suppress the generation of the action failure of organic EL display.

The above-mentioned effect in addition of the 7th execution mode is the same with the effect of above-mentioned the 4th execution mode.

(the 8th execution mode)

In the 8th execution mode, the situation of the cmos circuit that is made of n channel transistor and p channel transistor in the peripheral circuit setting of liquid crystal indicator is described.

In the liquid crystal indicator of the 8th execution mode, in shift- register circuit 25 and 35, DA transducer 28, clock generating circuit 29 and the level-conversion circuit 36 of the liquid crystal indicator of first execution mode shown in Figure 1, the cmos circuit 83 that is made of n channel transistor 81 and p channel transistor 82 shown in Figure 37 is set.In addition, this n channel transistor 81 and p channel transistor 82 are examples of the present invention's ' transistor seconds '.In addition, interconnect the gate electrode 81a of n channel transistor 81 and the gate electrode 82a of p channel transistor 82.Thus, apply same potential to the gate electrode 81a of n channel transistor 81 and the gate electrode 82a of p channel transistor 82.In addition, apply positive side current potential Vdd, simultaneously, apply minus side current potential Vbb to the source region of n channel transistor 81 81a to the source region of p channel transistor 82 82b.In addition, n channel transistor 81 and p channel transistor 82 have shared drain region 84.

In addition, in the 8th execution mode, as shown in Figure 1, shift- register circuit photomask 30 and 37, DA transducer photomask 33, clock generating circuit photomask 34 and level-conversion circuit photomask 38 are set, to cover the below of the cmos circuit 83 that is provided with in shift- register circuit 25 and 35, DA transducer 28, clock generating circuit 29 and the level-conversion circuit 36 respectively.In addition, in the 8th execution mode, apply the current potential of 1/2 (Vdd+Vbb)=about 2.75V respectively to shift- register circuit photomask 30 and 37, DA transducer photomask 33, clock generating circuit photomask 34 and level-conversion circuit photomask 38.

The above-mentioned formation in addition of the liquid crystal indicator of the 8th execution mode is the same with the formation of the liquid crystal indicator of above-mentioned first execution mode.In addition, the same with above-mentioned first execution mode, apply the current potential of 1/2 (Vdd+Vbb) to the pixel portions lightproof area of the display part photomask of the n channel transistor below configuration of the pixel portions of the 8th execution mode.In addition, the same with above-mentioned first execution mode, to the sampling transistor photomask of the liquid crystal indicator of the 8th execution mode and the current potential that the buffer photomask applies 1/2 (Vdd+Vss).

Below, with reference to Figure 37 and Figure 38, the action of the cmos circuit 83 that comprises in the peripheral circuit of liquid crystal indicator of eighth embodiment of the invention is described.In addition, the threshold voltage vt h that establishes the n channel transistor that constitutes cmos circuit 83 is about 1V, and the threshold voltage vt h of p channel transistor is about-2.5V.Thus, with regard to cmos circuit 83, the voltage of n channel transistor between gate electrode and channel region is conducting state for about 1V when above, and the voltage of p channel transistor between gate electrode and channel region is that pact-2.5V is a conducting state when following.In addition, with regard to cmos circuit 83, the voltage of n channel transistor between gate electrode and channel region is cut-off state for about 0.5V when following, and the voltage of p channel transistor between gate electrode and channel region is that pact-2V is a cut-off state when above.

In the 8th execution mode, when the top raceway groove of the n of cmos circuit 83 channel transistor 81 is a cut-off state and when one of the source region of n channel transistor 81 81b and drain region 84 apply the current potential of about 7.5V, apply at photomask under the situation of current potential of 1/2 (Vdd+Vbb)=about 2.75V to correspondence, effective voltage (potential difference) Vbc between the channel region 81c of the n channel transistor 81 of this photomask and cmos circuit 83 is about 0.4V as shown in figure 38.At this moment, when the top raceway groove of the n of cmos circuit 83 channel transistor 81 was cut-off state, effective voltage (potential difference) Vbc between the corresponding photomask and the channel region 81c of n channel transistor 81 became the voltage of the cut-off region of n channel transistor 81.Thus, suppress the bottom raceway groove conducting of n channel transistor 81 at this moment.

In addition, when the top of n channel transistor 81 raceway groove is a cut-off state and when the source region of n channel transistor 81 81b and drain region 84 apply same potential, apply at the photomask to correspondence under the situation of current potential of 1/2 (Vdd+Vbb)=about 2.75V, effective voltage (potential difference) Vbc between the channel region 81c of this photomask and n channel transistor 81 is the voltage beyond about 0.4V shown in Figure 38 sometimes.At this moment, owing to do not produce potential difference between the source region 81b of n channel transistor 81 and the drain region 84, so do not flow through leakage current between source region 81b and the drain region 84.

On the other hand, when the top raceway groove (raceway groove of gate electrode 82a side) of the p of cmos circuit 83 channel transistor 82 for cut-off state and when one of the source region of p channel transistor 82 82b and drain region 84 apply the current potential of about 7.5V, apply at photomask under the situation of current potential of 1/2 (Vdd+Vbb)=about 2.75V to correspondence, effective voltage (potential difference) Vbc between the channel region 82c of the p channel transistor 82 of this photomask and cmos circuit 83 is about 0.4V as shown in figure 38.Thus, when the top raceway groove of the p of cmos circuit 83 channel transistor 82 was cut-off state, the effective voltage Vbc between the corresponding photomask and the channel region 82c of p channel transistor 82 became the voltage (more than the pact-2V) of the cut-off region of p channel transistor 82.Thus, suppress bottom raceway groove (raceway groove of the photomask side) conducting of p channel transistor 82 at this moment.

In addition, when the top of p channel transistor 82 raceway groove is a cut-off state and when the source region of p channel transistor 82 82b and drain region 84 apply same potential, apply at the photomask to correspondence under the situation of current potential of 1/2 (Vdd+Vbb)=about 2.75V, effective voltage (potential difference) Vbc between the channel region 82c of this photomask and p channel transistor 82 is the voltage beyond about 0.4V shown in Figure 38 sometimes.At this moment, owing to do not produce potential difference between the source region 82b of p channel transistor 82 and the drain region 84, so do not flow through leakage current between source region 82b and the drain region 84.

In the 8th execution mode, as mentioned above, by to shift- register circuit photomask 30 and 37, DA transducer photomask 33, clock generating circuit photomask 34 and level-conversion circuit photomask 38 apply the current potential of 1/2 (Vdd+Vbb), when the top raceway groove of the n channel transistor 81 of the cmos circuit 83 corresponding with above-mentioned each photomask and p channel transistor 82 is cut-off state, each photomask and corresponding n channel transistor 81 and p channel transistor 82 channel region 81c and the voltage Vbc between the 82c separately can be become the voltage that n channel transistor 61 and p channel transistor 62 become cut-off state respectively.Therefore, can suppress when the top raceway groove with the n channel transistor 81 of cmos circuit 83 and p channel transistor 82 remains on cut-off state respectively the bottom raceway groove conducting of n channel transistor 61 and p channel transistor 62.Thus, can suppress to comprise in the peripheral circuit liquid crystal indicator generation action failure of cmos circuit.

Below, with reference to Figure 39, illustrate the current potential that puts on photomask, with relation corresponding to the threshold voltage vt h (design load) of the p channel transistor of this photomask and n channel transistor.In addition, in Figure 39, when the insulator film thickness between the photomask that p channel transistor and n channel transistor and their belows are disposed in expression is made as 3 times of gate insulation film thicknesses of p channel transistor and n channel transistor, put on the relation of the threshold voltage vt h of the current potential of photomask and p channel transistor and n channel transistor.

Here, with reference to Figure 39, the above-mentioned first and the 4th execution mode is discussed.In the liquid crystal indicator of above-mentioned first execution mode, the effective voltage Vbc between the channel region 8d of the pixel portions lightproof area 13a of display part photomask 13 (with reference to Fig. 1) and the n channel transistor 8 of corresponding pixel portions 6 becomes pact-1.4V～about 0.1V.In addition, in the first embodiment, apply the current potential of 1/2 (Vdd+Vbb)=about 1.5V to the pixel portions lightproof area 13a of display part photomask 13.At this moment, as can be seen from Figure 39, about 0.2V because the threshold voltage vt h of n channel transistor 8 descends from about 1.0V to about 0.8V is so the voltage range of voltage range of the conducting region of n channel transistor 8 (more than about 1V) and cut-off region (about 0.5V is following) is to the direction displacement of about 0.2V that descends.At this moment, the effective voltage Vbc (pact-1.4V～about 0.1V) between the channel region 8d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding n channel transistor 8 is maintained in the voltage range (about 0.3V is following) of cut-off region of the n channel transistor 8 after the displacement.Thus, the top raceway groove of the n channel transistor 8 of the pixel portions 6 of first execution mode be cut-off state during, apply the current potential of 1/2 (Vdd+Vbb) by pixel portions lightproof area 13a to the display part photomask 13 of correspondence, under the situation that the threshold voltage vt h of n channel transistor 8 reduces, also the bottom raceway groove with n channel transistor 8 remains on cut-off state.

In addition, in the organic EL display based on above-mentioned the 4th execution mode, the effective voltage Vbc between the channel region 68d of the n channel transistor 68 of the pixel portions lightproof area 13a of display part photomask 13 and corresponding pixel portions 66 (with reference to Figure 18) becomes pact-1.4V～pact-0.3V.In addition, in the 4th execution mode, apply the current potential of 1/2 (Vdd+Vbb)=about 2.75V to the pixel portions lightproof area 13a of display part photomask 13.At this moment, as can be seen from Figure 39, about 0.4V because the threshold voltage vt h of n channel transistor 68 descends from about 1.0V to about 0.6V is so the voltage range of voltage range of the conducting region of n channel transistor 68 (more than about 1V) and cut-off region (about 0.5V is following) is to the direction displacement of about 0.4V that descends.At this moment, (pact-1.4V～pact-0.3V) is maintained in the voltage range (about 0.1V is following) of cut-off region of the n channel transistor 68 after the displacement effective voltage Vbc between the channel region 68d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding n channel transistor 68.Thus, the top raceway groove of the n channel transistor 68 of the pixel portions 66 of the 4th execution mode be cut-off state during, apply by the pixel portions lightproof area 13a to the display part photomask 13 of correspondence under the situation of current potential of 1/2 (Vdd+Vbb), also the bottom raceway groove with n channel transistor 68 remains on cut-off state.

In addition, in the organic EL display of above-mentioned the 4th execution mode, by apply the current potential of 1/2 (Vdd+Vbb)=about 2.75V to the pixel portions lightproof area 13a of display part photomask 13, as can be seen from Figure 39, the threshold voltage vt h of the p channel transistor 73 of pixel portions 66 drops to pact-2.9V from pact-2.5V.Thus, the voltage range (more than the 2V) of voltage range of the conducting region of the p channel transistor 73 of pixel portions 66 (2.5V is following) and cut-off region is to the direction displacement that descends.Therefore, the voltage range of the cut-off region of p channel transistor 73 increases.At this moment, the effective voltage Vbc between the channel region 73d of the pixel portions lightproof area 13a of display part photomask 13 and corresponding p channel transistor 73 is maintained in the voltage range of cut-off region of the p channel transistor 73 after the displacement.Thus, the top raceway groove of the p channel transistor 73 of the pixel portions 66 of the 4th execution mode be cut-off state during, apply at the pixel portions lightproof area 13a to the display part photomask 13 of correspondence under the situation of current potential of 1/2 (Vdd+Vbb), also the bottom raceway groove with p channel transistor 73 remains on cut-off state.

(the 9th execution mode)

With reference to Figure 40-Figure 42, different with above-mentioned the 4th-Di seven execution modes in the 9th execution mode, illustrate in pixel portions to be provided with respectively corresponding to the photomask of n channel transistor and situation corresponding to the photomask of p channel transistor.In addition, among Figure 40-Figure 42, each current potential of the Vdd among the figure, PVdd, Vbb and Vsig is the same with above-mentioned the 4th execution mode.That is, the current potential of Vdd and PVdd is respectively about 7.5V and about 8V.In addition, the current potential of Vbb is pact-2V, and the current potential of Vsig is about 3.5V～about 6.5V.

The organic EL display of the 9th execution mode possesses organic EL display panel 91 and is assemblied in external circuit portion 92 on the organic EL display panel 91 as shown in figure 40.Organic EL display panel 91 comprises display part 93 and is arranged on the H series driver 94 and the V series driver 95 of display part 93 peripheries.In addition, in display part 93, be configured to a plurality of pixel portions 96 rectangular.

Each pixel portions 96 as shown in figure 41, by as n channel transistor 101, auxiliary capacitor 102, anode 103, the negative electrode 104 of switch element, be clamped in the organic EL 105 in anode 103 and the negative electrode 104 and constitute as the p channel transistor 106 of driving transistors.N channel transistor 101 is configured among the regulation zone 96a of pixel portions shown in Figure 40 96, and simultaneously, p channel transistor 106 is configured among the regulation zone 96a regulation zone 96b in addition of pixel portions shown in Figure 40 96.In addition, n channel transistor 101 and p channel transistor 106 are respectively examples of ' the first transistor ' of the present invention and ' transistor seconds '.In addition, regional 96a and 96b are respectively examples of ' first area ' of the present invention and ' second area '.In addition, n channel transistor 101 and p channel transistor 106 have the structure the same with the n channel transistor 68 of above-mentioned the 4th execution mode and p channel transistor 73.That is, the threshold voltage vt h of n channel transistor 101 is about 1V, and the threshold voltage vt h of p channel transistor 106 is pact-2.5V.

In addition, as shown in figure 41, the gate electrode 101a of n channel transistor 101 is connected on the gate lines G L.Through this gate lines G L, apply positive side current potential Vdd (about 7.5V) and minus side current potential Vbb (approximately-2V) to the gate electrode 101a of n channel transistor 101.In addition, the drain region 101b of n channel transistor 101 is connected on the drain line DL.Through this drain line DL, provide the signal potential Vsig (about 3.5V～about 6.5V) of picture signal to the drain region of n channel transistor 101 101b.The source region 101c of n channel transistor 101 is connected on the gate electrode 106a of electrode of auxiliary capacitor 102 and p channel transistor 106.The drain region 106b of p channel transistor 106 is connected in the wiring 97.Through this wiring 97, provide positive side current potential PVdd (about 8V) to the drain region of p channel transistor 106 106b.The source region 106c of p channel transistor 106 is connected on the anode 103.In addition, provide positive side current potential PVdd (about 8V), simultaneously, provide each pixel portions 96 shared earthing potential GND (Vcom) to negative electrode 104 to another electrode of auxiliary capacitor 102.In addition, the circuit of the pixel portions 96 of the 9th execution mode shown in Figure 41 constitutes the same with the circuit formation of the pixel portions 66 of the 4th execution mode shown in Figure 180.

In addition, as shown in figure 40, H series driver 94 comprises H series shift-register circuit 111 and analog switch 112.Analog switch 112 is made of n channel transistor 121 and p channel transistor 122 as shown in figure 42.The threshold voltage vt h of this n channel transistor 121 and p channel transistor 122 is respectively about 1V peace treaty-2.5V.In addition, only illustrate a switch among Figure 42 corresponding to 1 drain line DL.

Physical circuit as analog switch 112 constitutes, and in the source region of drain region that connects n channel transistor 121 and p channel transistor 122, connects the source region of n channel transistor 121 and the drain region of p channel transistor 122.In addition, to the signal potential Vsig of the drain region (source region of p channel transistor 122) of n channel transistor 121 received image signal, simultaneously, go up connection drain line DL in the source region (drain region of p channel transistor 122) of n channel transistor 121.In addition, to the output signal S1 of the gate electrode of n channel transistor 121 input H series shift-register circuit 111 (with reference to Figure 40), simultaneously, to the output signal S2 of the gate electrode input H of p channel transistor 122 series shift-register circuit 111.In addition, n channel transistor 121 is disposed among the regional 112a of analog switch 112, and simultaneously, p channel transistor 122 is disposed among the regional 112a regional 112b in addition of analog switch 112.

In addition, as shown in figure 40, V series driver 95 comprises V series shift-register circuit 113 and level-conversion circuit 114.In addition, drain line DL is connected on the H series shift-register circuit 111 through analog switch 112, and simultaneously, gate lines G L is connected on the V series shift-register circuit 113 through level-conversion circuit 114.

In addition, external circuit portion 92 comprises current potential generative circuit 92a of portion and 92b.The current potential generative circuit 92a of portion is connected in the wiring 97, simultaneously, has the function of generation PVdd (about 8V) current potential.Thus, 97 provide PVdd the current potential of (about 8V) through connecting up to the drain region of p channel transistor 106 106b (with reference to Figure 41).In addition, the 92b of current potential generative circuit portion has the generation Vbb (function of current potential approximately-2V).In addition, this current potential generative circuit 92b of portion is connected on the power-supply wiring (not shown) of L level side of level-conversion circuit 114.

Here, in the 9th execution mode, n channel transistor photomask 98 is set, below with the regional 96a (n channel transistor 101 shown in Figure 41) that covers pixel portions 96, simultaneously, the p channel transistor is set with photomask 99, with the below of the regional 96b (p channel transistor 106 shown in Figure 41) that covers pixel portions 96.In addition, the n channel transistor is examples of ' first photomask ' of the present invention with photomask 98, and the p channel transistor is examples of ' second photomask ' of the present invention with photomask 99.

As concrete structure, the n channel transistor with photomask 98 have cover a plurality of pixel portions 96 regional 96a (n channel transistor 101) separately the below a plurality of light shielding part 98a, 1 gate lines G L respectively is provided with a plurality of wire 98b of portion of 1 and links the linking part 98c of a plurality of wire 98b of portion.The n channel transistor with the specified quantity light shielding part 98a corresponding to prescriptive gate polar curve GL of photomask 98 be connected in the n channel transistor with on the 98b of wire portion corresponding to prescriptive gate polar curve GL of photomask 98.In addition, the n channel transistor is formed extended at both sides along gate lines G L with a plurality of wire 98b of portion of photomask 98, simultaneously, this n channel transistor is connected in the n channel transistor with on the linking part 98c of photomask 98 with the end of a plurality of wire 98b of portion of photomask 98 in the outside of display part 93.In addition, the n channel transistor is connected on the current potential generative circuit 92b of portion of external circuit portion 92 with the linking part 98c of photomask 98.That is, the current potential generative circuit 92b of portion from external circuit portion 92 provides Vbb (fixed potential approximately-2V) to the n channel transistor with photomask 98.

In the 9th execution mode, the same with first execution mode shown in Figure 3, use between the light shielding part 98a of photomask 98 at n channel transistor 101 (with reference to Figure 41) and n channel transistor, the dielectric film (not shown) of about 3 times of thickness of gate insulating film (not shown) thickness with n channel transistor 101 is set.Therefore, be about 1/3 of the electric field strength that puts on channel region 101d to gate electrode 101a (with reference to Figure 41) when same potential is provided, from gate electrode 101a when the electric field strength that when the n channel transistor provides current potential with photomask 98, from the n channel transistor, puts on channel region 101d (with reference to Figure 41) with the light shielding part 98a of photomask 98.Therefore, with the light shielding part 98a of photomask 98 and effective voltage (potential difference) Vbc between the channel region 101d, be made as 1/3 voltage of potential difference of the current potential Vch of the current potential Vback of light shielding part 98a of n channel transistor usefulness photomask 98 and channel region 101d as the n channel transistor.That is, the n channel transistor is 1/3 (Vback-Vch) with the light shielding part 98a and the effective voltage Vbc between the channel region 101d of photomask 98.

In addition, the p channel transistor with photomask 99 have cover a plurality of pixel portions 96 regional 96b (p channel transistor 106) separately the below a plurality of light shielding part 99a, 1 gate lines G L respectively is provided with a plurality of wire 99b of portion of 1 and links the linking part 99c of a plurality of wire 99b of portion.The p channel transistor with the specified quantity light shielding part 99a corresponding of photomask 99 with prescriptive gate polar curve GL be connected in the p channel transistor with photomask 99 with a corresponding 99b of wire portion of prescriptive gate polar curve GL on.In addition, the p channel transistor is formed extended at both sides along gate lines G L with a plurality of wire 99b of portion of photomask 99, simultaneously, this p channel transistor is connected in the p channel transistor with on the linking part 99c of photomask 99 with the end of a plurality of wire 99b of portion of photomask 99 in the outside of display part 93.In addition, the p channel transistor is connected in the wiring 97 in the outside of display part 93 with the linking part 99c of photomask 99.That is, 97 provide PVdd the fixed potential of (about 8V) with photomask 99 through connecting up to the p channel transistor from the current potential generative circuit 92a of portion of external circuit portion 92.

In the 9th execution mode, the same with first execution mode shown in Figure 3, use between the light shielding part 99a of photomask 99 at p channel transistor 106 (with reference to Figure 41) and p channel transistor, the dielectric film (not shown) of about 3 times of thickness of gate insulating film (not shown) thickness with p channel transistor 106 is set.Therefore, be about 1/3 of the electric field strength that puts on channel region 106d to gate electrode 106a (with reference to Figure 41) when same potential is provided, from gate electrode 106a when the electric field strength that when the p channel transistor provides current potential with photomask 99, from the p channel transistor, puts on channel region 106d (with reference to Figure 41) with the light shielding part 99a of photomask 99.Therefore, with the light shielding part 99a of photomask 99 and effective voltage (potential difference) Vbc (Pch) between the channel region 106d, be made as 1/3 voltage of p channel transistor as the p channel transistor with the potential difference of the current potential Vch (Pch) of the current potential Vback (Pch) of the light shielding part 99a of photomask 99 and channel region 106d.That is, the p channel transistor is 1/3 (Vback (Pch)-Vch (Pch)) with the light shielding part 99a of photomask 99 and the effective voltage Vbc (Pch) between the channel region 106d.

Below, with reference to Figure 40 and Figure 41, the action of the organic EL display of the 9th execution mode is described.In addition, voltage (Vgate, Vch, Vsig, Vgc, the Vgd) variation in the n channel transistor 101 (with reference to Figure 41) of pixel portions 96 and Figure 19 and the 4th execution mode shown in Figure 20 are the same.In addition, the voltage in the p channel transistor 106 (with reference to Figure 41) of pixel portions 96 (Vgate (Pch), Vch (Pch), Vd (Pch), Vgc (Pch), Vgd (Pch)) variation and Figure 24 and the 4th execution mode shown in Figure 25 are the same.

In addition, in the 9th execution mode, since to the n channel transistor that is arranged at n channel transistor 101 belows with photomask 98 (with reference to Figure 40) provide Vbb (fixed voltage approximately-2V), thus the n channel transistor with the current potential Vback of photomask 98 be fixed on Vbb (make an appointment with-2V).In addition, the current potential Vch of the channel region 101d of n channel transistor 101 changes in the scope of about 3.5V～about 6.5V.

Therefore, the n channel transistor changes in the scope of pact-1.8V～pact-2.8V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.Thus, (pact-1.8V～pact-2.8V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 101 to the n channel transistor all the time with the effective voltage Vbc between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.As a result, be suppressed at top raceway groove with n channel transistor 101 remain on cut-off state during, the bottom raceway groove conducting of n channel transistor 101.Therefore, be suppressed at and during this period between drain region 101b and source region 101c, flow through electric current through the bottom of n channel transistor 101 raceway groove.

In addition, in the 9th execution mode, owing to provide PVdd the fixed potential of (about 8V) with photomask 99 (with reference to Figure 40), so the p channel transistor is fixed on PVdd (about 8V) with the current potential Vback (Pch) of photomask 99 to the p channel transistor that is arranged at p channel transistor 106 belows.In addition, provide and offer the fixed potential of p channel transistor to the drain region of p channel transistor 106 106b with the identical PVdd (about 8V) of the current potential of photomask 99.

Therefore, in the 9th execution mode, the same with above-mentioned the 6th execution mode, the p channel transistor changes in the scope of about 0V～about 1.5V with effective voltage (potential difference) Vbc (Pch)=1/3 (Vback (Pch)-Vch (Pch)) between the channel region 106d of the light shielding part 99a of photomask 99 and p channel transistor 106.Thus, the p channel transistor is the voltage (more than the pact-2V) of the cut-off region of p channel transistor 106 with the effective voltage Vbc (Pch) (about 0V～about 1.5V) between the channel region 106d of the light shielding part 99a of photomask 99 and p channel transistor 106 all the time.As a result, be suppressed at top raceway groove with p channel transistor 106 remain on cut-off state during, the bottom raceway groove conducting of p channel transistor 106.Therefore, be suppressed at and during this period between drain region 106b and source region 106c, flow through electric current through the bottom of p channel transistor 106 raceway groove.

In the 9th execution mode, as mentioned above, with regard to pixel portions 96, when the n channel transistor corresponding to n channel transistor 101 provides the current potential of Vbb with photomask 98, to the current potential that PVdd is provided with photomask 99 corresponding to the p channel transistor of p channel transistor 106, thus, when the n channel transistor can being fixed on the current potential of Vbb with photomask 98, the p channel transistor can be fixed on the current potential of PVdd with photomask 99.Thus, with regard to pixel portions 96, the threshold voltage vt h that can suppress n channel transistor 101 follows the n channel transistor to change with the potential change of photomask 98, simultaneously, the threshold voltage vt h that can suppress the p channel transistor 106 of pixel portions 96 follows the p channel transistor to change with the potential change of photomask 99.Therefore, with regard to pixel portions 96, can make the action of n channel transistor 101 and p channel transistor 106 stable.

In addition, in the 9th execution mode, as mentioned above, with regard to pixel portions 96, by to the current potential that Vbb is provided with photomask 98 corresponding to the n channel transistor of n channel transistor 101, simultaneously, to the current potential that PVdd is provided with photomask 99 corresponding to the p channel transistor of p channel transistor 106, can make the n channel transistor be no more than the threshold voltage vt h of n channel transistor 101 with the effective voltage Vbc between the channel region 101d of photomask 98 and n channel transistor 101, simultaneously, can make the p channel transistor be no more than the threshold voltage vt h of p channel transistor 106 with the effective voltage Vbc (Pch) between the channel region 106d of photomask 99 and p channel transistor 106.Therefore, with regard to pixel portions 96, providing the current potential of Vbb to the n channel transistor with photomask 98 and when the p channel transistor provided the current potential of PVdd with photomask 99, n channel transistor 101 and p channel transistor 106 became conducting state even can suppress.Thus, with regard to pixel portions 96, can suppress with n channel transistor 101 and p channel transistor 106 remain on cut-off state during, owing to providing current potential to make n channel transistor 101 and 106 conductings of p channel transistor with photomask 98 and p channel transistor with photomask 99 to the n channel transistor, cause the faults such as action instability of organic EL display.

In addition, in the 9th execution mode, as mentioned above, by cover the below of a plurality of pixel portions 96 n channel transistor 101 separately with photomask 98 by a n channel transistor, simultaneously, cover the below of a plurality of pixel portions 96 p channel transistor 106 separately with photomask 99 by a p channel transistor, with a plurality of n channel transistors 101 (p channel transistor 106) respectively are provided with n channel transistor with photomask 98 (p channel transistor with photomask 99), simultaneously, provide the situation of regulation current potential to compare these a plurality of n channel transistors respectively with photomask 98 (p channel transistor with photomask 99), can make to the n channel transistor provides the quantity of the wiring etc. of current potential to reduce with photomask 98 (p channel transistor with photomask 99).Thus, can suppress to comprise display part 93 increases of a plurality of pixel portions 96, maximize so can suppress organic EL display with regard to the part that the quantity that connects up reduces.

In addition, in the 9th execution mode, as mentioned above, with regard to pixel portions 96, by the dielectric film (not shown) of about 3 times of thickness of gate insulating film (not shown) thickness with n channel transistor 101 is set between n channel transistor 101 and n channel transistor are with photomask 98, can be under the situation of n channel transistor with 98 gate electrodes of not expecting of photomask, even when when the n channel transistor applies the Vbb current potential with photomask 98, because it is big with the insulator film thickness that plays the gate insulator membrane interaction between the photomask 98 to be arranged on n channel transistor 101 and n channel transistor, so can suppress to put on the n channel transistor influences n channel transistor 101 with the Vbb current potential on the photomask 98 channel region 101d.Thus, can suppress owing to causing the variation of the threshold voltage vt h of n channel transistor 101 to become big so-called defective with the current potential that photomask 98 applies Vbb to the n channel transistor.

In addition, in the 9th execution mode, as mentioned above, with regard to pixel portions 96, by the dielectric film (not shown) of about 3 times of thickness of gate insulating film (not shown) thickness with p channel transistor 106 is set between p channel transistor 106 and p channel transistor are with photomask 99, can be under the situation of p channel transistor with 99 gate electrodes of not expecting of photomask, even when when the p channel transistor applies the PVdd current potential with photomask 99, because it is big with the insulator film thickness that plays the gate insulator membrane interaction between the photomask 99 to be arranged on p channel transistor 106 and p channel transistor, so can suppress to put on the p channel transistor influences p channel transistor 106 with the PVdd current potential on the photomask 99 channel region 106d.Thus, can suppress owing to causing the variation of the threshold voltage vt h of p channel transistor 106 to become big so-called defective with the current potential that photomask 99 applies PVdd to the p channel transistor.

(the tenth execution mode)

With reference to Figure 43, in the tenth execution mode, illustrate differently, with regard to pixel portions, the photomask that covers p channel transistor below is not set and the situation of the n channel transistor usefulness photomask below the n channel transistor that has covered the switch element effect only is set with the 9th execution mode shown in Figure 40.

In the tenth execution mode, the same with the 9th execution mode shown in Figure 40 as shown in figure 43, the n channel transistor is set with photomask 98, with the below of the regional 96a (the n channel transistor 101 that plays the switch element effect shown in Figure 41) that covers pixel portions 96.On the other hand, different with the 9th execution mode shown in Figure 40 in the tenth execution mode, the p channel transistor photomask of regional 96b (the p channel transistor 106 shown in Figure 41) below that covers pixel portions 96 is not set.In addition, regional 96a is an example of ' first area ' of the present invention and ' first circuit part ', and n channel transistor 101 is examples of ' the first transistor ' of the present invention.In addition, the n channel transistor is examples of ' first photomask ' of the present invention and ' pixel portions photomask ' with photomask 98.

In addition, in the tenth execution mode, analog switch is set with photomask 131, with the regional 112a of covering analog switch 112 and the below of 112b (n channel transistor 121 shown in Figure 42 and p channel transistor 122).In addition, regional 112a and 112b are examples of ' second area ' of the present invention, ' second circuit portion ' and ' peripheral circuit portion ', and n channel transistor 121 and p channel transistor 122 are examples of ' transistor seconds ' of the present invention.In addition, analog switch is examples of ' second photomask ' of the present invention and ' peripheral circuit portion photomask ' with photomask 131.

In addition, in the tenth execution mode, externally in the circuit part 92, except that current potential generative circuit 92a of portion and 92b, the current potential generative circuit 92c of portion of the intermediate potential (1/2 (Vdd+Vbb)) that generates positive side current potential Vdd and minus side current potential Vbb is set also.In addition, above-mentioned analog switch is connected on the current potential generative circuit 92c of portion with photomask 131.The intermediate potential (1/2 (Vdd+Vbb)) of positive side current potential Vdd and minus side current potential Vbb is provided with photomask 131 to analog switch thus.

In addition, other formation of the tenth execution mode is the same with above-mentioned the 9th execution mode.

Below, with reference to Figure 41-Figure 43, the action of the organic EL display of the tenth execution mode is described.In addition, voltage (Vgate, Vch, Vsig, Vgc, the Vgd) variation in the n channel transistor 101 (with reference to Figure 41) of pixel portions 96 and Figure 19 and the 4th execution mode shown in Figure 20 are the same.In addition, the voltage in the p channel transistor 106 (with reference to Figure 41) of pixel portions 96 (Vgate (Pch), Vch (Pch), Vd (Pch), Vgc (Pch), Vgd (Pch)) variation and Figure 24 and the 4th execution mode shown in Figure 25 are the same.

In addition, in the tenth execution mode, since to the n channel transistor that is arranged at n channel transistor 101 belows with photomask 98 (with reference to Figure 43) provide Vbb (fixed voltage approximately-2V), thus the n channel transistor with the current potential Vback of photomask 98 be fixed on Vbb (make an appointment with-2V).In addition, the current potential Vch of the channel region 101d of n channel transistor 101 changes in the scope of about 3.5V～about 6.5V.

Therefore, the n channel transistor changes in the scope of pact-1.8V～pact-2.8V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.Thus, (pact-1.8V～pact-2.8V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 101 to the n channel transistor all the time with the effective voltage Vbc between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.As a result, be suppressed at top raceway groove with n channel transistor 101 remain on cut-off state during, the bottom raceway groove conducting of n channel transistor 101.Therefore, be suppressed at and during this period between drain region 101b and source region 101c, flow through electric current through the bottom of n channel transistor 101 raceway groove.

In addition, in the tenth execution mode, to the analog switch of the n channel transistor 121 that is arranged at analog switch 112 and p channel transistor 122 (with reference to Figure 42) below with photomask 131 (with reference to Figure 43) provide positive side current potential Vdd (about 7.5V) and minus side current potential Vbb (intermediate potential of pact-2V) (

).That is, analog switch is fixed on about 3.0V with the current potential Vback of photomask 131.In addition, the current potential of the channel region of the n channel transistor 121 of analog switch 112 and p channel transistor 122 changes in the scope of about 3.5V～about 6.5V (the signal potential Vsig of picture signal).

Therefore, in the tenth execution mode, analog switch changes in the scope of pact-1.2V～pact-0.2V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region of photomask 131 and n channel transistor 121 (p channel transistor 122).Thus, (pact-1.2V～pact-0.2V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 121 to analog switch all the time with the effective voltage Vbc between the channel region of photomask 131 and n channel transistor 121.In addition, (pact-1.2V～pact-0.2V) is the voltage (more than the pact-2V) of the cut-off region of p channel transistor 122 to analog switch all the time with the effective voltage Vbc (Pch) between the channel region of photomask 131 and p channel transistor 122.As a result, be suppressed at top raceway groove with n channel transistor 121 (p channel transistor 122) remain on cut-off state during, the bottom raceway groove conducting of n channel transistor 121 (p channel transistor 122).Therefore, be suppressed at during this period through the bottom raceway groove of n channel transistor 121 (p channel transistor 122) and between drain region and source region, flow through electric current.

In the tenth execution mode, as mentioned above, when the n channel transistor corresponding to the n channel transistor 101 of pixel portions 96 provides the current potential of Vbb with photomask 98, to the current potential that 1/2 (Vdd+Vbb) is provided with photomask 131 corresponding to the analog switch of analog switch 112, thus, when the n channel transistor can being fixed on the current potential of Vbb with photomask 98, can be with the current potential of analog switch with photomask 131 stuck-at-s/2 (Vdd+Vbb).Thus, the threshold voltage vt h that can suppress the n channel transistor 101 of pixel portions 96 follows the n channel transistor to change with the potential change of photomask 98, simultaneously, can suppress the n channel transistor 121 of analog switch 112 and the threshold voltage vt h of p channel transistor 122 follows analog switch to change with the potential change of photomask 131.Therefore, the n channel transistor 101 of pixel portions 96, the n channel transistor 121 of analog switch 112 and the action of p channel transistor 122 are stablized.

In addition, in the tenth execution mode, as mentioned above, by the current potential of Vbb is provided with photomask 98 to the n channel transistor corresponding to the n channel transistor 101 of pixel portions 96, simultaneously, to the current potential that 1/2 (Vdd+Vbb) is provided with photomask 131 corresponding to the analog switch of analog switch 112, can make the channel region 101d of n channel transistor 101 of pixel portions 96 and the n channel transistor is no more than n channel transistor 101 with the effective voltage Vbc between the photomask 98 threshold voltage vt h, simultaneously, can make the channel region of n channel transistor 121 (p channel transistor 122) of analog switch 112 and analog switch is no more than n channel transistor 121 (p channel transistor 122) with the effective voltage Vbc between the photomask 131 threshold voltage vt h.Therefore, providing the current potential of Vbb to the n channel transistor with photomask 98 and when analog switch provided the current potential of 1/2 (Vdd+Vbb) with photomask 131, the n channel transistor 101 of pixel portions 96 and the n channel transistor 121 of analog switch 112 (p channel transistor 122) became conducting state even can suppress.Thus, can be suppressed at the n channel transistor 101 of pixel portions 96 and the n channel transistor 121 of analog switch 112 (p channel transistor 122) remain on cut-off state during, owing to providing current potential to make n channel transistor 101 and n channel transistor 121 (p channel transistor 122) conducting with photomask 98 and analog switch with photomask 131 to the n channel transistor, thereby cause the unsettled so-called fault of action of organic EL display.

In addition, in the tenth execution mode, as mentioned above, with regard to pixel portions 96, the n channel transistor that n channel transistor 101 belows that covered the switch element effect only are set can suppress to be used for to provide the wiring of current potential to twine to the n channel transistor with photomask 98 and complicate with photomask 98 by the photomask that covers p channel transistor 106 belows is not set.In addition, provide picture signal owing to can utilize the n channel transistor 101 of switch element effect to control to pixel portions 96, so if dispose n channel transistor photomask 98 below playing the n channel transistor 101 of switch element effect, the leakage current that then can suppress the rayed generation produces the faults such as signal potential Vsig variation of picture signal that cause, that offer pixel portions 96.In addition, when the crystallizing silicon layer (active layer) of the n channel transistor 101 that has formed the switch element effect, when using laser to carry out under the situation of crystallization of crystallizing silicon layer, even if because laser is by the crystallinity generation difference of n channel transistor with photomask 98 reflections, crystallizing silicon layer, also be difficult to depend on the crystallinity of crystallizing silicon layer (active layer), so can suppress the property difference of the n channel transistor 101 of switch element effect owing to play the characteristic of the n channel transistor 101 of switch element effect.Therefore, if only covered ground, the n channel transistor 101 belows configuration n channel transistor photomask 98 of switch element effect, then can suppress to the n channel transistor provides current potential to use with photomask 98 wiring twine complicate in, inhibition comes display image with gray scale (gradation) gray scale in addition corresponding to the signal potential Vsig of picture signal.

In addition, in the tenth execution mode, as mentioned above, by the intermediate potential (1/2 (Vdd+Vbb)) of positive side current potential Vdd and minus side current potential Vbb is provided with photomask 131 to analog switch, even if comprise n channel transistor 121 and p channel transistor 122 both sides in the analog switch 112, the n channel transistor 121 of analog switch 112 and p channel transistor 122 channel region and analog switch separately can not surpass n channel transistor 121 and p channel transistor 122 threshold voltage vt h separately with the effective voltage Vbc between the photomask 131 yet.

In addition, in the tenth execution mode, as mentioned above, by being provided for generating the current potential generative circuit 92c of portion of the intermediate potential (1/2 (Vdd+Vbb)) of positive side current potential Vdd and minus side current potential Vbb in the circuit part 92 externally, can easily provide the intermediate potential (1/2 (Vdd+Vbb)) of positive side current potential Vdd and minus side current potential Vbb with photomask 131 to analog switch.

In addition, other effect of the tenth execution mode is the same with above-mentioned the 9th execution mode.

(the 11 execution mode)

With reference to Figure 44, in the 11 execution mode, in the formation of the tenth execution mode shown in Figure 43, analog switch is divided into two analog switches photomask 131a and 131b with photomask.Particularly, analog switch is arranged on photomask 131a among the regional 112a of configuration n channel transistor 121 of analog switch 112, with the below of the n channel transistor 121 (with reference to Figure 42) that covers analog switch 112.This analog switch is connected in the generation Vbb of external circuit portion 92 (approximately-2V) on the current potential generative circuit 92b of portion of current potential with photomask 131a.Thus, the current potential generative circuit 92b of portion from external circuit portion 92 provides Vbb (fixed potential approximately-2V) to analog switch with photomask 131a.In addition, regional 112a is an example of ' first area ' of the present invention and ' first peripheral circuit portion ', and analog switch is an example of ' first photomask ' of the present invention with photomask 131a.In addition, n channel transistor 121 is examples of ' the first transistor ' of the present invention.

In addition, analog switch is arranged on photomask 131b among the regional 112b of configuration p channel transistor 122 of analog switch 112, with the below of the p channel transistor 122 (with reference to Figure 42) that covers analog switch 112.This analog switch is connected in photomask 131b on the current potential generative circuit 92a of portion of generation PVdd (about 8V) current potential of external circuit portion 92.Thus, the current potential generative circuit 92a of portion from external circuit portion 92 provides PVdd the fixed potential of (about 8V) to analog switch with photomask 131b.In addition, regional 112b is an example of ' second area ' of the present invention and ' second peripheral circuit portion ', and analog switch is an example of ' second photomask ' of the present invention with photomask 131b.In addition, p channel transistor 122 is examples of ' transistor seconds ' of the present invention.

In addition, in the 11 execution mode, the same with above-mentioned the tenth execution mode, with regard to pixel portions 96, the photomask that covers p channel transistor 106 (with reference to Figure 41) below that is positioned at regional 96b is not set, and the n channel transistor photomask 98 that covers n channel transistor 101 (with reference to Figure 41) below of playing the switch element effect that is positioned at regional 96a only is set.In addition, regional 96a is an example of ' first area ' of the present invention, and the n channel transistor is examples of ' first photomask ' of the present invention with photomask 98.In addition, n channel transistor 101 is examples of ' the first transistor ' of the present invention.

In addition, other formation of the 11 execution mode is the same with above-mentioned the 9th execution mode.

Below, with reference to Figure 41, Figure 42 and Figure 44, the action of the organic EL display of the 11 execution mode is described.In addition, voltage (Vgate, Vch, Vsig, Vgc, the Vgd) variation in the n channel transistor 101 (with reference to Figure 41) of pixel portions 96 and Figure 19 and the 4th execution mode shown in Figure 20 are the same.In addition, the voltage in the p channel transistor 106 (with reference to Figure 41) of pixel portions 96 (Vgate (Pch), Vch (Pch), Vd (Pch), Vgc (Pch), Vgd (Pch)) variation and Figure 24 and the 4th execution mode shown in Figure 25 are the same.

In addition, in the 11 execution mode, since to the n channel transistor that is arranged at n channel transistor 101 belows with photomask 98 (with reference to Figure 44) provide Vbb (fixed potential approximately-2V), thus the n channel transistor with the current potential Vback of photomask 98 be fixed on Vbb (make an appointment with-2V).In addition, the current potential Vch of the channel region 101d of n channel transistor 101 changes in the scope of about 3.5V～about 6.5V.

Therefore, the n channel transistor changes in the scope of pact-1.8V～pact-2.8V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.Thus, (pact-1.8V～pact-2.8V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 101 to the n channel transistor all the time with the effective voltage Vbc between the channel region 101d of the light shielding part 98a of photomask 98 and n channel transistor 101.As a result, be suppressed at top raceway groove with n channel transistor 101 remain on cut-off state during, the bottom raceway groove conducting of n channel transistor 101.Therefore, be suppressed at and during this period between drain region 101b and source region 101c, flow through electric current through the bottom of n channel transistor 101 raceway groove.

In addition, in the 11 execution mode, the analog switch to n channel transistor 121 (with reference to Figure 42) below that is arranged at analog switch 112 provides Vbb (current potential approximately-2V) with photomask 131a.Therefore, analog switch is fixed on pact-2.0V with the current potential Vback of photomask 131a.In addition, the analog switch to p channel transistor 122 (with reference to Figure 42) below that is arranged at analog switch 112 provides PVdd the current potential of (about 8V) with photomask 131b.Therefore, analog switch is fixed on about 8V with the current potential Vback (Pch) of photomask 131b.In addition, the current potential of the channel region of the n channel transistor 121 of analog switch 112 and p channel transistor 122 changes in the scope of about 3.5V～about 6.5V (the signal potential Vsig of picture signal).

Therefore, in the 11 execution mode, analog switch changes in the scope of pact-2.8V～pact-1.8V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region of photomask 131a and n channel transistor 121.Thus, (pact-2.8V～pact-1.8V) is the voltage (about 0.5V is following) of the cut-off region of n channel transistor 121 to analog switch all the time with the effective voltage Vbc between the channel region of photomask 131a and n channel transistor 121.In addition, analog switch changes in the scope of about 0.5V～about 1.5V with effective voltage (potential difference) Vbc (Pch)=1/3 between the channel region of photomask 131b and p channel transistor 122 (Vback (Pch)-Vch (Pch)).Thus, analog switch is the voltage (more than the pact-2V) of the cut-off region of p channel transistor 122 with the effective voltage Vbc (Pch) between the channel region of photomask 131b and p channel transistor 122 (about 0.5V～about 1.5V) all the time.As a result, be suppressed at top raceway groove with n channel transistor 121 and p channel transistor 122 remain on cut-off state during, the bottom raceway groove conducting of n channel transistor 121 and p channel transistor 122.Therefore, be suppressed at during this period through the bottom raceway groove of n channel transistor 121 and p channel transistor 122 and between drain region and source region, flow through electric current.

In the 11 execution mode, as mentioned above, when providing the current potential of Vbb with photomask 98 with corresponding to the analog switch of the n channel transistor 121 of analog switch 112 with photomask 131a corresponding to the n channel transistor of the n channel transistor 101 of pixel portions 96, the current potential of PVdd is provided with photomask 131b to the analog switch corresponding to the p channel transistor 122 of analog switch 112, thus, when the n channel transistor can being fixed on the current potential of Vbb with photomask 98 and analog switch with photomask 131a, analog switch can be fixed on the current potential of PVdd with photomask 131b.Thus, the threshold voltage vt h that can suppress the n channel transistor 101 of pixel portions 96 follows the n channel transistor to change with the potential change of photomask 98, simultaneously, can suppress the n channel transistor 121 of analog switch 112 and the threshold voltage vt h of p channel transistor 122 follows analog switch to change with the potential change of photomask 131a and 131b.Therefore, the n channel transistor 101 of pixel portions 96, the n channel transistor 121 of analog switch 112 and the action of p channel transistor 122 are stablized.

In addition, in the 11 execution mode, as mentioned above, by to corresponding to the n channel transistor of the n channel transistor 101 of pixel portions 96 with photomask 98 with the current potential of Vbb is provided with photomask 131a corresponding to the analog switch of the n channel transistor 121 of analog switch 112, simultaneously, the current potential of PVdd is provided with photomask 131b to the analog switch corresponding to the p channel transistor 122 of analog switch 112, can make the channel region 101d of n channel transistor 101 of pixel portions 96 and the n channel transistor is no more than n channel transistor 101 with the effective voltage Vbc between the photomask 98 threshold voltage vt h, simultaneously, can make the channel region of n channel transistor 121 (p channel transistor 122) of analog switch 112 and analog switch is no more than n channel transistor 121 (p channel transistor 122) with the effective voltage Vbc between the photomask 131a (analog switch photomask 131b) threshold voltage vt h.Therefore, can be suppressed at when the n channel transistor provides the current potential of Vbb with photomask 98 and analog switch with photomask 131a, when analog switch provides the current potential of PVdd with photomask 131b, the n channel transistor 101 of pixel portions 96 and the n channel transistor 121 (p channel transistor 122) of analog switch 112 become conducting state.Thus, can be suppressed at the n channel transistor 101 of pixel portions 96 and the n channel transistor 121 of analog switch 112 (p channel transistor 122) remain on cut-off state during, owing to providing current potential to make n channel transistor 101 and n channel transistor 121 (p channel transistor 122) conducting with photomask 98 and analog switch with photomask 131a (analog switch photomask 131b) to the n channel transistor, cause the faults such as action instability of organic EL display.

In addition, in the 11 execution mode, as mentioned above, the analog switch that is disposed at analog switch 112 belows is divided into corresponding to the analog switch of n channel transistor 121 photomask 131a with photomask, with corresponding to the analog switch of p channel transistor 122 photomask 131b, simultaneously, to analog switch photomask 131a, 131b provides the current potential of Vbb and the current potential of PVdd respectively, thereby the channel region of n channel transistor 121 and analog switch are further reduced than the threshold voltage vt h of n channel transistor 121 with the effective voltage Vbc between the photomask 131a.In addition, the channel region of p channel transistor 122 and analog switch are further increased than the threshold voltage vt h of p channel transistor 122 with the effective voltage Vbc (Pch) between the photomask 131b.Thus, the n channel transistor 121 of analog switch 112 and the cut-off characteristics of p channel transistor 122 are improved.At this moment, different with above-mentioned the tenth execution mode in the 11 execution mode, needn't generate the intermediate potential (1/2 (Vdd+Vbb)) of positive side current potential Vdd and minus side current potential Vbb, constitute so can simplify the circuit of external circuit portion 92.

In addition, other effect of the 11 execution mode is the same with the above-mentioned the 9th and the tenth execution mode.

(the 12 execution mode)

With reference to Figure 45, in the 12 execution mode, different with the 11 execution mode shown in Figure 44, in zone corresponding to analog switch 112, the photomask that covers n channel transistor 121 (with reference to Figure 42) below that is arranged in regional 112a is not set, and the analog switch photomask 131b that covers p channel transistor 122 (with reference to Figure 42) below that is positioned at regional 112b only is set.In addition, use on the photomask 131b at analog switch.Connect to generate the current potential generative circuit 92d of portion that the positive side current potential of VVdd that offers V series driver 95 is used.

In addition, other formation of the 12 execution mode is the same with above-mentioned the 11 execution mode.

In the 12 execution mode, as mentioned above, in zone corresponding to analog switch 112, the photomask that covers n channel transistor 121 belows is not set, and the analog switch photomask 131b that covers p channel transistor 122 belows only is set, thereby can suppress to complicate with the wiring winding that photomask 131b provides current potential to use to analog switch.Here, the carrier mobility of n channel transistor 121 is bigger than p channel transistor 122 usually, has the grid width littler than the grid width of p channel transistor 122 thus.Thus, the part that reduces because of grid width of n channel transistor 121 is difficult to produce because of light and incides the misoperation that active layer causes.Therefore, even if do not dispose photomask below n channel transistor 121, it is unstable that the action of analog switch 121 also is not easy to become.Therefore, if only cover ground, the below configuration analog switch photomask 131b of the p channel transistor 122 of analog switch 112, then but the limit suppresses to complicate with the wiring winding that photomask 131b provides current potential to use to analog switch, and the limit suppresses the action instability of analog switch 112.

In addition, other effect of the 12 execution mode is the same with above-mentioned the 11 execution mode.

In addition, current disclosed execution mode is an example in all respects, should not think restrictive.Scope of the present invention is not the explanation by above-mentioned execution mode, but is illustrated by the scope of claim, and comprises implication that the scope with claim is equal to and the whole changes in the scope.

For example, in the above-described embodiment, illustrate at liquid crystal indicator and organic EL display as an example of display unit, but the invention is not restricted to this, also the present invention can be applicable to the display unit beyond liquid crystal indicator and the organic EL display.For example, also the present invention can be applicable in surface field display (SED:Surface-conduction Electron-emitterDisplay) etc.

In addition, in the above-described embodiment, the crystal silicon film that constitutes TFT is carried out channel doping, but the invention is not restricted to this, also can crystal silicon film not carried out channel doping.

In addition, in the above-described embodiment, all carry out channel doping to being configured for the n channel transistor in the organic EL display and the crystal silicon film both sides of p channel transistor respectively, but the invention is not restricted to this, also can only carry out channel doping to one of the crystal silicon film of n channel transistor or crystal silicon film of p channel transistor.At this moment, when photomask provides various current potential, in order not flow through leakage current, preferably with regard to n channel transistor and p channel transistor threshold voltage vt h difference part separately, on the basis of estimating enough and to spare, utilize above-mentioned channel doping to carry out the control of the threshold voltage vt h of n channel transistor or p channel transistor.

In addition, in the above-described embodiment, explanation with the present invention be applicable to the glass substrate that is configured in the display floater bottom make light inject to below the organic EL display of bottom emissive type of back display map, but the invention is not restricted to this, also the present invention can be applicable to the organic EL display that penetrates the top emission structure of light to the gate electrode direction.

In addition, in the above-described embodiment, by heat whole of the amorphous silicon film that is formed on the substrate with uniform illuminate condition irradiation infrared laser, form column crystallization silicon (the accurate single crystals: integrant crystal silicon film pseudo-single crystals) that utilizes along cross growth, but the invention is not restricted to this, also can be by regulating the illuminate condition of infrared laser, in pixel portions, form the crystal silicon film that constitutes by the little polysilicon of crystal grain, simultaneously, in the zone beyond the pixel portions, form the crystal silicon film that the column crystallization silicon by cross growth constitutes.Thus, when transistorized performance uniformity that can be in being arranged at pixel portions improves, in peripheral circuit portion, form high performance transistor.

In addition, in the above-described embodiment, in V series driver, level-conversion circuit is set, but the invention is not restricted to this, also can in V series driver, level-conversion circuit be set.

In addition, in the above-described embodiment, by shining infrared laser to amorphous silicon film, formation is as the crystal silicon film of transistorized active layer, but the invention is not restricted to this, also can form crystal silicon film by Ultra-Violet Laser to amorphous silicon film irradiation excimer laser etc. as transistorized active layer.

In addition, in the above-mentioned the 3rd and the 6th execution mode, constitute the drain region of the n channel transistor that connects pixel portions and the pixel portions lightproof area of the display part photomask of correspondence, but the invention is not restricted to this, also can connect the pixel portions lightproof area of source region and corresponding display part photomask of the n channel transistor of pixel portions.

In addition, in the above-described embodiment, utilize variable resistance to regulate the threshold voltage vt h of n channel transistor, but the invention is not restricted to this, also can utilize variable resistance means in addition to regulate the threshold voltage vt h of n channel transistor.

In addition, in the above-described embodiment, externally in the circuit part variable resistance is set, but the invention is not restricted to this, also variable resistance can be set in display floater.In addition, variable resistance is not limited to 1, also can be provided with a plurality of.

In addition, in the above-mentioned the 3rd and the 6th execution mode, the pixel portions lightproof area of the drain region that constitutes the n channel transistor that connects whole pixel portions and corresponding display part photomask, but the invention is not restricted to this, also can be in the pixel portions lightproof area of the drain region of the n of coupling part pixel portions channel transistor and corresponding display part photomask, the current potential of 1/2 (Vdd+Vbb) is provided to the pixel portions lightproof area corresponding to the display part photomask of the n channel transistor of rest of pixels portion.

In the above-described 8th embodiment, when the current potential of the H level that will offer cmos circuit is made as Vdd, the current potential of L level is made as Vbb, but the invention is not restricted to this, also can be made as Vdd, and the current potential of L level is made as Vss at the current potential of the H level that will offer cmos circuit.In addition, in the liquid crystal indicator of the 8th execution mode, also can use the variable resistance 41 of first execution mode shown in Figure 1 to regulate the current potential that offers photomask.

In addition, in the above-described 8th embodiment, the pairing photomask of cmos circuit in being contained in peripheral circuit portion applies the fixed potential of 1/2 (Vdd+Vbb), but the invention is not restricted to this, also can utilize the variable resistance 41 of first execution mode shown in Figure 1 to wait and regulate the current potential that puts on photomask.Constitute if so, then scalable constitutes the n channel transistor of cmos circuit and the threshold voltage of p channel transistor.Thus, can regulate the n channel transistor of photomask and cmos circuit and the effective voltage Vbc voltage between the p channel transistor channel region separately respectively, with under the situation of the voltage range of the cut-off region that exceeds n channel transistor and p channel transistor, the effective voltage Vbc between the n channel transistor of photomask and cmos circuit and the channel region separately of p channel transistor enters respectively in the voltage range of cut-off region of n channel transistor and p channel transistor.

In addition, in above-mentioned the 9th-Di 12 execution modes, Vbb is set at pact-2V, but the invention is not restricted to this, also Vbb can be set at 0V.Vbb is being set under the situation of 0V like this, for example in the formation of the tenth execution mode (with reference to Figure 43), offer the analog switch that below the n of analog switch 112 channel transistor 121 and p channel transistor 122, is provided with and become 1/2 (Vdd+Vbb)=1/2 (7.5-0) 3.75V with the current potential Vback of photomask 131.Thus, analog switch changes in the scope of pact-0.917V～about 0.083V with effective voltage (potential difference) Vbc=1/3 (Vback-Vch) between the channel region of photomask 131 and n channel transistor 121 (p channel transistor 122).In addition,

Promptly, analog switch is always the voltage (about 0.5V is following) of the cut-off region of n channel transistor 121 with the effective voltage Vbc between the channel region of photomask 131 and n channel transistor 121, simultaneously, analog switch is always the voltage (more than the pact-2V) of the cut-off region of p channel transistor 122 with the effective voltage Vbc (Pch) between the channel region of photomask 131 and p channel transistor 122.Like this, if Vbb is set at about 0V, then (the current potential generative circuit portion of current potential of pact-2V) is so can simplify the formation of external circuit portion owing to needn't be provided for generating Vbb.

In addition, in above-mentioned the 9th-Di 12 execution modes, use the n channel transistor as switching transistor, simultaneously, use the p channel transistor as driving transistors, but the invention is not restricted to this, also can when the p channel transistor is used as switching transistor, the n channel transistor be used as driving transistors.

In addition, in above-mentioned the 11 execution mode, to applying the identical PVdd current potential of current potential with the PVdd of the drain region of the p channel transistor that offers pixel portions with photomask corresponding to the analog switch of the p channel transistor of analog switch, but the invention is not restricted to this, also can also can apply and offer the identical positive side current potential of positive side current potential of V series driver to the identical positive side current potential of positive side current potential that applies and offer H series driver corresponding to the analog switch of the p channel transistor of analog switch with photomask.Under the situation that applies the positive side current potential identical to analog switch with photomask with the positive side current potential that offers H series driver corresponding to the p channel transistor of analog switch, by analog switch is configured in H series driver (analog switch) below with photomask, can suppress to complicate with the wiring winding that photomask provides current potential to use to analog switch.In addition, under the situation that applies the positive side current potential identical to analog switch with photomask with the positive side current potential that offers V series driver corresponding to the p channel transistor of analog switch, because V series driver is with the speed action lower than H series driver, become unstable because of the action of V series driver so can suppress to apply current potential.

In addition, in the 12 execution mode, the current potential of the VVdd identical with the VVdd current potential that offers V series driver is provided with photomask to analog switch, but the invention is not restricted to this, the current potential of the identical PVdd of the PVdd current potential that provides with drain region to the p of pixel portions channel transistor also can be provided, or apply and offer the identical positive side current potential of positive side current potential of H series driver.

Claims (20)

1, a kind of display unit is characterized in that, possesses:

The first area has the function of regulation, and comprises the first transistor;

First photomask is arranged in the described first area, and is disposed in the zone corresponding to described the first transistor, is provided first current potential;

Second area has the function of regulation, and comprises transistor seconds; With

Second photomask is arranged in the described second area, and is disposed in the zone corresponding to described transistor seconds, is provided second current potential.

2, display unit according to claim 1 is characterized in that:

The first area that comprises described the first transistor comprises first circuit part with predetermined function,

The second area that comprises described transistor seconds comprises the second circuit portion with predetermined function.

3, display unit according to claim 2 is characterized in that:

Described first circuit part comprises the pixel portions with described the first transistor,

Described second circuit portion comprises peripheral circuit portion, and this peripheral circuit portion is arranged on the periphery of the display part that comprises described pixel portions, has described transistor seconds,

Described first photomask comprises the pixel portions photomask that is disposed at the described the first transistor below that comprises in the described pixel portions,

Described second photomask comprises the peripheral circuit portion photomask that is disposed at the described transistor seconds below that comprises in the described peripheral circuit portion.

4, display unit according to claim 3 is characterized in that:

Described first current potential that offers described pixel portions photomask be with the gate electrode that puts on corresponding described the first transistor on the identical current potential of current potential.

5, display unit according to claim 4 is characterized in that:

Described pixel portions photomask is electrically connected on the gate electrode of described the first transistor.

6, display unit according to claim 3 is characterized in that:

Described first current potential that offers described pixel portions photomask be with one of the source region that puts on corresponding described the first transistor and drain region on the identical current potential of current potential.

7, display unit according to claim 6 is characterized in that:

Described pixel portions photomask is electrically connected on one of the source region of described the first transistor and drain region.

8, display unit according to claim 3 is characterized in that:

Described pixel portions comprises the p channel transistor,

Described first current potential that offers the described pixel portions photomask of the p channel transistor below that is disposed at described pixel portions is the positive side current potential that puts on the drain region of described p channel transistor.

9, display unit according to claim 3 is characterized in that:

Described pixel portions comprises a plurality of described the first transistors,

At least one of a plurality of the first transistors of described pixel portions plays switch element,

Mode according to the below of the first transistor that has covered described switch element effect at least disposes described pixel portions photomask.

10, display unit according to claim 3 is characterized in that:

Described first circuit part comprises a plurality of pixel portions with described the first transistor,

Cover the below of a plurality of described pixel portions the first transistor separately by a described pixel portions photomask.

11, display unit according to claim 3 is characterized in that:

Described peripheral circuit portion comprises the p channel transistor at least,

Described peripheral circuit portion photomask is configured in the below of described p channel transistor at least.

12, display unit according to claim 11 is characterized in that:

Described peripheral circuit portion also comprises the n channel transistor except that described p channel transistor,

Described peripheral circuit portion photomask is configured in the below of described n channel transistor and described p channel transistor.

13, display unit according to claim 1 is characterized in that, also comprises:

First grid dielectric film with described the first transistor of first thickness;

First dielectric film is arranged between described the first transistor and described first photomask, has second thickness more than 3 times of described first thickness of described first grid dielectric film;

Second grid dielectric film with described transistor seconds of the 3rd thickness; With

Second dielectric film is arranged between described transistor seconds and described second photomask, has the 4th thickness more than 3 times of described the 3rd thickness of described second grid dielectric film.

14, display unit according to claim 13 is characterized in that:

Described first grid dielectric film and described first dielectric film are made of same material,

Described second grid dielectric film and described second dielectric film are made of same material.

15, display unit according to claim 1 is characterized in that:

Described first current potential provides to the positive side current potential of the gate electrode of described the first transistor and the intermediate potential of minus side current potential,

Described second current potential provides to the positive side current potential of the gate electrode of described transistor seconds and the intermediate potential of minus side current potential.

16, display unit according to claim 15 is characterized in that:

The current potential generative circuit portion that also possesses the intermediate potential that is used to generate described positive side current potential and minus side current potential.

17, display unit according to claim 15 is characterized in that:

At least one side of described first area and described second area comprises n channel transistor and p channel transistor both sides.

18, display unit according to claim 1 is characterized in that:

The first area that comprises described the first transistor is arranged on pixel portions with the second area that comprises described transistor seconds,

Described first photomask is configured in the below of the first transistor in the first area that is contained in described pixel portions,

Described second photomask is configured in the below of the transistor seconds in the second area that is contained in described pixel portions.

19, display unit according to claim 18 is characterized in that:

The first transistor of described first area and the transistor seconds of described second area have mutually different conduction type.

20, display unit according to claim 1 is characterized in that:

Described first area comprises the pixel portions with described the first transistor and has first peripheral circuit portion of described the first transistor,

Described second area comprises second peripheral circuit portion with described transistor seconds,

Described first photomask is configured in the first transistor that is contained in described pixel portions and is contained in the below of the first transistor of described first peripheral circuit portion,

Described second photomask is configured in the below of the transistor seconds that is contained in described second peripheral circuit portion.

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