CN100517516C - Floating word line detection method, storage device, testing method and system thereof, and memory array - Google Patents

Abstract

Apparatus and methods capable of detecting floating word lines in a memory array are provided. The local word lines on one side of the memory array can be set to a predetermined voltage level (eg, an intermediate voltage level between V _PP and V _NWLL ) by driving the local word lines from each side with separate drive lines. After the local word line on one side is disconnected, the memory cells on the other side can be tested to detect a read failure, which indicates the presence of a floating word line on that side.

Description

Floating word line detection method, storage device, testing method and system thereof, and memory array

technical field

The present invention relates generally to testing memory devices and, more particularly, to devices and techniques capable of testing dynamic random access memory (DRAM) devices.

Background technique

Solutions in sub-micron CMOS technology have resulted in an increased demand for high-speed semiconductor memory devices, such as Dynamic Random Access Memory (DRAM), Pseudo-Static Random Access Memory (PSRAM) devices, and the like. Here, such storage devices are generally referred to as DRAM devices.

Such a device uses a memory cell (also called a storage node) usually consisting of a transistor and a capacitor. The cell is accessed by activating the word line, turning on the transistor, and connecting a capacitor to the bit line. The charge stored in the capacitor is then sensed by a sense amplifier to determine whether a "1" or a "0" is stored in the accessed cell. To optimize access to memory cells (eg, to speed up access, simplify signal traces, and/or facilitate layout), word lines are sometimes grouped and controlled through a main word line. Individual word lines in a group (called local word lines to distinguish them from main word lines) are driven by a) activating the control main word line for that group, and b) assigning a drive line to a particular word line.

FIG. 1 shows a portion of a conventional array structure 100 in a standby mode using word line group 102 controlled by main word line 110 to access memory cells 107 . As an example, each main wordline 110 controls four local wordlines 102 . In the illustrated standby mode, the word line (WL) reset line 124 is activated (indicated by the bold line), thereby pulling down each connected word line 102 to a low (or negative) word line voltage via pull-down transistor 114 level (V _NWLL ). This keeps the cell transistors connected to the word line 102 turned off, thereby maintaining information as charge stored in the cell capacitor.

FIG. 2 shows the same part of the array as in FIG. 1 . But this time in the active mode, the group of main word lines on the left indicated by the corresponding main word line 1100 bold frame is selected. As an example, the wordline 0 drive line 122 (WLDrive0) is pulled up (shown in bold) to the wordline high voltage (V _PP ), and in each wordline group, the corresponding pullup transistor is connected to V _PP .

Only in the selected main wordline group (group 0 in this example), the pull-up transistor 112 is activated, thereby connecting the corresponding local wordline 102 to _VPP through the drive line 122 (shown in bold). This causes the transistor of the corresponding memory cell 107 to turn on, thereby connecting the cell transistor to the bit line 103 . As a result, data can be read from or written to the memory cell 107 through the sense amplifier 104 via the bit line (BL) 103 . Similarly, information can be read from or written to other memory cells 107 via the same bit line as well as complementary bit line (/BL) 103 by activating the other main word line 110 and drive line 122 .

In the example shown, local word line 102 is driven from only one side. Unfortunately, this one-sided concept has the disadvantage that as soon as the drive voltage is removed from the drive side, the local word line is no longer driven and may float at an undefined level.

Simulation experiments have shown that the threshold voltage range of the "floating word line" is currently in the range of 1.3V to 1.6V. In this context, it has been observed that a memory cell connected to a floating word line may corrupt the information stored in a word line to which the memory cell is well connected (for example by maintaining the connection to the bit line), resulting in a read failure. Analysis has shown that typically only word lines that remain pulled up (area 130 shown in FIG. 2 ), for example due to a defect lacking a pull-down connection, create application-dependent problems. Unconnected actual floating word lines do not appear to be causing these problems. Unfortunately, in current designs using drive lines driven from one side, it is difficult to drive the word line to a defined intermediate V _PP level and test the state of this floating word line quickly enough (eg, before this level is lost) .

Thus, for example in wafer testing, there is no reliable way to identify chips affected by this floating word line problem. There is therefore a need for apparatus and methods that can test chips that identify chips with floating word lines that cause read failures.

Contents of the invention

Embodiments of the present invention generally provide apparatus and methods that enable testing to identify chips with floating word lines.

One embodiment provides a method of detecting floating word lines in a dynamic random access memory device having at least one memory array, wherein voltage levels are applied to different side segments of the array by different drive lines and reset lines above the word line. The method generally includes imposing to one or more first word lines in a first edge segment of the memory array an intermediate voltage level between a word line high voltage level and a negative word line low voltage level, to the One or more pull-down transistors coupled to one or more reset lines of the first side of the first word line apply a negative word line voltage level and access one or more memory cells on a second side of the memory array to detect a read failure indicating that one of the first word lines is not properly connected to the reset line through one of the pull-down transistors.

Another embodiment provides a method of testing a memory device comprising a memory array having at least a first edge segment and a second edge segment, wherein word lines in the first edge segment and word lines in the second edge segment The word lines are driven by different drive and reset lines. The method generally includes, when the memory device is in a first mode, driving word lines in the first and second edge segments in a substantially similar manner through different drive lines and reset lines, and when the memory device is in a second In the mode, the word lines in the first and second segments are driven in an independent manner through different drive lines and reset lines.

Another embodiment provides a memory array. The memory array generally includes first and second sets of one or more main word lines on respective first and second side segments of the array; a plurality of local word lines for each main word line, each local word line lines are coupled to at least one memory cell; one or more common bit lines are coupled to the memory cells on the first and second edge segments; and separate drive and reset lines allow the local word on the first edge segment The line is driven to a different voltage level than the corresponding local word line on the second edge segment.

Another embodiment provides a memory device generally including at least one memory array and control circuitry. The memory array generally includes first and second side segments, each segment including a plurality of word lines, one or more common bit lines, at least first and second pairs of drive lines and reset lines, the bit lines being passed through the second The word lines of the first and second edge segments are coupled to the accessible memory cells, and the first and second pairs of drive and reset lines are capable of driving the word lines in the first and second edge segments to different voltage levels. flat. The control circuit is generally configured to impose a voltage between a word line high voltage level and a negative word line low voltage level to one or more first word lines in the first edge segment through corresponding one or more drive lines. intermediate voltage level, applying a negative word line voltage level to one or more corresponding reset lines coupled to the first side segment of the first word line through one or more pull-down transistors, and accessing the second side of the memory array One or more memory cells on the segment to detect a read failure indicating that one of the first word lines is not properly connected to the reset line through one of the pull-down transistors.

Another embodiment provides a testing system that generally includes a storage device under test and a tester. The memory device generally includes at least one memory array having first and second side segments, each segment including a plurality of word lines, one or more common bit lines, at least first and second pairs of drive and reset lines , the bit lines are coupled to accessible memory cells through word lines in the first and second edge segments, and the first and second pairs of drive and reset lines are capable of connecting the first and second edge segments to The word lines are respectively driven to different voltage levels. The tester is typically programmed to test the memory device by placing the device in a test mode, wherein the memory device is configured to impose a word line high voltage on one or more first word lines in a first edge segment of the memory array level and the negative word line low voltage level, a negative word line is applied to one or more corresponding reset lines coupled to the first side segment of the first word line through one or more pull-down transistors. line low voltage level, and access one or more memory cells on the second side segment of the memory array.

Description of drawings

In order that the features of the invention described above may be better understood, a more particular description of the invention briefly summarized above will be rendered by reference to Examples, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

Figure 1 shows an exemplary conventional memory array segment in standby mode;

Figure 2 shows an exemplary conventional memory array segment in active mode;

3A and 3B illustrate exemplary memory array segments and corresponding signal timing diagrams in a standby state in test mode in accordance with one embodiment of the present invention;

4A and 4B illustrate exemplary memory array segments and corresponding signal timing diagrams in the active state of test mode in accordance with one embodiment of the present invention;

5 illustrates a flowchart of exemplary operations for detecting floating word lines in the memory array segments shown in FIGS. 3 and 4; and

FIG. 6 illustrates an exemplary system for testing storage devices according to one embodiment of the present invention.

Detailed ways

Embodiments of the invention generally provide apparatus and methods capable of detecting floating word lines in a memory array. The local word lines on one side of the memory array can be set to a predetermined voltage level (eg, an intermediate voltage level between V _PP and V _NWLL ) by driving the local word lines from each side with separate drive lines. After disconnecting the local word line on the one side, the memory cells on the other side can be tested for read failures, which can indicate a floating word line on the side.

As described herein, the word lines can be driven (independently) from both sides of the array by providing separate local word line drive and reset lines. As used here, the term drive line generally refers to the wire to which a drive signal is applied to connect the local word line to V _PP through the pull-up transistor of the main word line, while the term reset line generally refers to the pull-down transistor used to pass the main word line Connect the local word line to the V _NWLL wire.

For purposes of illustration, the array described here has the following feature: Although the word line drive lines and reset lines are separated, the bit line (BL) lengths are not divided. By maintaining the bit line length, cells connected to floating word lines on one side of the array can share a common bit line with cells on the other side of the array. Separating the drive and reset lines allows the word lines on both sides of the array to be independently driven during test mode (for detecting read failures caused by floating word lines). But when test mode is inactive, usually both sides are driven at the same time, as in a conventional array. Although for some embodiments the drive and reset lines are illustrated as being physically separated, the drive and reset lines may also be selectively separable, for example by some type of switching device.

Memory array with separate local word line drive lines

FIG. 3A illustrates an exemplary memory array segment 300 in an active test mode in accordance with one embodiment of the present invention. As shown, the array 300 can be divided into a left section _301L and a right section _301R (those skilled in the art will recognize that this left and right orientation is arbitrary), and the bitline pair 103 is common to both sections. of. The local word line 102 of the left segment 301 _L is driven (pull-up ₎ and reset (pull-down) by drive and reset lines 322 _L and 324 L, while the right segment 301 _{R is driven and reset by drive and reset lines 322 R and} 324 _R local word line 102 .

Because the reset and drive lines are separated, the word lines 102 in the left and right segments can be driven separately, which enables testing of floating word lines. As before, if the test mode is not active, the word lines in the left and right segments can be driven conventionally (drive and reset lines are driven in the same manner as the right). However, when the test mode is activated, the word lines 102 in the left and right segments can be driven independently (in the example shown, the test mode is configured to test the floating word line in the right segment _301R ).

For example, as shown in the corresponding timing diagram of FIG. 3B , the word line 102 in the right segment 301 _R may be driven (or forced) to an intermediate voltage level V between V _PP and V _NWLL (referred to as "intermediate V _PP "). , while the word lines in the left segment _301L remain inactive (pulled down). This intermediate voltage level may be applied to drive line 322 _R connected to local word line 102 through pull-up transistor 112 when the main word line is activated. This intermediate voltage level can be applied externally or generated internally (e.g., by a trimmable internal voltage generator), and the particular level can be selected for setting the wordlines within a voltage range that has proven problematic. within (for example, 1.3-1.6V).

Due to some defect 130, a floating word line 102 on one side of the array (e.g., right segment 301 _R ) that remains connected to a pull-up but not to a pull-down may result in a read of cells on the other side of the array (e.g., left segment 301 _L ) fail. Such defects may appear at different layers, but generally the common feature is that the pull-down is disconnected in some way (for example, due to a faulty connection to the pull-down transistor or due to faulty operation of the transistor itself). As a result, even when the intermediate voltage level is no longer driven and V _NWLL is applied to reset drive line 324, these floating word lines are not pulled down (by pull-down transistor 114) and remain at the intermediate voltage level for a period of time.

This is illustrated by the timing diagram of Figure 4B, which shows how the "good" word line is pulled down to _VNWLL , while the floating word line remains at an intermediate voltage level. As a result, the corresponding memory cell 107 associated with the floating word line access may remain connected to the bit line 103, which in turn may affect the writing of information to or from another cell 107 connected to the same bit line 103. A unit 107 reads the information. As shown in FIG. 4A, local word line segments under the defect may cause the application to fail because they do not remain connected to the pull-up. On the other hand, the word line segment shown above the defect 130 may remain connected to the pull-up when an intermediate voltage level is applied, thus causing the application to fail.

In any case, by being able to force the word lines on one side of the array to an intermediate voltage range, test data patterns can be designed to detect these read failures by accessing cells on the other side of the array. For example, these test data patterns can be chosen such that a bit of data written to a memory cell that remains connected to a bit line due to a floating word line (in one edge of the array) adversely affects memory cells in the other edge of the array. Access to one bit of data. Detecting these read failures may allow devices with defects causing floating word lines to be identified at the front end (eg, during wafer testing).

Figure 4A shows an embodiment of the proposed active state of word line segments in test mode, where word line 0 of main group 0 (in left segment _301L ) is accessed in order to detect floating word lines in right segment _301R . This word line can be accessed quickly enough after releasing the word line on the right segment _301R from the intermediate voltage that the floating word line (not connected to pull down) has not been naturally pulled down (eg by leakage). In other words, the intermediate V _PP level can be removed from the word lines on the right segment 301 _R just before the word lines in the left segment 301 _L are accessed, causing correctly connected word lines to be pulled down to V _NWLL . On the other hand, the floating word line will remain at an intermediate voltage level, which may cause memory cells 107 connected to the floating word line to remain coupled to the bit line, which in turn may affect access to the left memory cells 107 of the array 300 .

Exemplary test operation

FIG. 5 illustrates a flowchart of exemplary operations 500 for detecting floating word lines in a memory device having memory array segments as shown in FIGS. 3 and 4 in accordance with one embodiment of the present invention. As shown, if it is determined in step 502 that the device is not in a test mode (for detecting floating word lines), the word lines on both sides of the array may be driven in step 504 .

On the other hand, if the device is in test mode, the word lines on different sides of the array are independently driven as shown in steps 506-520. In step 506, as shown in FIG. 3A, the word lines on one side of the array are driven to an intermediate voltage level. Depending on the particular embodiment, any number of different word lines may be precharged to intermediate voltage levels. For example, only one or more (assuming n is the total number of main word lines, up to n/2) main word lines may be activated.

In any case, at step 508, the intermediate voltage level is removed, and at step 510, a word line low voltage (V _NWLL ) is applied to the word line through the reset line. As a result, properly connected word lines should be pulled down to V _NWLL . However, word lines that are not properly connected to pull-down will remain at an intermediate voltage level.

To detect these floating word lines, a test for read failures on the other side of the array is performed at step 512 . For example, cells on both sides of the array sharing a common bit line may have been pre-written with a data pattern as described above. If a read failure is detected at step 514 (e.g., based on a mismatch between read and written information), then it may be assumed at step 520 that there is a floating word line in the first side, and it is recognized that the device contains Defects that can be repaired in some cases (e.g. through redundancy).

If no read failure is detected, then at step 516 it is assumed that there are no floating word lines and the test can be repeated at step 518 . Depending on the particular embodiment, the test may be repeated with varying parameters, for example, by changing the value of the intermediate voltage level, by selecting different word lines or groups of word lines on the same or different sides of the array, and so on. In some cases, many of these parameters can be controlled through one or more control registers.

Exemplary Test System

For example, FIG. 6 shows an exemplary test system 600 according to an embodiment of the present invention, wherein a tester 601 is configured to execute a test program 603 that configures a storage device 610 for accessing one or more The control register 642 is tested. The test program 603 may include a set of test data patterns and operation sequences to test the floating word lines in the DRAM device 610 under test. In other words, the test program may be configured to interface with the device 610 through the interface 613 (eg, address, data, and command line) to perform the operations described above with reference to FIG. 5 .

For some embodiments, interface 613 may include a row to provide a forced external intermediate voltage level to be applied to the word line under test. For some embodiments, instead of or in addition to using an external forcing voltage, device 610 may include circuitry for internally generating intermediate voltage levels.

In any event, a data pattern designed to detect the presence of a floating word line can be written to a particular cell through addressing circuitry 630 and I/O control circuitry 650 . As previously described and shown in FIGS. 3 and 4, device 610 may include one or more memory arrays 620 with separate word line drive lines.

In operation (eg, during wafer testing), tester 601 may issue commands to write to one or more control registers 642 in order to place device 610 in test mode, select a side of array 620 for testing, and the like. The operations described above for detecting floating word lines may be performed as part of a stand-alone test or as part of a more complex test.

in conclusion

By independently driving the word lines on different sides of the array, the word lines on one side of the array can be forced to an intermediate voltage level associated with the floating word lines. These floating word lines can cause detectable read failures when accessing memory cells on the other side of the array. As a result, storage devices containing such defects can be identified on this area before they reach the front end.

While the foregoing is directed to embodiments of the invention, other embodiments of the invention can be devised without departing from the essential scope of the invention, which is defined by the claims appended hereto.

Claims (22)

1. method that is used for detecting the floating word line of dynamic random access memory device with at least one memory array, wherein by different drive wires and reset line voltage level is applied to the word line of the different edge section of described array, described method comprises:

One or more first word lines in the first limit section in described memory array are forced the intermediate voltage level between word line high-voltage level and the negative word line low voltage level;

One or more reset lines to the first limit section that is coupled to described first word line by one or more pull-down transistors apply negative word line voltage level, so that one or more first word lines of the described first limit section reach negative word line voltage level; And

One or more storage unit of visiting on the second limit section of described memory array read failure with detection, described read the failure be illustrated in during described one or more reset lines apply negative word line voltage level, one of first word line correctly is not connected to described reset line by one of pull-down transistor.

2. the method for claim 1, wherein one or more first word lines in the first limit section in described memory array are forced intermediate voltage level and are comprised external voltage signal is provided.

3. the method for claim 1, wherein one or more first word lines in the first limit section in described memory array are forced intermediate voltage level and are included in the inner voltage signal that produces of described dynamic random access memory device.

4. the method for claim 1, one or more storage unit of wherein visiting on the second limit section of described memory array comprise the one or more storage unit that are coupled to bit line and also are coupled to one of described first word line of visit.

5. method as claimed in claim 4, wherein said intermediate voltage level is in 1.3V arrives the scope of 1.6V.

6. a test has the method for the memory device of memory array, and described memory array has the first and second limit sections at least, and wherein the word line in the word line in the first limit section and the second limit section is driven by different drive wires and reset line, and described method comprises:

When test pattern is not activated, drive word line in the first and second limit sections in an identical manner by different drive wires and reset line;

When described test pattern is activated, drive word line in the first and second limit sections by different drive wires and reset line in mode independent of each other, wherein, drive word line independently and comprise the word line in the described first limit section is urged to intermediate voltage level between word line high-voltage level and negative word line low voltage level, and the described word line in the described second limit section remains on described negative word line low voltage level.

7. method as claimed in claim 6 wherein comprises with the word line that mode independently drives in the first and second limit sections:

One or more word lines in the described first limit section are forced the intermediate voltage level between word line high-voltage level and the negative word line low voltage level.

8. method as claimed in claim 7 wherein also comprises with the word line that mode independently drives in the first and second limit sections:

One or more storage unit on the second limit section of reference-to storage array read failure with detection, and described one of failure expression first word line that reads correctly is not connected to reset line on the first limit section by pull-down transistor.

9. memory array comprises:

Second group of one or more main word lines on first group of the one or more main word lines on the first limit section of array and the second limit section at array;

By a plurality of local word line of each main word line control, each local word line all is coupled with at least one storage unit;

Be coupled to one or more common bit lines of the storage unit of the first and second limit sections on both;

The drive wire and the reset line that separate, permission is urged to intermediate voltage level between word line high-voltage level and negative word line low voltage level with the local word line on the first limit section, and the described word line in the described second limit section remains on described negative word line low voltage level.

10. memory array as claimed in claim 9, wherein each drive wire is by being coupled to local word line by pulling up transistor of corresponding main word line control.

11. memory array as claimed in claim 9, wherein each reset line is coupled to local word line by the pull-down transistor by corresponding main word line control.

12. a memory device comprises:

Memory array with first and second limit sections, each section comprises a plurality of word lines, one or more common bit lines and at least the first and second drive wires and reset line, described common bit lines can be coupled to addressable storage unit by the word line of the first and second limit sections among both, and first and second drive wires can be driven into different voltage levels with the word line in the first and second limit sections with reset line;

Control circuit is configured to:

By the one or more drive wires in first drive wire of the first limit section one or more first word lines in the first limit section are driven into intermediate voltage level between word line high-voltage level and the negative word line low voltage level;

One or more reset lines in first reset line of the first limit section apply negative word line voltage level, and described first reset line is coupled to described first word line by one or more pull-down transistors;

One or more storage unit on the second limit section of reference-to storage array read failure with detection, and described one of failure expression first word line that reads correctly is not connected to described reset line by one of pull-down transistor.

13. memory device as claimed in claim 12 also is included in the inner circuit that produces the voltage signal of intermediate voltage level.

14. memory device as claimed in claim 13, wherein said intermediate voltage level are outside adjustable.

15. memory device as claimed in claim 12 also comprises one or more control registers of writing, so that make described equipment place test pattern.

16. memory device as claimed in claim 15, wherein one or more control registers allow to select during test pattern word line to be forced intermediate voltage level.

17. a test macro comprises:

Memory device with at least one memory array, described memory array has the first and second limit sections, each section comprises a plurality of word lines, one or more common bit lines and at least the first and second pairs of drive wires and reset line, described common bit lines can be coupled to addressable storage unit by the word line of the first and second limit sections among both, and first and second pairs of drive wires can be driven into different voltage levels with the word line in the first and second limit sections independently with reset line;

Tester, be programmed to by making memory device place test pattern to test this equipment, wherein said memory device is configured to one or more first word lines in the first limit section of memory array and forces intermediate voltage level between word line high-voltage level and the negative word line low voltage level, one or more reset lines to the first limit section that is coupled to described first word line by one or more pull-down transistors apply negative word line voltage level, and the one or more storage unit on the second limit section of reference-to storage array.

18. the described test macro of claim 17, wherein said tester is configured to relatively data value that obtains from the one or more storage unit on the second limit section of array of being visited and the data of before having write this array, to detect the floating word line in the first limit section of this array.

19. test macro as claimed in claim 17, wherein said tester are configured to change intermediate voltage level and repeat this test.

20. test macro as claimed in claim 19, wherein said tester are configured to change described intermediate voltage level by the voltage generator of regulating this device interior under test.

21. test macro as claimed in claim 17, wherein said tester provide the voltage signal that is in described intermediate voltage level to described equipment.

22. a memory device comprises:

Be used to store first memory storage of data;

Be used to store second memory storage of data, the storage unit in wherein said first and second memory storages is coupled to the shared set of sensing amplifier by bit line;

Be used to activate the active device of first memory storage;

Be coupled to first drive unit of first memory storage, be used to drive word line devices and reach intermediate voltage level between word line high-voltage level and the negative word line low voltage level;

First resetting means is used for by one or more pull-down transistors negative word line voltage level being applied to described active device;

Pick-up unit is used to visit second memory storage and detects the active device that floats, and it is characterized in that the defective between pull-down transistor and the active device connects.

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