CN100517512C - Shift register - Google Patents

Abstract

A shift register comprises a signal generating circuit, a driving circuit, a reset circuit and a control switch. The signal generating circuit comprises a first switch and a second switch, wherein the first switch is used for generating a first output signal according to a clock signal when being started, and the second switch is used for generating a second output signal according to the clock signal when being started and transmitting the second output signal to the output end of the shift register. The driving circuit is used for controlling the first switch and the second switch of the signal generating circuit according to the input signal received by the input end of the shift register. The reset circuit is used for closing the first switch and the second switch of the signal generating circuit and resetting the output signal output by the output end. The control switch is used for resetting the output signal output by the output end.

Description

Shift Register

technical field

The invention relates to a shift register, in particular to a shift register capable of accelerating response time.

Background technique

A liquid crystal display is a flat panel display made of a glass substrate. In order to save the manufacturing cost of the liquid crystal display, it is a future trend to fabricate the driving control circuit on the glass substrate of the liquid crystal display in the form of thin film transistors, and most of them currently adopt the amorphous silicon process.

Please refer to FIG. 1 to FIG. 3 at the same time, FIG. 1 is a schematic diagram of a known liquid crystal display 100, FIG. 2 is a schematic diagram of the gate drive circuit 120 of the liquid crystal display 100 in FIG. 1, and FIG. Schematic diagram of the register. As shown in FIG. 1 , the liquid crystal display 100 includes a display array 110 , a control circuit 124 , and a gate driving circuit 120 . The display array 110 is used to display images. The control circuit 124 is used to generate signals required for the operation of the gate driving circuit 120 , such as a first clock signal CK, a second clock signal XCK, and a start signal ST. The gate driving circuit 120 is used to drive the display array 110 . As shown in FIG. 2 , the gate drive circuit 120 includes a multi-stage shift register 122, and each stage of the shift register 122 is coupled in series, and sequentially according to the first clock signal CK and the second clock signal XCK The gate signal GOUT is generated to drive the display array 110, and the phase of the second clock signal XCK is opposite to that of the first clock signal CK, and in the signal connection of each shift register 122, the first clock signal CK and The second clock signal XCK is interchanged in turn, that is, the clock signal input terminal CK1 and the clock signal input terminal CK2 are alternately coupled with the first clock signal CK and the second clock signal XCK. Each stage of the shift register 122 has an output terminal OUT, an input terminal IN, and a feedback terminal FB, and includes a signal generating circuit 310 , a driving circuit 320 , a reset circuit 330 , and a control switch 340 . As shown in FIG. 3 , the signal generating circuit 310 includes a switch, such as a thin film transistor TFT7, which is used to generate a switch at the output terminal OUT of the shift register 122 according to the first clock signal CK (it can also be the second clock signal XCK) when turned on. Gate signal GOUT(N). The driving circuit 320 controls the signal generating circuit 310 according to the input signal received by the input terminal IN of the shift register 122 . The input signal received by the input terminal IN of the shift register 122 is the gate signal GOUT(N−1) or the start signal (ST) output by the output terminal of the previous stage of the shift register. The reset circuit 330 is used to turn off the signal generating circuit 310 and reset the gate signal GOUT(N) output from the output terminal OUT (that is, to pull down the voltage of the output terminal OUT to a specific low potential VSS). The control switch 340 is used to reset the gate signal GOUT(N) output by the output terminal OUT according to the feedback signal received by the feedback terminal FB; wherein, the feedback signal received by the feedback terminal FB is a second-stage shift register The gate signal GOUT(N+1) outputted by the output terminal of .

Although both the control switch 340 and the reset circuit 330 are used to reset the gate signal GOUT(N) output from the output terminal OUT, the control switch 340 is only used when receiving the gate signal GOUT(N) output by the next-stage shift register. +1), the reset circuit 330 works continuously for a long time. Because in the amorphous silicon manufacturing process, if the thin film transistor works for a long time, its efficiency will be reduced, and even its working life will be reduced. Therefore, it is necessary to use a control switch 340 that only works once in a cycle, so as to avoid noise interference and affect the output and extend the life of the product.

In order to more clearly describe the operation details of the known shift register 122 , please refer to FIG. 4 and also refer to FIG. 3 . FIG. 4 is a timing diagram of various related signals of the shift register 122 shown in FIG. 3 during operation. As shown in Figure 4, within time T1, the input signal received by the input terminal IN (that is, the gate signal GOUT(N-1) output by the output terminal of the previous stage shift register or the start signal (ST )) is raised to a high potential, thereby turning on the thin film transistor TFT ₁ of the driving circuit 320, and further turning on the thin film transistor TFT ₇ of the signal generating circuit 310, but the first clock signal CK is at a low potential at time T1, so the output terminal OUT The output gate signal GOUT(N) is still at a low potential; in addition, the input signal GOUT(N-1) or the start signal ST also turns on the thin film transistor TFT ₄ of the reset circuit 330, so that the terminal _N2 drops to a low potential, Therefore, the reset circuit 330 also stops the operation of the shutdown signal generating circuit 310; however, the terminal _N3 remains at a high potential due to the continuous supply of the DC voltage VDD, so the reset circuit 330 still resets the gate signal GOUT output by the output terminal OUT (N), that is, the gate signal GOUT(N) output from the output terminal OUT is lowered to a low potential. The control switch 340 does not work because the feedback signal GOUT(N+1) of the feedback terminal FB is at a low potential.

During the time T2, the input signal GOUT(N-1) or the start signal ST received by the input terminal IN is lowered to a low potential, thereby turning off the thin film transistor TFT ₁ of the driving circuit 320, but the thin film transistor TFT 1 of the signal generating circuit 310 The transistor TFT ₇ is still turned on, and the terminal _N1 is pulled high again due to the parasitic capacitance effect when the first clock signal CK rises to a high potential, and the gate signal GOUT(N) output from the output terminal OUT also becomes a high potential. In addition, the reset circuit 330 still stops the operation of the shutdown signal generating circuit 310 because the terminal _N2 is still at a low potential (the second clock signal XCK is at a low potential at time T2), and the reset circuit 330 also stops because the terminal _N3 is low. The gate signal GOUT(N) output from the output terminal OUT is low (the gate signal GOUT(N) output from the output terminal OUT turns on the thin film transistor TFT ₆ ) and the reset of the gate signal GOUT(N) output from the output terminal OUT is stopped. The control switch 340 still does not work because the feedback signal GOUT(N+1) of the feedback terminal FB is at a low potential.

In time T3, because the feedback signal GOUT(N+1) of the feedback terminal FB rises to a high potential, the thin film transistor TFT ₉ of the control switch 340 is turned on, and then the gate signal GOUT(N) output from the output terminal OUT is reduced to low potential. The reset circuit 330 turns on the thin film transistor TFT ₂ because the second clock signal XCK rises to a high potential, and thus turns off the thin film transistor TFT ₇ of the signal generating circuit 310, and the reset circuit 330 also turns on because the terminal N ₃ rises to a high potential. The gate signal GOUT(N) output from the output terminal OUT is reset again, that is, the gate signal GOUT(N) output from the output terminal OUT is lowered to a low potential.

In the following time, the reset circuit 330 will continue to work to close the signal generating circuit 310 and reduce the gate signal GOUT(N) output from the output terminal OUT to a low potential until the input signal GOUT(N-1 ) or the start signal ST rises to a high potential again. Furthermore, the shift register 122 of the next stage also repeats the above operations, so that the gate signal GOUT can be sequentially generated to drive the display array 110 .

However, the gate signal GOUT output by each shift register 122 is not only used to drive the display array 110, but also needs to be output to the input terminal IN of the next shift register 122 and the input terminal IN of the previous shift register 122. The feedback terminal FB thus increases the burden on the output terminal OUT, and further increases the rising time (rising time) of the gate signal GOUT output by each stage of the shift register 122 . In addition, in addition to the increase of the rising time of the gate signal GOUT, the feedback signal received by the previous stage shift register will also attenuate, so the falling time of the gate signal GOUT output by the previous stage shift register 122 (falling time )Increase. Therefore, the known shift register 122 has a relatively long response time.

Contents of the invention

Therefore, the object of the present invention is to propose a shift register with faster response time to solve the known problems.

The shift register of the present invention includes a signal generating circuit, a driving circuit, a reset circuit, and a control switch. The signal generating circuit includes a first switch and a second switch, the first switch is used to generate a first output signal according to a clock signal when turned on, the second switch is coupled to the output end of the shift register, and is used for When turned on, a second output signal is generated according to the clock signal and sent to the output end of the shift register. The driving circuit is coupled to the first switch and the second switch of the signal generating circuit, and is used to control the first switch and the second switch of the signal generating circuit according to the input signal received by the input end of the shift register . The reset circuit is coupled to the signal generating circuit, and is used for closing the first switch and the second switch of the signal generating circuit and resetting the output signal output from the output terminal. The control switch is coupled to the output end of the shift register and the signal generating circuit of the subsequent shift register, and is used to reset the output signal output by the output end. Wherein the first switch of the signal generating circuit is coupled to the feedback end of the previous stage shift register, and is used to generate an output signal to the control switch of the previous stage shift register according to the clock signal when turned on.

According to another aspect of the present invention, there is also provided a thin film transistor liquid crystal display, including: a display array, and a gate drive circuit, used to generate a plurality of gate signals to drive the display array, the gate drive circuit includes a multi-stage The shift registers are coupled in series, each stage of the shift register has an input end and an output end, and each stage of the shift register includes: a signal generating circuit, including: a first switch, used for switching on Generate a first output signal according to a clock signal; and a second switch, coupled to the output end of the shift register, used to generate a second output signal according to the clock signal when turned on, and transmit it to the output end of the shift register ; a drive circuit, coupled to the first switch and the second switch of the signal generating circuit, used to control the first switch and the second switch of the signal generating circuit according to the input signal received by the input terminal of the shift register; a reset circuit, coupled to the signal generating circuit, for closing the first switch and the second switch of the signal generating circuit and resetting the output signal output by the output terminal; and a control switch, coupled to the shift register The output terminal and the signal generating circuit of the subsequent stage shift register are used to reset the output signal output by the output terminal. Wherein the first switch of the signal generating circuit is coupled to the feedback end of the previous stage shift register, and is used to generate an output signal to the control switch of the previous stage shift register according to the clock signal when turned on.

Description of drawings

FIG. 1 is a schematic diagram of a known liquid crystal display.

FIG. 2 is a schematic diagram of a gate driving circuit of the liquid crystal display shown in FIG. 1 .

FIG. 3 is a schematic diagram of a shift register of the gate driving circuit of FIG. 2 .

FIG. 4 is a schematic timing diagram of various related signals of the shift register of FIG. 3 during operation.

FIG. 5 is a schematic diagram of a liquid crystal display of the present invention.

FIG. 6 is a schematic diagram of a gate driving circuit of the liquid crystal display shown in FIG. 5 .

FIG. 7 is a schematic diagram of a shift register of the gate driving circuit of FIG. 6 .

FIG. 8 is a comparison diagram of gate signals output by the shift register of the present invention and a known shift register.

[Description of main component labels]

100, 500 LCD display 110, 510 display array

120, 520 gate drive circuit 122, 522 shift register

310, 710 Signal generating circuit 320, 720 Driving circuit

330, 730 reset circuit 340, 740 control switch

CK1, CK2 Clock signal input terminal IN Input terminal

OUT Output Terminal FB Feedback Terminal

FBO Feedback output terminal FS Feedback signal

VSS Specific Low Potential VDD DC Voltage

CK first clock signal XCK second clock signal

ST Start signal GOUT Gate signal

N ₁ , N ₂ , N ₃ , N ₁₁ , terminal TFT thin film transistor

N ₁₂ , N ₁₃

124, 524 control circuit

Detailed ways

Please refer to FIG. 5 to FIG. 7 at the same time. FIG. 5 is a schematic diagram of a liquid crystal display 500 of the present invention, FIG. 6 is a schematic diagram of a gate drive circuit 520 of a liquid crystal display 500 shown in FIG. Schematic of a shift register. The liquid crystal display 500 of the present invention includes a display array 510 , a control circuit 524 , and a gate driving circuit 520 . The display array 510 is used to display images. The control circuit 524 is used to generate signals required for the operation of the gate driving circuit 520 , such as a first clock signal CK, a second clock signal XCK, and a start signal ST. The gate driving circuit 520 is used to drive the display array 510 . The gate driving circuit 520 includes a multi-stage shift register 522, and each stage of the shift register 522 is coupled in series, and sequentially generates the gate signal GOUT according to the first clock signal CK and the second clock signal XCK to Drive the display array 510, and the phase of the second clock signal XCK is opposite to the phase of the first clock signal CK, and in the signal connection of each stage of shift register 522, the first clock signal CK and the second clock signal XCK are Alternately interchanged, that is, the clock signal input terminal CK1 and the clock signal input terminal CK2 are alternately coupled with the first clock signal CK and the second clock signal XCK. Unlike known ones, the signal generating circuit 710 of each stage of the shift register 522 includes a first switch and a second switch, such as a thin film transistor TFT ₆₀ and a thin film transistor TFT ₅₇ . As shown in FIG. 7 , the thin film transistor TFT ₅₇ (the second switch) of the signal generation circuit 710 is used to switch on the output end of the shift register 522 according to the first clock signal CK (it can also be the second clock signal XCK) when it is turned on. OUT generates the gate signal GOUT(N), and the thin film transistor TFT ₆₀ (the first switch) of the signal generating circuit 710 is used for shifting according to the first clock signal CK (it can also be the second clock signal XCK) when turned on. The feedback output terminal FBO of the register 522 generates a feedback signal FS(N). The driving circuit 720 is used to control the thin film transistor TFT ₆₀ and the thin film transistor TFT ₅₇ of the signal generating circuit 710 according to the input signal received by the input terminal IN of the shift register 522, and the input received by the input terminal IN of the shift register 522 The signal is the gate signal GOUT(N-1) or the start signal (ST) output from the output terminal of the shift register of the previous stage. The reset circuit 730 is used to turn off the thin film transistor TFT ₆₀ and the thin film transistor TFT ₅₇ of the signal generating circuit 710, and reset the gate signal GOUT(N) output from the output terminal OUT (that is, to pull down the voltage of the output terminal OUT to a specific low Potential VSS). The control switch 740 is used to reset the gate signal GOUT(N) output from the output terminal OUT according to the feedback signal received by the feedback terminal FB, and the feedback signal received by the feedback terminal FB is the feedback output of the next-stage shift register The feedback signal FS(N+1) output from terminal FBO.

Since the feedback signal FS received by the control switch 740 of each stage shift register 522 is generated by the first switch of the signal generating circuit of the next stage shift register, to replace the output output of the next stage shift register The gate signal GOUT(N+1), that is, the control switch 740 can reset the gate of the output terminal OUT according to the feedback signal FS(N+1) generated by the first switch of the signal generating circuit of the next-stage shift register. Pole signal GOUT(N), so the output terminal OUT of the shift register 522 need not be coupled to the feedback terminal FB of the previous stage of shift register, that is, the burden of the output terminal OUT is reduced, and thus the number of shift registers of each stage is reduced. The rise time of the gate signal GOUT output by 522. In addition, since the feedback signal FS generated by the first switch of the signal generating circuit 710 is only provided to the control switch of the previous stage shift register, the previous stage shift register The received feedback signal FS will not attenuate, thereby reducing the falling time of the gate signal GOUT output by the previous stage shift register 122 . Therefore, the shift register 522 of the present invention has a shorter response time.

Please refer to FIG. 8 , which is a comparison diagram of the gate signal GOUT output by the shift register 522 of the present invention and the conventional shift register 122 . As shown in Figure 8, after being simulated by SPICE circuit simulation software, the rise time of the gate signal GOUT(N) output by the Nth stage shift register 522 of the present invention is shorter than that of the gate signal output by the known Nth stage shift register 122 The rise time of GOUT (N) is faster by 0.45 microseconds, and the fall time of the gate signal GOUT (N-1) output by the N-1 shift register 522 of the present invention is shorter than that of the known N-1 shift register The falling time of the gate signal GOUT(N-1) output by 122 is 0.30 microsecond faster.

Based on the above, the signal generation circuit 710 of the shift register 522 of the present invention includes a first switch TFT ₆₀ and a second switch TFT ₅₇ , and the first switch TFT ₆₀ is used to generate a feedback signal FS at the feedback output terminal FBO of the shift register 522 , and the second switch TFT ₅₇ is used to generate the gate signal GOUT at the output terminal OUT of the shift register 522, so the gate signal GOUT output by each stage of shift register 522 does not need to be provided to the previous stage of shift register The feedback terminal FB is provided by the feedback signal FS generated by the first switching TFT ₆₀ at the feedback output terminal FBO.

Compared with the known technology, the output terminal OUT of the shift register 522 of the present invention does not need to be coupled to the feedback terminal FB of the previous stage shift register 522, so the burden of the output terminal OUT of each stage shift register 522 can be reduced. , thereby reducing the rising time (rising time) and falling time (falling time) of the gate signal GOUT. Therefore, the shift register 522 of the present invention has a shorter response time.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (5)

1. A shift register has an input terminal and an output terminal, comprising: Signal generation circuit, including: The first switch is used to generate a first output signal according to the clock signal when turned on; and A second switch, coupled to the output end of the shift register, is used to generate a second output signal according to the clock signal when turned on, and transmit it to the output end of the shift register; a driving circuit, coupled to the first switch and the second switch of the signal generating circuit, used to control the first switch and the second switch of the signal generating circuit according to the input signal received by the input terminal of the shift register; a reset circuit, coupled to the signal generating circuit, for closing the first switch and the second switch of the signal generating circuit and resetting the output signal output by the output terminal; and A control switch, coupled to the output end of the shift register and the signal generating circuit of the subsequent shift register, is used to reset the output signal output by the output end, Wherein the first switch of the signal generating circuit is coupled to the feedback end of the previous stage shift register, and is used to generate an output signal to the control switch of the previous stage shift register according to the clock signal when turned on. 2. The shift register according to claim 1, wherein the first switch and the second switch are thin film transistors. 3. A thin film transistor liquid crystal display, comprising: display array, and The gate drive circuit is used to generate a plurality of gate signals to drive the display array. The gate drive circuit includes a multi-stage shift register, which is coupled in series, and each stage of the shift register has an input terminal And the output terminal, each stage of shift register contains: Signal generation circuit, including: The first switch is used to generate a first output signal according to the clock signal when turned on; and A second switch, coupled to the output end of the shift register, is used to generate a second output signal according to the clock signal when turned on, and transmit it to the output end of the shift register; a driving circuit, coupled to the first switch and the second switch of the signal generating circuit, used to control the first switch and the second switch of the signal generating circuit according to the input signal received by the input terminal of the shift register; a reset circuit, coupled to the signal generating circuit, for closing the first switch and the second switch of the signal generating circuit and resetting the output signal output by the output terminal; and A control switch, coupled to the output end of the shift register and the signal generating circuit of the subsequent shift register, is used to reset the output signal output by the output end, Wherein the first switch of the signal generating circuit is coupled to the feedback end of the previous stage shift register, and is used to generate an output signal to the control switch of the previous stage shift register according to the clock signal when turned on. 4. The liquid crystal display according to claim 3, further comprising a control circuit coupled to the gate drive circuit for generating the clock signal, and an input of the first stage shift register of the gate drive circuit terminal generates a start signal. 5. The liquid crystal display according to claim 3, wherein the first switch and the second switch are thin film transistors.

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