CN100517459C - Image processing device - Google Patents

Abstract

An image processor is provided to increase a speed of entire image processing by efficiently operating a CPU. In the image processor (1), a high-speed bus (10) and a peripheral bus (12) are connected via a bus bridge (11). The CPU (13) for performing calculation and control of image processing, a data transmitting/receiving FIFO memory (18) for transmitting and receiving image compression data to and from a host device (4), a frame memory (16) for storing image decompression data from an electronic camera (2), etc. and displaying the data on a display panel (3), and a compression/decompression circuit (17) for compressing the image decompression data and decompressing the image compression data are connected to the both buses (10, 12). The CPU (13) and the frame memory (16) are connected to the high-speed bus (10), and the data transmitting/receiving FIFO memory (18) is connected to the peripheral bus (12).

Description

image processing device

technical field

The present invention relates to an image processing device that performs compression/decompression of image data.

Background technique

In recent years, in addition to displaying image data, electronic devices such as mobile phones are equipped with an electronic camera function to both display and store captured image data. Therefore, such an electronic device needs to perform complex processing of a large amount of image data, and an image processing device using a CPU is generally used (for example, Patent Documents 1 and 2). FIG. 3 shows an example of a conventional image processing device. The image processing device 101 adopts a bus architecture in which a high-speed bus 10 and a peripheral bus 12 are connected via a bus bridge 11, and various functional circuits are connected to the two buses 10 and 12. That is, the following components are connected to the high-speed bus 10: CPU 13, which performs calculation and control required in image processing, etc.; ROM 14, which stores the processing program of CPU 13; RAM 15, which is used as a work area for calculation performed by CPU 13 wait. Furthermore, the following components are connected to the peripheral bus 12: a frame memory 16, which stores the image decompression data from the electronic camera 2 and the image decompression data after decompressing the image compression data from the host device 4, and displays the data on the In display panel 3 such as LCD; Compression/decompression circuit 17, it carries out the compression of image decompression data and the decompression of image compression data; The sending and receiving; And general-purpose timer circuit 19 etc. In addition, the image processing device 101 includes: a register 20 for frame memory, which is read/written by the CPU 13, and data in the frame memory 16; a register 21 for compression/decompression circuits, which is read/write by the CPU 13, and data of the compression/decompression circuit 17; The register 22 for transmission and reception is used by the CPU 13 to read/write data in the FIFO memory 18 for data transmission and reception. In addition, in this application, image compression data refers to compressed image data, and image decompression data refers to uncompressed image data.

The image decompression data from the electronic camera 2 is stored in the frame memory 16 and displayed on the display panel 3, and is read into the CPU 13 via the frame memory register 20 and the peripheral bus 12, and is processed by the compression/decompression circuit 17 and the RAM 15. compression. The compressed image data is written into the data transmission and reception FIFO memory 18 via the peripheral bus 12 and the data transmission and reception register 22 , and is sequentially transmitted to the host device 4 . On the other hand, the FIFO memory 18 for data transmission and reception receives the compressed image data from the host device 4, and the compressed image data is sequentially read into the CPU 13 via the register 22 for transmission and reception of data and the peripheral bus 12, and passed through the compression/decompression circuit 17. and RAM15 etc. are decompressed. The decompressed image data is stored in the frame memory 16 via the peripheral bus 12 and the frame memory register 20 and displayed on the display panel 3 .

Patent Document 1: JP-A-2001-350461 Gazette;

Patent Document 2: Japanese Unexamined Patent Publication No. 2002-77709.

Contents of the invention

Although image processing is performed as described above, there is an increasing demand for high-speed image processing in order to achieve higher quality of displayed images, various processing of moving images and still images, and the like. In general, to increase the speed of image processing, various circuits including a CPU are increased in speed, but it is also important to operate the CPU efficiently in consideration of power consumption and cost.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an image processing device capable of speeding up image processing by operating a CPU more efficiently.

In order to solve the above-mentioned problems, the image processing device according to the preferred embodiment of the present invention connects the high-speed bus and the peripheral bus via a bus bridge, and connects the following components to the high-speed bus and the peripheral bus: CPU, which performs image processing operations and control; FIFO memory for data transmission and reception, which transmits and receives image compressed data with the host device; frame memory, which stores image decompression data and displays the data on the display panel; and compression/decompression circuit, which compresses image decompression data In an image processing device for decompressing image compressed data, the above CPU and frame memory are connected to a high-speed bus, the above-mentioned FIFO memory for data transmission and reception is connected to a peripheral bus, and the above-mentioned compression/decompression circuit is connected to a high-speed bus, and the high-speed bus The processing capability of the peripheral bus is relatively high, and the processing capability of the peripheral bus is relatively low.

An image processing device according to another preferred embodiment of the present invention has a CPU direct connection bus for instructions, a CPU direct connection bus for data, and a high-speed bus, and the following components are connected to these buses: a CPU that performs calculations for image processing and Control; ROM, which stores the processing program of the CPU; RAM, which is used as a work area for calculations performed by the CPU; FIFO memory for data transmission and reception, which performs transmission and reception of image compressed data with the host device; frame memory, which stores image decompression data And display this data on the display panel; and compression/decompression circuit, in the image processing device that it carries out the compression of the image decompression data and the decompression of the image compression data, the above-mentioned CPU and ROM are directly connected to the bus with the instruction CPU, and the above-mentioned The CPU, RAM, and frame memory are connected to the CPU direct connection bus for data, and the CPU and the FIFO memory for data transmission and reception are connected to the high-speed bus.

In this image processing device, it is preferable that the above-mentioned compression/decompression circuit is directly connected to a data CPU by a connection bus.

(invention effect)

According to the present invention, since the image processing device connects the frame memory with a large amount of data to a bus with a relatively high processing capacity, and connects the FIFO memory for transmitting and receiving data with a small amount of data to a bus with a relatively low processing capacity, the CPU can be efficiently operated. In this way, the overall image processing speed can be realized.

Description of drawings

FIG. 1 is a block diagram of an image processing device according to a preferred embodiment of the present invention.

FIG. 2 is a block diagram of an image processing device according to another preferred embodiment of the present invention.

FIG. 3 is a block diagram of a conventional image processing device.

Explanation of symbols: 1, 5-image processing device; 2-electronic camera; 3-display panel; 4-host device; 10-high-speed bus; 12-peripheral bus; 13, 23-CPU; 16-frame memory; 17- Compression/decompression circuit; 18-FIFO memory for data transmission and reception; 20-register for frame memory; 21-register for compression/decompression circuit; 22-register for data transmission and reception; 24-instruction CPU directly connected to the bus; 25-data CPU Connect directly to the bus.

Detailed ways

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an image processing device according to a preferred embodiment of the present invention. This image processing device 1 adopts a bus structure in which a high-speed bus 10 operating at a high frequency of, for example, 75 MHz and a peripheral bus 12 operating at a frequency of, for example, 25 MHz are combined via a bus bridge 11, and various functional circuits are connected to the two buses. 10, 12 connections. That is, the following parts are connected to the high-speed bus 10: CPU13, which performs necessary calculation and control of image processing, etc.; ROM14, which stores the processing program of CPU13; and RAM15, which is used as a work area for the calculation performed by CPU13 etc., are also connected: a frame memory 16, which stores the image decompression data from the electronic camera 2 and the image decompression data after decompressing the image compression data from the host device 4, and displays the data on a display panel 3 such as an LCD; and A compression/decompression circuit 17 performs compression of image decompression data and decompression of image compression data. Furthermore, the following components are connected to the peripheral bus 12: a FIFO memory 18 for data transmission and reception, which transmits and receives image compressed data to and from the host device 4; and a general-purpose timer circuit 19, and the like. Furthermore, the image processing device 1 includes: a register 20 for frame memory, which is read/written by the CPU 13 to read/write the data of the frame memory 16; a register 21 for the compression/decompression circuit, which is read/written by the CPU 13 to read/write the data of the compression/decompression circuit 17; and The register 22 for data transmission and reception is used by the CPU 13 to read/write the data of the FIFO memory 18 for data transmission and reception. In addition, the compression/decompression circuit 17 is, specifically, a JPEG circuit used for compression/decompression of still images, an MPEG circuit used for compression/decompression of moving images, or the like. Note that, for example, when the image processing device 1 is used in an electronic device such as a mobile phone, the host device 4 is a processor device or the like that controls the main functions of the device.

The image decompression data from the electronic camera 2 is stored in the frame memory 16 and displayed on the display panel 3, and is read into the CPU 13 via the frame memory register 20 and the high-speed bus 10, and the compression/decompression circuit 17 and RAM15 etc. are compressed. The compressed image data is written into the FIFO memory 18 for data transmission and reception via the peripheral bus 12 and the register 22 for data transmission and reception, and is sequentially transmitted to the host device 4 . On the other hand, the FIFO memory 18 for data transmission and reception receives the compressed image data from the host device 4, and the compressed image data is sequentially read into the CPU 13 via the register 22 for transmission and reception of data and the peripheral bus 12, and is transmitted by the compression/decompression circuit 17 and the peripheral bus 12. RAM15 etc. are decompressed. The decompressed image data is stored in the frame memory 16 via the high-speed bus 10 and the frame memory register 20 and displayed on the display panel 3 .

Here, the high-speed bus 10 operates at a high frequency of, for example, 75 MHz, and image decompression data is read from the frame memory 16 to the CPU 13 at high speed and written from the CPU 13 to the frame memory 16 at high speed. Furthermore, since the frame memory 16 is connected to the same bus as the RAM 15 used as a work area for computation, it is possible to eliminate overhead time which is wasteful time due to bus switching in a series of computations. In this way, the CPU operates efficiently during the transmission of image decompression data with a large amount of data, which contributes to speeding up the overall image processing. Furthermore, since the data transfer between the CPU 13 and the compression/decompression circuit 17 is also via the high-speed bus 10, the overall image processing speed is further increased. On the other hand, since the peripheral bus 12 operates at a frequency of, for example, 25 MHz, writing of compressed image data to the FIFO memory 18 for data transmission and reception or reading to the CPU 13 is relatively slow. However, the image compression data is, for example, 1/10 or even 1/100 of the image decompression data, and the amount of data is relatively small, so the overall image processing speed does not drop much.

In this way, the image processing device 1 connects the frame memory 16 with a relatively large amount of data to the high-speed bus 10 with relatively high processing capability, and connects the FIFO memory 18 for transmitting and receiving data with a relatively small amount of data to the peripheral bus with relatively low processing capability. 12 connections, it is possible to make the CPU 13 work efficiently, and it is possible to realize high-speed image processing as a whole. In addition, the FIFO memory 18 for data transmission and reception is connected to the peripheral bus 12. This is because if there are too many functional circuits connected to the high-speed bus 10, the load capacity of the high-speed bus 10 will become larger, and the operable frequency corresponding to this will decrease. reason.

Furthermore, in this image processing device 1, the compression/decompression circuit 17 is connected to the high-speed bus 10, but in the case of using a compression/decompression circuit 17 with less reading/writing of the CPU 13, the compression/decompression circuit 17 may be The circuit 17 is connected to the peripheral bus 12 .

Next, an image processing device according to another preferred embodiment of the present invention will be described based on FIG. 2 . This image processing device 5 has adopted following bus structure, and this bus structure has: directly connect CPU23 and ROM14 instruction (instruction) directly connect bus 24 with CPU; high-speed bus 10. For example, the instructions of the processing system of the ARM system use the TCM (Tightly Coupled Memory) bus, the TCM bus and the AMBA (Advanced Microcontroller Bus Architecture) bus used for the data are respectively equivalent to the direct connection bus 24 for the CPU for the instruction, and the direct connection bus 25 for the CPU for the data. , High-speed bus 10. In addition, the aforementioned peripheral bus 12 (not shown) may be provided as needed.

The bus 25 is directly connected to the CPU for data, and the above-mentioned frame memory 16 and compression/decompression circuit 17 are also connected. Furthermore, the high-speed bus 10 is connected to the above-mentioned FIFO memory 18 for data transmission and reception, a timer circuit 19 and the like. Note that, like the image processing device 1 , the image processing device 5 includes the aforementioned frame memory register 20 , compression/decompression circuit register 21 , and data transmission and reception register 22 .

The CPU for instructions is directly connected to the bus 24 and the CPU for data is directly connected to the bus 25 , and the reading or writing operation is performed within, for example, one cycle of the basic operation clock of the CPU 23 . On the other hand, the high-speed bus 10 performs reading or writing operations in, for example, 5 to 10 cycles. Therefore, the image processing device 5 reads the decompressed image data from the frame memory 16 to the CPU 23 at a higher speed and writes the image decompression data from the CPU 23 to the frame memory 16 at a higher speed than the image processing device 1 .

In this way, in the image processing device 5, the frame memory 16 with a large amount of data is connected to the CPU direct connection bus 25 with a relatively high processing capacity, and the FIFO memory 18 for transmitting and receiving data with a small amount of data is connected to a relatively low processing capacity. Since the high-speed bus 10 is used, it is possible to further increase the speed of the overall image processing. In addition, the FIFO memory 18 for data transmission and reception is connected to the high-speed bus 10. This is because the frame memory 16 is moved to the CPU for data and directly connected to the bus 25, so the load capacity of the high-speed bus 10 does not increase so much.

In addition, in this image processing device 5, the compression/decompression circuit 17 is connected to the CPU direct connection bus 25 for data, but in the case of using the compression/decompression circuit 17 with less reading/writing of the CPU 23, the The compression/decompression circuit 17 is connected to the high-speed bus 10 .

As mentioned above, the image processing device according to the embodiment of the present invention has been described, but the present invention is not limited to the embodiment, and various design changes can be made within the range of matters described in the claims. . For example, if the electronic equipment using the image processing devices 1 and 5 does not have the electronic camera 2, the function of storing the image decompression data from the electronic camera 2 in the frame memory 16 may be omitted. The general-purpose timer circuit 19 may not be included, and of course other necessary functional circuits may also be included.

Claims (1)

1. An image processing device, wherein a high-speed bus and a peripheral bus are combined via a bus bridge, and the following components are connected to these high-speed buses and the peripheral bus: a CPU, which performs calculation and control of image processing; a FIFO memory for data transmission and reception, It transmits and receives image compressed data with a host device; a frame memory stores image decompressed data and displays the data on a display panel; and a compression/decompression circuit performs compression of image decompressed data and decompression of image compressed data. is that Connecting the CPU and the frame memory with a high-speed bus, connecting the FIFO memory for sending and receiving data with the peripheral bus, connecting the compression/decompression circuit with a high-speed bus, The processing capability of the high-speed bus is relatively high, and the processing capability of the peripheral bus is relatively low.

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