CN100514663C - Semiconductor memory element, phase change memory element and method of manufacturing the same - Google Patents

Abstract

A phase change memory element comprises a substrate, a lower electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer, a cup-shaped heating electrode, an upper electrode and a phase change material spacer. Wherein, the lower electrode is formed in the substrate. The first dielectric layer is located on the substrate and has a cup-shaped heating electrode therein, which is in contact with the lower electrode. The strip-shaped second dielectric layer and the strip-shaped third dielectric layer are respectively arranged on the substrate in different directions, wherein each second dielectric layer and each third dielectric layer cover partial area surrounded by the cup-shaped heating electrode, and the third dielectric layer is laminated on the second dielectric layer. The upper electrodes are located on the third dielectric layers, wherein each third dielectric layer and the upper electrode thereon form a stack structure. The phase change material spacer is located on the sidewall of the stack structure and is in physical and electrical contact with the cup-shaped heating electrode and the upper electrode.

Description

Semiconductor memory element, phase-change memory element and manufacturing method thereof

technical field

The present invention relates to a semiconductor storage element and a manufacturing method thereof, and in particular to a semiconductor storage element capable of obtaining a small heating area through a simple process, a phase change memory (phase change memory, PCM) and a manufacturing method thereof.

Background technique

With the vigorous development of portable products and the improvement of functional requirements, the current global memory market demand is rapidly expanding, and the rapid growth of non-volatile memory (non-volatile memory) is the most eye-catching. In order to adapt to this industry change, major manufacturers and research institutions around the world have already begun to develop next-generation memory technology like a fire. Among various possible technologies, phase-change memory elements and magnetoresistive random access memory (Magnetoresistive RAM, MRAM) are attracting more attention.

Phase-change memory is a non-volatile memory element that uses thermal effects to change the crystalline phase of phase-change materials to convert the resistance of the element. When the heating area through which the current flows is smaller, the heating current required to cause the phase change is smaller, and the RESET/SET driving current is also smaller. Correspondingly, this also corresponds to a smaller area of the driving transistor, that is, a smaller area of the memory unit cell (MemoryUnit Cell). Therefore, various researches have recently been designed on the size of the heating area. For example the European patent EP 1339111 of announcement in 2003 AD.

However, most of the currently known technologies involve etching contact holes in complex dielectric layers or sacrificial layers to reduce the heating area. Moreover, when the contact hole is only nanometer in size, the hole filling reliability and pass rate of the phase change film will be greatly reduced, and the dry pre-cleaning (Dry Pre-Cleaning) of the contact hole before coating becomes complicated and difficult to control.

Contents of the invention

The purpose of the present invention is to provide a phase-change memory element to easily achieve the purpose of reducing the heating area.

Another object of the present invention is to provide a method for manufacturing a phase change memory element, which can maintain its yield as the size of the element is reduced.

Another object of the present invention is to provide a method for manufacturing a phase-change memory element, which can simplify the process.

Another object of the present invention is to provide a semiconductor memory element suitable for use in non-volatile memory unit cells of micro to nanometer size.

The present invention proposes a phase-change memory element, which includes a substrate, multiple lower electrodes, a first dielectric layer, multiple cup-shaped heating electrodes, multiple layers of second and third dielectric layers, multiple upper electrodes, and multiple phase Variable material spacers. Wherein, the lower electrode is formed in the base, and the first dielectric layer is located on the base, and there are cup-shaped heating electrodes therein, and the bottom of each cup-shaped heating electrode is in contact with each lower electrode. The second dielectric layers are arranged on the base in the first direction, wherein each second dielectric layer covers a part of the area surrounded by the cup-shaped heating electrodes. The third dielectric layers are arranged on the base in the second direction, wherein each third dielectric layer covers a part of the area surrounded by the cup-shaped heating electrodes and is stacked on the second dielectric layer. The upper electrode is located on the third dielectric layer, wherein each third dielectric layer and the upper electrode on it form a stack structure. The phase change material spacer is located on the sidewall of the stack structure, and forms physical and electrical contact with the cup-shaped heating electrode and the upper electrode.

According to the phase change memory element described in a preferred embodiment of the present invention, the material of the cup-shaped heating electrode includes TiN, and the material of the upper electrode includes TiW.

According to the phase-change memory element described in a preferred embodiment of the present invention, when the width of the area surrounded by each cup-shaped heating electrode is 0.2 μm, the thickness of the phase-change material spacer can be between 20-50 nm (this value Depending on the maximum allowable overlay error (Overlay Error) of various photolithography steppers (Stepper), it basically follows that "half the thickness of the phase change material spacer plus the maximum allowable overlay error is equal to each cup half of the width of the area surrounded by the shaped heating electrode"). In addition, if the thickness of the phase-change material spacer is as large as 100 nm, the width of the area surrounded by each cup-shaped heating electrode will increase accordingly.

According to the phase change memory element described in a preferred embodiment of the present invention, the materials of the first dielectric layer and the third dielectric layer include oxide, and the material of the second dielectric layer includes nitride.

The present invention further proposes a method for manufacturing a phase-change memory element, which includes firstly providing a substrate on which a plurality of lower electrodes have been formed. Then, a first dielectric layer is provided on the substrate, and a plurality of cup-shaped heating electrodes are provided in the first dielectric layer, and the bottom of each cup-shaped heating electrode is in contact with each lower electrode. Afterwards, multiple layers of second dielectric layers are formed on the substrate, and each layer of second dielectric layers covers a partial area surrounded by each cup-shaped heating electrode along the first direction. Then, a plurality of stacked structures are formed on the substrate, and each stacked structure covers a part of the area surrounded by each cup-shaped heating electrode in the second direction, wherein the stacked structure is composed of a third dielectric layer and an upper electrode constituted. Next, a phase-change material (PC) film is formed on the substrate to cover the above-mentioned stack structure and the second dielectric layer, and then anisotropically etched this layer of phase-change material film to form a phase-change material gap on the sidewall of the stack structure wall, and each phase change material spacer wall will make physical and electrical contact with each cup-shaped heating electrode and upper electrode. Afterwards, over-etching the phase-change material spacer to remove the phase-change material film on the sidewall of the second dielectric layer.

According to the method for manufacturing a phase-change memory device according to an embodiment of the present invention, the time for over-etching the phase-change material spacer is a time corresponding to the thickness of the phase-change material spacer.

The present invention also proposes a method for manufacturing a phase-change memory element, which includes firstly providing a substrate on which a plurality of lower electrodes have been formed. Then, a first dielectric layer is provided on the substrate, and a plurality of cup-shaped heating electrodes are provided in the first dielectric layer, and the bottom of each cup-shaped heating electrode is in contact with each lower electrode. Afterwards, multiple layers of second dielectric layers are formed on the substrate, and each layer of second dielectric layers covers a partial area surrounded by each cup-shaped heating electrode along the first direction. Then, the edges of each second dielectric layer are rounded, and then a plurality of stacked structures are formed on the substrate, and each stacked structure covers a part of the area surrounded by each cup-shaped heating electrode in the second direction, wherein The stack structure is composed of a third dielectric layer and an upper electrode. Next, a phase-change material (PC) film is formed on the substrate to cover the above-mentioned stack structure and the second dielectric layer, and then anisotropically etched this layer of phase-change material film to form a phase-change material gap on the sidewall of the stack structure wall, and each phase change material spacer wall will make physical and electrical contact with each cup-shaped heating electrode and upper electrode.

According to the method for manufacturing a phase-change memory element described in another embodiment of the present invention, the method for rounding the corners of the second dielectric layer includes using Inductively Coupled Plasma-Argon (Inductively Coupled Plasma-Ar, ICP-Ar) ) cleaning step or an isotropic (partial or complete) dry etch process or even a wet etch process can be achieved.

In all the above-mentioned methods of the present invention, the step of forming the second dielectric layer is, for example, firstly forming a nitride film on the substrate, and then performing photolithography and etching processes to form the above-mentioned second dielectric layer in the first direction.

In all the above-mentioned methods of the present invention, the step of forming the stack structure is, for example, firstly forming the third dielectric layer and the upper electrode sequentially on the substrate, and then performing photolithography and etching processes to form the stack structure in the second direction.

In all the above-mentioned methods of the present invention, the step of providing the first dielectric layer on the substrate, for example, firstly provides the first oxide layer with a plurality of openings on the substrate, and each opening exposes each lower electrode, and then forms a dielectric layer on the substrate. The heating electrode material covers the first oxide layer, the inner surface of the opening and the lower electrode. Next, fill the opening with the second oxide layer, and planarize the second oxide layer to remove the second oxide layer and heating electrode material outside the opening.

The present invention further proposes a semiconductor storage element, comprising a substrate, a plurality of lower electrodes, a first, a second and a third dielectric layer, a plurality of cup electrodes, a plurality of upper electrodes, a conductor material spacer and a non-volatile memory unit cell. Wherein, the lower electrodes are formed in the base, the first dielectric layer is located on the base, and the cup-shaped electrodes are located in the first dielectric layer, and the bottom of each electrode is in contact with each lower electrode. The second dielectric layer is arranged on the base in the first direction, wherein each layer of the second dielectric layer covers a part of the area surrounded by each cup-shaped electrode. The third dielectric layer is arranged on the base in the second direction, wherein each layer of the third dielectric layer covers a part of the area surrounded by each cup-shaped electrode and is stacked on the second dielectric layer. The upper electrode is located on the third dielectric layer, wherein each layer of the third dielectric layer and each upper electrode on it form a stack structure, and the conductive material spacer is located on the side wall of the stack structure, and is connected with the cup-shaped electrode and the upper electrode. The electrodes make physical and electrical contact. Furthermore, the non-volatile memory unit cells are embedded between each conductive material spacer and each cup-shaped electrode.

According to the semiconductor storage element described in another embodiment of the present invention, the material of the above-mentioned cup electrode comprises TiW, TiN, Al, Cu/TaN or various metal silicides (Metal Silicide), and the material of the conductor material spacer comprises TiW , TiN, Al, Cu/TaN or various metal silicides (MetalSilicide).

According to another embodiment of the present invention, in the semiconductor memory device, materials of the first and third dielectric layers include oxide, and materials of the second dielectric layer include nitride.

According to the semiconductor storage element described in another embodiment of the present invention, the above-mentioned non-volatile memory unit cell may be a single magnetic tunnel junction (magnetic tunnel junction, MTJ) unit cell of a magnetoresistive random access memory (MRAM), Mask-type read-only memory unit (Mask ROM), programmable read-only memory (programmable ROM, PROM) anti-fuse type (Anti-Fuse) unit cell, non-volatile resistance memory (Resistance RAM, RRAM) unit crystal cell or other 3D non-volatile memory (3D-NVM) unit cell.

Because the present invention utilizes the phase-change material spacer as the contact hole structure of the heating electrode, the contact area between the phase-change material and the heating electrode in the phase-change memory element can be made smaller than the area produced by photolithography, so it has a relatively "Surface contact structure" smaller contact area. Furthermore, the process of the present invention is significantly simplified compared to known techniques. At the same time, the structure of the present invention does not need to consider the current flow problem caused by the misalignment of the general phase change material and the contact hole of the upper electrode. Moreover, in the process of defining the contact area between the phase-change material spacer and the heating electrode, the present invention will not have the well-known hole that is too small to fill the bottom or the junction of the top of the sidewall film on both sides (metal or phase-change material) When the film fills the hole (the film fills the hole), the gap (Seam) that cannot be filled appears. In addition, when the planarization process of the phase change material film is successfully developed, the cross spacer structure of the present invention is not limited to the application of phase change memory, but can be used in the structure of 3D non-volatile memory (3D-NVM).

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

1A to 1G are schematic diagrams of the manufacturing process of a phase-change memory device according to a preferred embodiment of the present invention.

2A to 2E are schematic diagrams of the manufacturing process of a phase-change memory device according to a preferred embodiment of the present invention.

Description of main component marking

100: base

102: Lower electrode

104: opening

106, 110: oxide layer

108: Cup heating electrode

112: first dielectric layer

114: second dielectric layer

114a: Rounded second dielectric layer

116: Stack structure

118: The third dielectric layer

120: Upper electrode

122: Phase change material (PC) film

122a: phase change material spacer

124: contact hole

200: Corner

d: distance

r: aperture

Detailed ways

1A to 1G are schematic diagrams of the manufacturing process of a phase-change memory device according to a preferred embodiment of the present invention.

Please refer to FIG. 1A , where part (1) is a top view of the component, and part (2) is a cross-sectional view of line II-II of part (1). In the method of this embodiment, a substrate 100 is provided first, in which a plurality of bottom electrodes 102 have been formed. Then, the first dielectric layer 112 can be provided on the substrate, for example, the first oxide layer 106 having a plurality of openings 104 is provided on the substrate 100 , and each opening 104 exposes each lower electrode 102 . The diameter r of each opening 104 is related to the thickness of the subsequently formed phase change material spacer, which will be described in detail later.

Then, please refer to FIG. 1B , where part (1) is a top view of the component, and part (2) is a cross-sectional view of line II-II of part (1). A heating electrode material is formed on the substrate 100 to cover the first oxide layer 106 , the inner surface of the opening 104 and the lower electrode 102 , and then the second oxide layer 110 is filled in the opening 104 . Afterwards, the aforementioned second oxide layer 110 is planarized to remove the second oxide layer 110 and heating electrode material outside the opening 104 . And the remaining heating electrode material is cup-shaped heating electrode (cup-shaped heat electrode) 108, and its material is such as TiN, thickness then can be less than 20nm, and the bottom of each cup-shaped heating electrode 108 contacts with each lower electrode 102 . Wherein, the first oxide layer 106 and the second oxide layer 110 are the first dielectric layer 112 mentioned above, and the first dielectric layer 112 is not limited to the oxide layer, and other suitable dielectric materials can also be used.

Afterwards, please refer to Figure 1C, where part (1) is a top view of the component, and part (2) is a cross-sectional view of the II-II line segment of part (1), and part (3) is part (1) Sectional view of line III-III. A plurality of second dielectric layers 114 are formed on the substrate 100, and each second dielectric layer 114 covers a part of the area surrounded by each cup-shaped heating electrode 108 in the first direction, wherein the second dielectric layer 114 The thickness is, for example, 60 nm. The step of forming the second dielectric layer 114 is, for example, to form a nitride film on the substrate 100 first, and then perform a photolithography and etching process to form the second dielectric layer 114 in the first direction.

Then, please refer to FIG. 1D , where part (1) is a top view of the component, and part (2) is a cross-sectional view of line II-II of part (1). A plurality of stacked structures 116 are formed on the substrate 100, and each stacked structure 116 covers a part of the area surrounded by each cup-shaped heating electrode 108 in the second direction; A distance d is reserved to avoid an increase in the contact area between the subsequently formed phase change material spacer and the cup-shaped heating electrode 108 . In addition, the above-mentioned first direction and the second direction are different directions, for example, they are perpendicular to each other in this figure. The step of forming the stack structure 116 is, for example, firstly forming a layer of third dielectric layer 118 and an upper electrode 120 on the substrate 100, and then performing another photolithography and etching process, wherein the material of the upper electrode 120 is, for example, TiW or other A suitable conductive material, and the thickness of the third dielectric layer 118 is, for example, 100 nm and the thickness of the upper electrode 120 is, for example, 100 nm. In an example, the photolithography mask for forming the stack structure 116 and the second dielectric layer 114 may be the same if allowed by the photolithography mask design and the setting of the stepper.

Next, please refer to FIG. 1E , where part (1) is a top view of the device, and part (2) is a cross-sectional view of line II-II of part (1). A phase change material (PC) thin film 122 is formed on the substrate 100 to cover the stack structure 116 and the second dielectric layer 114 .

Then, please refer to Figure 1F, where part (1) is a top view of the component, and part (2) is a cross-sectional view of the II-II line segment of part (1), and part (3) is part (1) Sectional view of line III-III. Anisotropic etching of the phase-change material thin film 122 (see FIG. 1E ) to form phase-change material spacers 122a on the sidewalls of the stack structure 116, and each phase-change material spacer 122a will be in contact with each cup-shaped heating electrode 108 (such as shown in part (1)). However, since the second dielectric layer 114 has vertical sidewalls, there are also phase change material spacers 122a on the sidewalls of the second dielectric layer 114 (as shown in part (3)).

Therefore, please refer to Figure 1G, where part (1) is a top view of the component, and part (2), part (3) and part (4) are the line segment II-II and III of part (1) respectively. Sectional view of line III and line IV-IV. Afterwards, the phase change material spacer 122 a is over-etched to remove the phase change material film on the sidewall of the second dielectric layer 114 . The time for over-etching the phase-change material spacer 122 a is, for example, the time corresponding to the thickness of the phase-change material spacer 122 a or longer. When the aperture r of each opening 104 (see FIG. 1A ) is 0.2 μm, the thickness of the phase change material spacer 122a can be between 20-50nm (this value depends on various photolithography steppers (Stepper ) depends on the maximum allowable overlay error (Overlay Error), which basically follows the principle of "half the thickness of the phase change material spacer plus the maximum allowable overlay error is equal to half the width of the area surrounded by each cup-shaped heating electrode" in principle). In addition, if the thickness of the phase change material spacer 122a is as large as 100 nm, the pore size r can be increased accordingly.

It can be observed from FIG. 1G that the phase-change memory element of the present invention uses a phase-change material spacer 122a as the contact hole 124 of the entire element. Therefore, in the element of the present invention, the contact area between the phase change material (ie, 122a) and the heating electrode (ie, 108) is smaller than that produced by photolithography, and has a smaller surface area than the "surface contact structure". The contact area, so it has the ability to achieve the minimum contact area.

2A to 2E are schematic diagrams of the manufacturing process of a phase-change memory device according to another preferred embodiment of the present invention, wherein components identical or similar to those in the previous embodiment are also labeled with the elements in FIGS. 1A to 1G .

Please refer to FIG. 2A , where part (1) is a top view of the component, and part (2) is a cross-sectional view of line II-II of part (1). In this figure, the steps in FIG. 1A to FIG. 1B are the same, and the substrate 100 is firstly provided, in which the lower electrode 102 has been formed. Then, a first dielectric layer 112 with cup-shaped heating electrodes 108 is provided on the substrate 100 , and the bottom of each cup-shaped heating electrode 108 is in contact with each lower electrode 102 .

Then, please refer to FIG. 2B , where part (1) is a top view of the component, and part (2) is a cross-sectional view of line II-II of part (1). Multiple layers of second dielectric layers 114 are formed on the substrate 100 , and each layer of second dielectric layer 114 covers a partial area surrounded by each cup-shaped heating electrode 108 in a first direction.

Then, please refer to FIG. 2C , which is a cross-sectional view of the subsequent process of the line segment III-III in part (1) of FIG. 2B . Edges 200 of each second dielectric layer 114 (see FIG. 2B ) are rounded to form a rounded second dielectric layer 114a. The rounding method mentioned above, for example, utilizes an inductively coupled plasma-argon (Inductively Coupled Plasma-Ar, ICP-Ar) cleaning step or an isotropic (partial or complete) dry etching process or even Wet etching process and the like can be achieved.

Next, please refer to Figure 2D, where part (1) is a top view of the component, and part (2), part (3) and part (4) are the II-II line segment and III of part (1) respectively. Sectional view of line III and line IV-IV. A plurality of stacked structures 116 are formed on the substrate 100, and each stacked structure 116 covers a part of the area surrounded by each cup-shaped heating electrode 108 in the second direction, wherein the stacked structure 116 is formed by the third dielectric layer 118 and the upper electrode 120 constituted. Such a stacked structure of the third dielectric layer and the upper electrode requires only one photolithography process, and at the same time, the two have self-aligned line widths and side walls. Next, a phase change material (PC) thin film 122 is formed on the substrate 100 to cover the stacked structure 116 and the rounded second dielectric layer 114a.

Again, please refer to Figure 2E, where part (1) is a top view of the component, and part (2), part (3) and part (4) are the line segment II-II and III of part (1) respectively. Sectional view of line III and line IV-IV. Perform anisotropic etching on the phase-change material film 122 (see FIG. 2D ) to form phase-change material spacers 122a on the sidewalls of the stack structure 116, and each phase-change material spacer 122a will be in contact with each cup-shaped heating electrode 108 . Moreover, because of the shape of the corner 200 of the rounded second dielectric layer 114a, no phase change material spacer 122a is formed on the sidewall of the second dielectric layer 114a.

In addition, the present invention can also be applied to other semiconductor storage elements, and taking FIG. 2E of the above-mentioned embodiment as an example, when the material of the spacer 122a is changed to a conductive material, the conductive material spacer and each cup-shaped electrode can be A non-volatile memory unit cell is embedded between them. For example, the material of the above-mentioned cup-shaped electrode is TiW, TiN, Al, Cu/TaN or various metal silicides, and the material of the conductor material spacer can also be TiW, TiN, Al, Cu/TaN or each A metal silicide (Metal Silicide). The so-called non-volatile memory unit cell can be a single magnetic tunnel junction (magnetic tunnel junction, MTJ) unit cell of a magnetoresistive random access memory (MRAM), a masked read-only memory unit (Mask ROM), Anti-fuse cell of programmable read-only memory (programmableROM, PROM), unit cell of non-volatile resistance memory (ResistanceRAM, RRAM) or other 3D non-volatile memory (3D-NVM) unit cell. In addition, the material of the above-mentioned first and third dielectric layers may be oxide, and the material of the second dielectric layer may be nitride.

In summary, the features of the present invention are:

1. In the structure of the present invention, the contact area between the phase-change material spacer and the cup-shaped heating electrode is smaller than the area produced by photolithography, and is controlled by the crossing area of the thickness of the two, which has a ratio of "surface contact structure" "Smaller contact area.

2. The process of the present invention is much simpler than known techniques.

3. The present invention utilizes phase-change material spacer etching to define the contact area with the cup-shaped heating electrode, so when the etching is completed, not only the contact with the upper electrode is completed, but also the contact hole structure of the present invention is defined. Therefore, the present invention does not need to consider the current flow problem caused by the misalignment of the general phase change material and the contact hole of the upper electrode.

4. The structure of the present invention is a single contact hole.

5. The process of the present invention does not require the phase-change material coating to be filled into the nanometer-sized contact hole at all, so there will be no hole that is too small to fill the bottom or the top of the sidewall film on both sides to be jointed (shrinking) will not be filled. The problem of the gap (Seam).

6. If the planarization process of the phase change material film is successful in the future, the structure of the present invention will be used in 3D-NVM.

7. The cross spacer structure of the present invention is not limited to the application of the phase change memory. For example, the spacer part of the phase change material is changed to TiN material like the bottom electrode, and then the two crossed TiN intersections are inserted into other possible non-volatile memory unit cells (Unit Cell), which is as small as nanometers. The physical and electrical contact between the non-volatile memory cell unit cell and the upper and lower electrodes will be easier to achieve than the general contact hole type memory cell and the upper and lower electrodes. This is easy to understand from the problem of lithography overlay error (Overlay Error). The non-volatile memory unit cells described here are MTJ of MRAM, Anti-Fuse of Mask ROM or PROM, and unit cells of RRAM, etc. Other non-volatile memory unit cells not mentioned can also be used.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (19)

1. A phase-change memory element, characterized in that it comprises: base; a plurality of lower electrodes formed in the substrate; a first dielectric layer on the substrate; A plurality of cup-shaped heating electrodes are located in the first dielectric layer, and the bottom of each cup-shaped heating electrode is in contact with each of the lower electrodes; a plurality of second dielectric layers arranged on the substrate in a first direction, wherein each of the second dielectric layers covers a partial area surrounded by each of the cup-shaped heating electrodes; A multi-layer third dielectric layer is arranged on the substrate in a second direction, wherein each of the third dielectric layers covers a part of the area surrounded by each of the cup-shaped heating electrodes and is stacked on the above-mentioned second dielectric layers; a plurality of upper electrodes located on the above third dielectric layers, wherein each of the third dielectric layers and each of the upper electrodes thereon form a stack structure; and A plurality of phase-change material spacers are located on the sidewalls of the stacked structure, and are in physical and electrical contact with the cup-shaped heating electrodes and the upper electrodes. 2. The phase-change memory element according to claim 1, wherein the materials of the cup-shaped heating electrodes include TiN, TaN, W or metal silicide. 3. The phase change memory element according to claim 1, wherein the materials of the upper electrodes include TiW, TiN, Al, Cu/TaN or metal silicide. 4. The phase-change memory device according to claim 1, wherein materials of the first dielectric layer and the third dielectric layer include oxide, and materials of the second dielectric layer include nitride. 5. A method for manufacturing a phase-change memory element, characterized in that it comprises: providing a substrate having formed with a plurality of bottom electrodes; providing a first dielectric layer on the substrate, the first dielectric layer has a plurality of cup-shaped heating electrodes, and the bottom of each cup-shaped heating electrode is in contact with each of the lower electrodes; forming multiple layers of second dielectric layers on the substrate, each of the second dielectric layers covering a partial area surrounded by each of the cup-shaped heating electrodes in the first direction; forming a plurality of stacked structures on the substrate, each of the stacked structures covering a part of the area surrounded by each of the cup-shaped heating electrodes in the second direction, wherein each of the stacked structures is composed of a third dielectric layer and an upper electrode; forming a thin film of phase-change material on the substrate, covering the above-mentioned stacked structures and the above-mentioned second dielectric layers; Anisotropically etching the phase-change material film to form a plurality of phase-change material spacers on the sidewalls of the above-mentioned stacked structures, and each of the phase-change material spacers forms physical and electrical contact with each of the cup-shaped heating electrodes and the upper electrode; as well as Over-etching the phase-change material spacers to remove the phase-change material thin films on the sidewalls of the second dielectric layer. 6. The method of manufacturing a phase-change memory element according to claim 5, wherein the step of forming the above-mentioned second dielectric layers on the substrate comprises: forming a nitride film on the substrate; and Perform photolithography and etching processes to form the above-mentioned second dielectric layers in the first direction. 7. The method for manufacturing a phase-change memory element according to claim 5, wherein the step of forming the above-mentioned stacked structures on the substrate comprises: sequentially forming the third dielectric layer and the upper electrode on the substrate; and Perform photolithography and etching processes to form the above stacked structures in the second direction. 8. The method for manufacturing a phase-change memory element according to claim 5, wherein the time for over-etching the phase-change material spacers is the time corresponding to the thickness of each phase-change material spacer. 9. The method of manufacturing a phase-change memory element according to claim 5, wherein the step of providing the first dielectric layer on the substrate comprises: providing a first oxide layer on the substrate, the first oxide layer has a plurality of openings, each of which exposes each of the lower electrodes; forming a heating electrode material on the substrate to cover the first oxide layer, the inner surfaces of the above-mentioned openings and the above-mentioned lower electrodes; filling the openings with a second oxide layer; and planarizing the second oxide layer to remove the second oxide layer and the heating electrode material outside the openings. 10. A method for manufacturing a phase-change memory element, characterized by comprising: providing a substrate having formed with a plurality of lower electrodes; providing a first dielectric layer on the substrate, the first dielectric layer has a plurality of cup-shaped heating electrodes, and the bottom of each cup-shaped heating electrode is in contact with each of the lower electrodes; forming multiple layers of second dielectric layers on the substrate, each of the second dielectric layers covering a partial area surrounded by each of the cup-shaped heating electrodes in the first direction; rounding corners of each of the second dielectric layers; forming a plurality of stacked structures on the substrate, each of the stacked structures covering a part of the area surrounded by each of the cup-shaped heating electrodes in the second direction, wherein each of the stacked structures is composed of a third dielectric layer and an upper electrode; forming a thin film of phase change material on the substrate, covering the above-mentioned stacked structures and the above-mentioned second dielectric layers; and Anisotropically etching the phase-change material film to form a plurality of phase-change material spacers on the sidewalls of the above-mentioned stacked structures, and each phase-change material spacer forms physical and electrical contact with each of the cup-shaped heating electrodes and the upper electrodes. 11. The method for manufacturing a phase-change memory element according to claim 10, wherein the method for rounding the corners of each of the second dielectric layers comprises using an inductively coupled plasma-argon gas cleaning step, an isotropic dry type etching process or wet etching process. 12. The method for manufacturing a phase-change memory element according to claim 10, wherein the step of forming the above-mentioned second dielectric layers on the substrate comprises: forming a nitride film on the substrate; and Perform photolithography and etching processes to form the above-mentioned second dielectric layers in the first direction. 13. The method of manufacturing a phase-change memory element according to claim 10, wherein the step of forming the above-mentioned stacked structures on the substrate comprises: sequentially forming a third dielectric layer and an upper electrode on the substrate; and Perform photolithography and etching processes to form the above stacked structures in the second direction. 14. The method of manufacturing a phase-change memory element according to claim 10, wherein the step of providing the first dielectric layer on the substrate comprises: forming a first oxide layer on the substrate, the first oxide layer has a plurality of openings, each of which exposes each of the lower electrodes; forming a heating electrode material on the substrate to cover the first oxide layer, the inner surfaces of the above-mentioned openings and the above-mentioned lower electrodes; filling the openings with a second oxide layer; and planarizing the second oxide layer to remove the second oxide layer and the heating electrode material outside the openings. 15. A semiconductor memory element, characterized by comprising: base; a plurality of lower electrodes formed in the substrate; a first dielectric layer on the substrate; a plurality of cup-shaped electrodes located in the first dielectric layer, and the bottom of each of the electrodes is in contact with each of the lower electrodes; a plurality of second dielectric layers arranged on the substrate in a first direction, wherein each of the second dielectric layers covers a partial area surrounded by each of the cup-shaped electrodes; A multi-layer third dielectric layer is arranged on the substrate in a second direction, wherein each third dielectric layer covers a partial area surrounded by each cup-shaped electrode and is stacked on the above-mentioned second dielectric layers; a plurality of upper electrodes located on the above third dielectric layers, wherein each of the third dielectric layers and each of the upper electrodes thereon form a stack structure; a plurality of conductive material spacers, located on the sidewalls of the stack structure, and forming physical and electrical contact with the above-mentioned cup electrodes and the upper electrode; and The non-volatile storage unit cell is embedded between each of the conductor material spacers and each of the cup-shaped electrodes. 16. The semiconductor memory device according to claim 15, wherein the materials of the cup-shaped electrodes include TiW, TiN, Al, Cu/TaN or metal silicide. 17. The semiconductor memory device according to claim 15, wherein the materials of the conductive material spacers include TiW, TiN, Al, Cu/TaN or metal silicide. 18. The semiconductor memory device according to claim 15, wherein the material of the first dielectric layer and the third dielectric layer comprises oxide, and the material of the second dielectric layer comprises nitride. 19. The semiconductor storage element according to claim 15, wherein the non-volatile memory unit cell comprises a single magnetic tunnel junction unit cell of a magnetoresistive random access memory, a mask type read-only memory unit, a Program the antifuse type unit cell of the read-only memory or the unit unit cell of the non-volatile resistance memory.

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