CN100514271C - chip set, north bridge chip and disk data access method - Google Patents

Abstract

A chip set for accessing data of redundant disk array is connected between CPU, system memory and disk array. The north bridge chip is connected between the central processing unit and the system memory, and comprises a disk array accelerator for executing the function of disk array data access. The south bridge chip is connected between the north bridge chip and the disk array and used for accessing data of the disk array.

Description

Chip set, north bridge chip and disk data access method

technical field

The present invention relates to a computer system, and in particular to a redundant disk array computer system.

Background technique

In order to provide greater capacity, higher read and write performance, or security, modern computer systems usually support the function of Redundant Array of Independent Disks (RAID). To put it simply, RAID is to use several disks as an array to form a disk group, and cooperate with the design of data scattered arrangement to improve data security. When storing data at the same time, the data can be divided into many sections and stored in each disk separately. Therefore, the performance of the entire computer system can be improved by using each disk to provide data bonus effects. In addition, RAID can also use parity check (parity check), so that when any disk in the array is damaged, data can still be read.

FIG. 1 shows a schematic diagram of a computer system 100 with a redundant disk array. The computer system 100 includes a disk array 130 , a south bridge chip 108 , a north bridge chip 104 , a system memory 106 and a CPU 102 .

In FIG. 1 , it is assumed that the disk array 130 is composed of three disks, including disks 132 , 134 and 136 . The south bridge chip 108 includes a disk controller 110 for controlling the storage of the disks 132 , 134 and 136 respectively. The north bridge chip 104 is coupled between the south bridge chip 108 , the system memory 106 and the CPU 102 .

The disk controller 110 shown in FIG. 1 can be an Integrated Driver Electronics (Integrated Driver Electronics, IDE) or an Advanced Host Controller (Advanced Host Controller, AHC). The system memory 106 can be a dynamic random access memory (Dynamic Random Access Memory, DRAM).

FIG. 2 is a flow chart showing an example of writing RAID data by the computer system 100 . First, the central processing unit 102 will first write the data D1 into the system memory 106 (step S201), and then the disk controller 110 reads another data D2 from the disk 134, and writes the data D2 into the system memory 106 (step S201). S202), after that, the central processing unit 102 reads the data D2 from the system memory 106 (step S203), and then the central processing unit 102 performs an exclusive OR (XOR) operation on the data D1 and D2 to obtain the parity data DP (step S204 ), then the central processing unit 102 writes the parity data DP in the system memory 106 (step S205), and finally the disk controller 110 makes the data D1 write in the disk 132 (step S206), and then the disk controller 110 makes the parity data DP Write to the disk 136 (step S207).

As in the above example, it can be found that the CPU 106 has to handle almost all the steps, which will cause the overall performance of the computer system to deteriorate.

Contents of the invention

The present invention provides a chip set for redundant disk array data access, the chip set is connected between a central processing unit, a system memory and a disk array, the chip set includes: a disk array accelerator, according to the disk array The control command is used to execute the function of accessing the first data and the second data stored in the system memory, and performing logical operations on the first data and the second data to obtain parity data; the north bridge chip buffer, which includes a memory The image temporary storage area is used to store the disk controller control command; and the image temporary storage area is used to store the disk array control command, and; and the south bridge chip is connected between the north bridge chip and the disk array for access The data of the disk array includes: a disk controller, used to control the data access of the disk array, and a south bridge chip register, used to store the disk array control command.

Furthermore, the present invention provides a Northbridge chip for redundant disk array data access, the Northbridge chip is connected between a central processing unit and a system memory, and the Northbridge chip is connected to a disk array through a Southbridge chip , the north bridge chip includes: a disk array accelerator, which is used to perform access to the first data and the second data stored in the system memory according to the disk array control command, and perform logical operations on the first data and the second data to The function of obtaining parity data; and a Northbridge chip register, including the Northbridge chip register, which includes a memory image temporary storage area, used to store disk controller control commands; and an image temporary storage area, used to store the disk array control commands.

Furthermore, the present invention provides a disk array data access method, including: mapping a disk array control command to a north bridge chip register; a disk array accelerator accessing and storing in the system memory according to the disk array control command a first data and a second data; and the disk array accelerator performs logic operations on the first data and the second data according to the disk array control command to obtain a third data, and writes the third data the system memory.

Description of drawings

FIG. 1 is a schematic diagram showing a computer system supporting RAID.

FIG. 2 is a flow chart showing a process for performing RAID data writing.

FIG. 3 is a schematic diagram showing a computer system supporting RAID of the present invention.

FIG. 4 is a flow chart showing the implementation of RAID data writing according to the present invention.

FIG. 5 is a schematic diagram showing another computer system supporting RAID of the present invention.

FIG. 6 is a flow chart showing another implementation of RAID data writing in the present invention.

FIG. 7 is a flow chart showing the implementation of RAID data reading according to the present invention.

Explanation of main component symbols

100, 300, 500～computer system

102, 302, 502～central processing unit

104, 304, 504～Northbridge chip

106, 306, 506 ~ system memory

108, 308, 508～South Bridge chip

110, 310, 510～disk controller

130, 330, 530～disk array

350, 550～disk array accelerator

132, 134, 136, 332, 334, 336, 532, 534, 536～disk

512～South bridge chip buffer

560～North bridge chip buffer

562～memory image temporary storage area

564～Image Temporary Storage Area

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

FIG. 3 is a schematic diagram showing a computer system 300 of the present invention. The computer system 300 includes: a disk array 330 , a south bridge chip 308 , a north bridge chip 304 , a system memory 306 and a CPU 302 .

In FIG. 3 , it is assumed that the disk array 330 is composed of three disks, including disks 332 , 334 and 336 . The south bridge chip 308 includes a disk controller 310 for controlling the storage of the disks 332 , 334 and 336 , and a disk array accelerator (RAIDA) 350 for performing the functions of the disk array. The north bridge chip 304 is coupled between the south bridge chip 308 , the system memory 306 and the CPU 302 .

FIG. 4 is a flow chart showing an example of computer system 300 executing RAID data writing. First, the central processing unit 302 will first write the data D1 into the system memory 306 (step S401), and then the disk controller 310 reads another data D2 from the disk 334 and writes the data D2 to the system memory 306 via the North Bridge chip 304 in (step S402). Afterwards, the disk array accelerator 350 reads the data D1 and D2 from the system memory 106 via the north bridge chip 304 (step S403), and then the disk array accelerator 350 performs an exclusive OR (XOR) operation on the data D1 and D2 to obtain the parity data DP( Step S404), then the disk array accelerator 350 writes the parity data DP into the system memory 306 via the north bridge chip 304 (step S405), and finally the disk controller 310 makes the parity data DP write into the disk 336 from the system memory 306 (step S406) , and then the disk controller 310 enables the data D1 to be written from the system memory 306 to the disk 332 (step S407).

From the above, it can be known that embedding a disk array accelerator in the south bridge chip 308 can reduce the load of the CPU 302 and improve the performance of the computer system 300 . However, since data is continuously transmitted through the bus between the north bridge chip 304 and the south bridge chip 306, the bandwidth of the bus is also occupied.

FIG. 5 is a schematic diagram of another computer system 500 of the present invention. The computer system 500 includes: a disk array 530 , a chipset 570 , a system memory 506 and a CPU 502 .

In FIG. 5 , chipset 570 includes north bridge chip 504 and south bridge chip 508 . Assume that the disk array 530 is composed of three disks, including disks 532 , 534 and 536 . The south bridge chip 508 includes: a disk controller 510 for controlling the storage of the disks 532 , 534 and 536 ; and a south bridge chip register 512 for temporarily storing related control commands of the disk array accelerator 550 . The north bridge chip 504 is coupled between the south bridge chip 508 , the system memory 506 and the CPU 502 . In this embodiment, a disk array accelerator (RAIDA) 550 is disposed in the north bridge chip 504 for performing the function of a disk array (RAIDA). In addition, the north bridge chip 504 also includes a north bridge chip register 560 for temporarily storing related control commands.

In Fig. 3 of the present invention, because the disk array accelerator 350 is located in the south bridge chip 308, so the disk array accelerator 350 can easily execute RAID according to the setting stored in the relevant control command in the south bridge chip register (not shown). function.

And in Fig. 5 of the present invention, because the disk array accelerator 550 is placed in the north bridge chip 504, so before executing the RAID function, the relevant control commands of the disk array accelerator 550 must be copied to the north bridge chip cache memory 560 by the south bridge chip register 512, It can be provided to the disk array accelerator 550 for use.

In order to copy the relevant control commands to the north bridge chip register 560, the north bridge chip 504 will peep (snoop) the memory image temporary storage area 562 storing the relevant control commands about the disk controller 510 in the north bridge chip register 560, when the operating system or other external When the instruction executes the write operation to the memory image temporary storage area 562, the north bridge chip 504 will store the disk array control command image (mapping) about the disk array accelerator 550 in the south bridge chip register 512 to the image temporary storage area 560 of the north bridge chip In the shadow register 564. The image temporary storage area 564 can be a specific area in the north bridge chip temporary storage area 560, for example, an area that can use a memory map output input cycle (MMIO cycle).

In order to describe the present invention more specifically, please refer to FIG. 6 , which shows a flowchart 600 of an example of writing RAID data by the computer system 500 .

First, the central processing unit 502 will first write the data D1 into the system memory 506 (step S601), and then the disk controller 510 reads another data D2 from the disk 534 and writes the data D2 to the system memory 506 via the north bridge chip 504 in (step S602). Next, the north bridge chip 504 peeps the memory image temporary storage area 562 (step S603 ). If the operating system or other external instructions execute the write operation to the memory image temporary storage area 562, the north bridge chip 504 will store the disk array control command mapping (mapping) about the disk array accelerator 550 in the south bridge chip register 512 to the north bridge chip in the shadow register 564 of the buffer 560 (step S604). Afterwards, the disk array accelerator 550 reads the data D1 and D2 from the system memory 506 according to the disk array control command of the image temporary storage area 564 (step S605), and then the disk array accelerator 550 performs exclusive-or (Exclusive- OR XOR) operation to obtain parity data DP (step S606), then disk array accelerator 550 writes parity data DP in system memory 506 (step S607), and finally disk controller 510 makes data D1 and parity data DP from system memory 506 are respectively written to the disk 532 and the disk 536 (step S608).

FIG. 7 is a flow chart 700 of an example of reading RAID data performed by the computer system 500 according to another embodiment of the present invention.

Firstly, the disk controller 510 stores the data D1 stored in the disk 532 into the system memory 506 via the south bridge chip 508 and the north bridge chip 504 (step S701 ). Next, it is judged whether the data D1 is correct data (step S702). If the data D1 is correct, the CPU 502 directly reads the data D1 stored in the system memory 506 (step S703 ).

If the data D1 is incorrect, the computer system 500 must restore the correct data D1 according to another piece of data D2 and the parity data DP. Therefore, the disk controller 510 stores the data D2 stored in the disk 534 and the parity data DP stored in the disk 536 into the system memory 506 through the south bridge chip 508 and the north bridge chip 504 respectively (step S704 ). And the north bridge chip 504 peeks at the memory image temporary storage area 562 storing related control commands of the disk controller 510 (step S705 ). If the operating system performs a write operation to the memory image temporary storage area 562, then the north bridge chip 504 will store the disk array control command image (mapping) about the disk array accelerator 550 in the south bridge chip register 512 to the north bridge chip register 560 image temporary storage area 564 (step S706). Next, the disk array accelerator 550 reads the data D2 and the parity data DP stored in the system memory 506 according to the disk array control command of the image temporary storage area 564, and performs an inverse exclusive-or (EXCLUSIVE-NOR, XNOR) logic operation to obtain the correct data D1 (step S707). Finally, the disk array accelerator 550 writes the correct data D1 into the system memory 506 (step S708), so that the central processing unit 502 can read the correct data D1 from the system memory 506 (step S709), and then the disk controller 510 Write the correct data D1 into the disk 532 (step S710).

From the above, it can be found that because the present invention places the disk array accelerator 550 in the north bridge chip 504, the bus transmission of data between the north bridge chip 504 and the south bridge chip 506 can be reduced, so that the bandwidth of the bus can be released, and then also reduced Latency to read system memory data 506 .

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (9)

1. A chipset for redundant disk array data access, the chipset is connected between central processing unit, system memory and disk array, the chipset includes: The north bridge chip, connected between the central processing unit and the system memory, includes: The disk array accelerator is used to perform the function of accessing the first data and the second data stored in the system memory according to the disk array control command, and performing logical operations on the first data and the second data to obtain parity data; Northbridge chip register, which includes a memory image temporary storage area for storing disk controller control commands; and an image temporary storage area for storing disk array control commands; and The south bridge chip is connected between the north bridge chip and the disk array, and is used to access the data of the disk array; including: The disk controller is used to control the data access of the disk array, and the south bridge chip register is used to store the disk array control command. 2. The chip set as claimed in claim 1, wherein the image temporary storage area uses a memory image output input cycle, and the north bridge chip peeks at the memory image temporary storage area, and when an operating system or an external command is executed on the memory image temporary storage area During writing operation, the north bridge chip maps the control command of the disk array accelerator stored in the south bridge chip to the image temporary storage area. 3. A north bridge chip used for redundant disk array data access, the north bridge chip is connected between the central processing unit and the system memory, the north bridge chip is connected to the disk array through the south bridge chip, the north bridge chip includes: A disk array accelerator, which is used to perform a function of accessing first data and second data stored in the system memory according to a disk array control command, and performing a logic operation on the first data and the second data to obtain parity data; and The north bridge chip register includes the north bridge chip register, which includes a memory image temporary storage area for storing the disk controller control command; and an image temporary storage area for storing the disk array control command. 4. The north bridge chip as claimed in claim 3, wherein the image temporary storage area uses a memory image output input cycle; the north bridge chip peeps at the memory image temporary storage area, and when the operating system or an external command executes the memory image temporary storage area During write operation, the north bridge chip maps the disk array control command originally stored in the register of the south bridge chip to the image temporary storage area. 5. A disk array data access method, comprising: Map the disk array control command to the north bridge chip buffer; The disk array accelerator accesses the first data and the second data stored in the system memory according to the disk array control command; and The disk array accelerator performs logic operations on the first data and the second data according to the disk array control command to obtain third data, and writes the third data into the system memory. 6. The disk array data access method as claimed in claim 5, wherein the north bridge chip register includes a memory image temporary storage area and an image temporary storage area, wherein peeping at the memory image temporary storage area, when operating system or external command When performing a write operation on the memory image temporary storage area, the disk array control command is mapped from the south bridge chip buffer to the image temporary storage area. 7. The disk array data access method as claimed in claim 6, further comprising mapping the disk array control command from the south bridge chip buffer to the image temporary storage area, wherein the image temporary storage area uses a memory image output input cycle . 8. The disk array data access method as claimed in claim 5, wherein when executing the disk array data writing function, the central processing unit writes the first data into the system memory, and utilizes a disk controller to store the data in the disk. The second data of the array is written into the system memory, and the disk array accelerator performs an XOR logical operation on the first data and the second data to obtain parity data, and makes the disk controller make the first data and the Parity data is written to the disk array. 9. The disk array data access method as claimed in claim 5, wherein when performing the disk array data read function, utilize a disk controller to write the first data and the second data stored in the disk array to The system memory, the disk array accelerator performs an inverse XOR logical operation on the first data and the second data to obtain the third data, wherein the first data is parity data, and the central processing unit reads and stores it in the system The third data of the memory, and the disk controller enables the third data to be written into the disk array.

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