CN100511948C

CN100511948C - Method and system for conveying filter compensation coefficient for digital power control system

Info

Publication number: CN100511948C
Application number: CN 200580008019
Authority: CN
Inventors: 阿莱恩·查普斯
Original assignee: Power One Inc
Current assignee: Pai Capital Co ltd
Priority date: 2004-02-12
Filing date: 2005-01-27
Publication date: 2009-07-08
Anticipated expiration: 2025-01-27
Also published as: CN101076937A

Abstract

Provided are a method and a system for programming digital filter compensation coefficients of a numerically controlled switching power supply in a distributed power supply system. The distributed power system includes a plurality of point-of-load (POL) regulators each including at least one power switch adapted to deliver power to a load and a digital controller adapted to control operation of the power switch in response to feedback measurements. The digital controller also includes a digital filter having a transfer function defined by a plurality of filter coefficients. A serial data bus is connected to each POL regulator. The system controller is connected to the serial data bus and is adapted to transmit digital data to multiple POL regulators through the serial data bus. The digital data includes programming data for programming a plurality of filter coefficients. The system controller also includes a user interface adapted to receive programming data therefrom.

Description

Transmit the method and system of the filter compensation coefficient of digital power control system

Related application data

The application requires to enjoy the temporary patent application No.60/544 that submitted on February 12nd, 2004,553 priority according to 35 U.S.C. § 119 (c).Present patent application also requires to continue to enjoy the patent application No.10/361 that submitted on February 10th, 2003, the patent application No.10/326 that on December 21st, 667 and 2002 submitted, 222 priority according to 35U.S.C. § 120 as part.

Technical field

The present invention relates to power circuit, specifically, relate to digital power control system and method that the parameter of switch mode power supply circuit is programmed.

Background technology

Switch mode power is known in the art, is used for available direct current (DC) or exchanges (AC) level voltage being transformed into another DC level voltage.Buck converter is a kind of special switch mode power, and it enters the output inductor that is connected with load by switching flowing of electric current stores the energy in the output inductor selectively, for load provides DC output voltage through adjusting.It comprises two power switchs that dispose with mosfet transistor usually.The filtering capacitor in parallel with load reduces the ripple of output current.Pulse-width modulation (PWM) control circuit is used for the gating of power controlling switch in an alternating manner, with flowing of electric current in the control output inductor.Pwm control circuit is used by the reflection output voltage of feedback control loop transmission and/or the signal of current level, imposes on the duty cycle of power switch according to the load state adjustment that changes.

Traditional pwm control circuit is used such as operational amplifier, comparator and is resembled the resistor that is used for loop compensation and digital circuit components that the artificial circuit component the passive device the capacitor and some resemble gate and the trigger constitutes.But desirable is to use digital circuit to replace artificial circuit component fully, because digital circuit takies less physical space, draws less power, and can realize programmable functions or adaptive control technology.

Traditional digital control circuit comprises signal (for example, the output voltage (V that expression is needed control _o)) be transformed into the A-D converter (ADC) of digital signal with the error signal of the difference of benchmark with n bit.Digital control circuit provides control signal for the power switch with duty cycle with digital error signal control figure pulse width modulator, digital pulse-width modulator, makes the output valve of power supply follow the tracks of benchmark.Digital control circuit can also comprise the digital filter such as the infinite impulse response with associated transfer function (IIR) filter.Transfer function comprises the penalty coefficient of the operation that defines iir filter.Desirable is to have the ability that changes these penalty coefficients or these penalty coefficients are programmed, so that definition is for the operation of the digital filter of concrete load state.

Because electronic system often need provide power with different discrete voltage and current level, therefore be known that intermediate bus voltage is assigned to electronic system everywhere, and the point of the power consumption in electronic system place comprises POL (POL) adjuster alone, for example switching regulator DC/DC converter.Particularly, each electronic circuit is furnished with POL adjuster separately, is used for the required voltage level of intermediate bus voltage alternative cost electronic circuit.An electronic system can comprise a plurality of POL adjusters, is used for intermediate bus voltage is transformed into each voltage level.It is desirable to, the POL adjuster is arranged near corresponding electronic circuit, so that the length of the low-voltage and high-current line of cloth in electronic system is minimized.Intermediate bus voltage can flow to a plurality of POL adjusters with little electric current line, makes the loss minimum.

Adopt this distributed approach, need control and the supervision of coordination these POL adjusters of power-supply system.The POL adjuster is worked under the power-supply controller of electric that alone POL adjuster is activated, programmes and monitors cooperates usually.Be known that in this technical field controller activates each POL adjuster with multi-link parallel bus and programmes.For example, parallel bus can transmit enabling of making that each POL adjuster switches on and off/disable bit and to voltage identification (VID) code bit of the output voltage set-point programming of POL adjuster.Controller can also connect the voltage/current that each POL adjuster of monitoring is carried with other, so that detect the fault state of POL adjuster.The shortcoming of this control system is that it strengthens the complexity of whole electronic system and size.

Therefore, useful provide a kind of these and some other shortcomings that can overcome prior art switch mode power is carried out numerically controlled system and method.Also useful provide a kind of system and method that the operation of the numerical control switch mode power in the distributed power supply system is controlled and monitored.Specifically, usefully provide a kind of system and method that the digital filter compensation coefficients of the numerical control switch mode power in the distributed power supply system is programmed.

Summary of the invention

The present invention has overcome the shortcoming of prior art, and a kind of system and method that the digital filter compensation coefficients of numerical control switch mode power in the distributed power supply system is programmed is provided.

In one embodiment of the invention, a kind of power control system comprises a plurality of POLs (POL) adjuster, and each POL adjuster comprises that at least one is fit to power switch and a digitial controller that is fit to according to the operation of feedback measurement result power controlling switch to the load transmission power.Digitial controller also comprises a digital filter that has by the transfer function of a plurality of filter coefficient definition.A serial data bus is connected with each POL adjuster.There is a system controller to receive on the serial data bus, is fit to transmit numerical data to a plurality of POL adjusters by serial data bus.Numerical data comprises the programming data to a plurality of filter coefficient programmings.System controller also comprises the user interface that is fit to therefrom receive programming data.

A kind of method of control a plurality of POLs (POL) adjuster is provided in another embodiment of the present invention.Each POL adjuster comprises that at least one is fit to power switch and a digitial controller that is fit to according to the operation of feedback measurement result power controlling switch to the load transmission power.Digitial controller also comprises a digital filter that has by the transfer function of a plurality of filter coefficient definition.This method comprises the following steps: that (a) receives the programming data to a plurality of filter coefficient programmings; (b) send programming data by the common data bus serial that is connected with a plurality of POL adjusters; And (c) a plurality of filter coefficients of some the relevant POL adjusters in a plurality of POL adjusters are programmed according to programming data.Specifically, receiving step also comprises the programming data of reception from the user.

In yet another embodiment of the present invention, provide a kind of point-of-load regulator, this point-of-load regulator comprises a power converting circuit that is fit to intermediate voltage is transformed to output voltage.Power converting circuit comprises that at least one is fit to power switch and a digitial controller that is fit to according to the operation of feedback measurement result power controlling switch to the load transmission power.Digitial controller also comprises a digital filter that has by the transfer function of a plurality of filter coefficient definition.A serial data bus interface is fit to send the programming information of the external series data/address bus that is connected with it certainly.A controller is connected with power converting circuit with serial data bus interface, is fit to determine a plurality of filter coefficients according to the programming data that receives by serial data bus interface.

In yet another embodiment of the present invention, provide a kind of method to the power control system programming.Power control system comprises a plurality of POLs (POL) adjuster, and each POL adjuster comprises that at least one is fit to power switch and a digitial controller that is fit to according to the operation of feedback measurement result power controlling switch to the load transmission power.Digitial controller also comprises a digital filter that has by the transfer function of a plurality of filter coefficient definition.This method comprises: (a) show the screen of the operation of an exemplary point-of-load regulator of at least one simulation, described at least one screen comprises that the user can be the value of the characteristic selection of exemplary point-of-load regulator; (b) receive user's input of selecting at user option value; (c) calculating is imported the corresponding digital filter coefficient with the user; And (d) will send at least one point-of-load regulator in a plurality of point-of-load regulator to the corresponding data of the filter coefficient that is calculated selectively, for described digital filter programming is used.

Description of drawings

Be used for filter coefficient is sent to the system and method for a plurality of point-of-load regulator in the power-supply system and realizes other advantages of the present invention and purpose from understanding more all sidedly below with reference to those skilled in the art that the accompanying drawing detailed description of preferred embodiments, in these accompanying drawings:

Fig. 1 shows the switch mode power with digital control circuit;

Fig. 2 shows provides the window of high and low saturation signal formula fast A C;

Fig. 3 shows the digitial controller with infinite impulse response filter and error controller;

Fig. 4 shows the exemplary control system that transmits filter compensation coefficient according to one embodiment of the present of invention;

Fig. 5 shows the exemplary POL adjuster of POL control system;

Fig. 6 shows the example system controller of POL control system;

Fig. 7 is the exemplary screen schematic diagram that the graphic user interface (GUI) of the operation of simulating the POL adjuster is shown; And

Fig. 8 is the exemplary screen schematic diagram that the GUI that the penalty coefficient of digitial controller is programmed is shown.

Embodiment

The invention provides and a kind of switch mode power is carried out numerically controlled method.Specifically, the invention provides a kind of system and method that the digital filter compensation coefficients of numerical control switch mode power in the distributed power supply system is programmed.In the following detailed description, the same unit shown in same element numerals is used for being labeled in one or more figure.

Fig. 1 shows the exemplary switch mode power 10 with digital control circuit according to one embodiment of the present of invention design.Power supply 10 comprises input dc voltage V _InBe transformed into output dc voltage V _oBe added to resistive load 20 (R _Load) on the layout of buck converter.Power supply 10 comprises a pair of

power switch

12,14 with the MOSFET cell configuration.The source terminal of high side power switch 12 is received input voltage V _InOn, the source terminal ground connection of low side power switch 14, and the drain electrode end of

power switch

12,14 is connected together and determines a phase node.Output inductor 16 is connected on the phase node and output voltage V is provided _oTerminal between, and capacitor 18 and resistive load R _LoadIn parallel.Corresponding

driving device

22,24 alternately drives the gate terminal of power switch 12,14.

Driver

22,24 is again by digital control circuit 30 controls (explanation below).The switching of

power switch

12,14 is provided at the intermediate voltage that has the general rectangular waveform on the phase node, and the filter that is formed by output inductor 16 and capacitor 18 is transformed into square waveform the output voltage V that is essentially DC _o

The feedback signal that digital control circuit 30 receives from the output of power supply 10.As shown in Figure 1, feedback signal and output voltage V _oCorresponding, though be appreciated that feedback signal also can (or all right) and resistive load R _LoadOutput current that is drawn or expression need by any other signal of digital control circuit 30 controls corresponding.Feedback path can also comprise the output voltage V that will be detected _oBe reduced to the voltage divider (not shown) of exemplary voltages level.Digital control circuit 30 provides duty cycle to be controlled so as to output voltage V _o(or output current) adjusts to the pulse-width modulation waveform of desirable level.Even this exemplary power supply 10 is shown the layout with buck converter, but be appreciated that this feedback control loop control of carrying out with 30 pairs of power supplys of digital control circuit 10 be equally applicable to such as isolate and non-isolation structure boost with the buck-boost converter the layout and the different control strategies that are called voltage mode, current-mode, charge mode and/or average-current mode controller of other known power source.

Specifically, digital control circuit 30 comprises A-D converter (ADC) 32, digitial controller 34 and digital pulse-width modulator (DPWM) 36.ADC32 also comprises feedback signal (that is output voltage V, that receives as input _o) and voltage reference (Ref), produce the poor (Ref-V of expression input _o) digital voltage error signal (VEd _k) window formula fast A C.Digitial controller 34 has voltage error signal VEd _kBe transformed into numeral and export the transfer function G (z) that offers DPWM36, the waveform (PWM that DPWM 36 becomes to have proportional pulsewidth with this signal transformation _k).The filter compensation coefficient that digitial controller 34 receptions are used for transfer function G (z) is as input, and this also will further specify below.Pulse modulation waveform PWM as discussed above, that DPWM 36 is produced _kReceive by

corresponding driving device

22,24 on the gate terminal of

power switch

12,14.

Fig. 2 shows the exemplary window formula fast A C 40 that is used for digital control circuit 30.Voltage reference Ref and output voltage V that ADC 40 receives as input _oVoltage reference is added to and comprises and be connected on reference voltage terminal and receive positive voltage (V _DD) on current source between resistor 42A, 42B, 42C, 42D and be connected on reference voltage terminal and the current source of ground connection between the central authorities of resistor ladder of resistor 44A, 44B, 44C, 44D.These resistors respectively have corresponding resistance value, determine a plurality of voltage increments above and below voltage reference Ref with current source.The size of resistance value and/or current source can be chosen to determine the LSB resolving power of ADC 40.The comparator array that comprises a plurality of positive side comparator 46A, 46B, 46C, 46D and a plurality of negative side comparator 48A, 48B, 48C, 48D is received on the resistor ladder.Positive side comparator 46A, 46B, 46C, 46D respectively have one to receive non-inverting input terminal on the output voltage V o and the inverting terminal on respective resistors of receiving among resistor 42A, 42B, 42C, the 42D.Similarly, negative side comparator 48A, 48B, 48C respectively have one to receive output voltage V _oOn non-inverting input terminal and the inverting terminal on respective resistors of receiving among resistor 44A, 44B, 44C, the 44D.Negative side comparator 48D has the non-inverting input terminal of a ground connection and receives output voltage V _oOn inverting terminal.Be appreciated that to comprise more resistors and comparator, with increase voltage increment number, thus the scope of increase ADC 40, and just exemplarily show a limited number of resistors and comparator among Fig. 2.

ADC 40 also comprises the logical device 52 that is connected with the output of comparator 46A, 46B, 46C and 48A, 48B, 48C.Logical device 52 receives comparator output, and expression digital voltage error VEd is provided _kMany bits (for example, 4 bits) and line output.For instance, surpass voltage increment of reference voltage Ref (for example, output voltage V 5mV) _oTo make the output of comparator 46B, 46A, 48A, 48B and 48C become high level, and make the output of comparator 46C, 46D and 48D remain low level.Logical device 52 is interpreted as logic level 9 (or binary one 001) with this, produces associated voltage error signal VEd _kBe appreciated that voltage reference Ref is variable, so that the window of mobile ADC 40.If output voltage V _oSurpass the highest voltage increment of resistor ladder, the output of comparator 46D just provides a HIGH (height) saturation signal.Similarly, if output voltage V _oBe lower than the lowest voltage increment of resistor ladder, the output of comparator 48D just provides a LOW (low) saturation signal.

Figure 3 illustrates digitial controller with digital filter and ADC 40.Digital filter further comprised according to former voltage error input VEd _kWith former output PWM ' _kProduce output PWM ' _kInfinite impulse response (IIR) filter.As discussed above, ADC 40 provides voltage error input VEd _kDigital filter output PWM ' _kOffer digital pulse-width modulator (DPWM) 36, digital pulse-width modulator 36 is with pulse-width modulation control signal (PWM _k) offer the power switch of power supply.

Iir filter illustrates with the block diagram form, comprise a plurality of first

delay time registers

72,74 ..., 76 (respectively be designated as z ^-1), a plurality of have

coefficient

71,73 ..., 77 (be designated as C0, C1 ..., Cn) first mathematical operator (multiplier), a plurality of second mathematical operator (adder) 92,94,96, a plurality of second

delay time register

82,84 ..., 86 (respectively be designated as z ^-1) and a plurality of have coefficient 83,87 (be designated as B1 ..., Bn) the 3rd mathematical operator (multiplier).First

delay time register

72,74,76 is respectively preserved voltage error VEd _kA sampling in the past, a corresponding coefficient weighting in the

coefficient

71,73,77 is used in this sampling again.Similarly, second delay time register, 82,84,86 each preservation output PWM ' _kA sampling in the past, a corresponding coefficient weighting in the

coefficient

83,87 is used in this sampling again.Adder 92,94 and 96 will combine through the input and output sampling of weighting.Be appreciated that in the iir filter to comprise more delay time registers and coefficient, and just exemplarily show limited several among Fig. 3.Digital filter configuration shown in Fig. 3 is the exemplary realization of following transfer function G (z):

G (z) = \frac{PWM (z)}{VEd (z)} = \frac{C_{0} + C_{1} \cdot z^{- 1} + C_{2} \cdot z^{- 2} + . . . + C_{n} \cdot z^{- n}}{1 - B_{1} \cdot z^{- 1} - B_{2} \cdot z^{- 2} - . . . - B_{n} \cdot z^{- n}}

Error controller 62 receives the input signal of the error condition of a plurality of reflection ADC 40 and digital filter.Specifically, error controller 62 receives and reflects HIGH and the LOW saturation signal of output voltage V o above and below the ADC voltage window respectively from ADC 40.Mathematical operator (adder) 92,94,96 respectively provides the spill over of the situation of overflowing (that is carry-out bit) of a reflection mathematical operator to error controller 62.Digital filter also is included in when arriving upper and lower range limit output PWM ' _kThe scope limiter 81 of amplitude limit.In this case, scope limiter 81 provides corresponding limit signal for error controller 62.

These input signals of error controller 62 usefulness change the operation of digital filter, so that improve the response of digital filter to the load state of change.Error controller 62 is connected with second

delay time register

82,84,86 with each first

delay time register

72,74,76, so that can reset and/or preset being stored in wherein value.As used herein, " resetting " value of being meant is set to initial value (for example, zero), and " presetting " value of being meant is set to another predetermined value.Particularly, error controller 62 can replace voltage error VEd with the predetermined value that changes power supply characteristic _kWith output PWM ' _kSampling in the past.Error controller 62 receive need as

coefficient

71,73 ..., 77 and 83 ..., 87 data value imports as the outside.Be appreciated that can by for

coefficient

71,73 ..., 77 and 83 ..., 87 select suitable data value that the characteristic of digital filter is programmed.

Digitial controller comprises that also permission is at PWM ' _kThe multiplexer of selecting between the pre-set output signal that output signal and error controller 62 are provided 64.Which signal the selection signal that error controller 62 is provided determines to allow by multiplexer 64.Enter HIGH or LOW when saturated at ADC40, error controller 62 by control multiplexer 64 with PWM ' _kSignal is set to specific predetermined value (or value of sampling before a series of the depending in part on).In order to recover smoothly from this situation, error controller also can change these delayed input and output samplings by reloading a plurality of first

delay time registers

72,74,76 and a plurality of second

delay time register

82,84,86.This will guarantee that feedback control loop is at the controlled characteristic of ADC 40 during from saturation recovery.

For instance, if ADC 40 suffered is just saturated, promptly the LOW signal is changed into high level state from low level state, just can be with PWM ' _kSampling is reset to zero, to help to reduce error.By with PWM ' _kSampling is reset to zero, and the pulsewidth that sends the high side power switch 12 of power supply 10 to goes to zero, thereby disconnects the power supply to resistive load 20 (see figure 1)s effectively.In order to recover smoothly from this situation, also can be with sampling PWM ' _K-1, PWM ' _K-2..., PWM ' _K-nBe reset to zero or be predisposed to another value and smoothly recover so that allow.Similarly, if ADC 40 suffered is negative saturated, promptly the HIGH signal is changed into high level state from low level state, just can be with PWM ' _kSampling is predisposed to maximum, sends the pulsewidth of high side power switch 12 to increase, reduces error.In addition, when generation digital filter internal digital was overflowed, error controller 62 can take measures to prevent the uncontrolled order of power switch, such as the input and output sampling that changes digital filter.

The switch mode power of Fig. 1 also comprises POL (POL) adjuster at the power consumption point place that is arranged on electronic system in one embodiment of the invention.Power control system comprises that a plurality of same POL adjusters, data/address bus that at least one is connected with a plurality of POL adjusters and one receive and is fit on the data/address bus send numerical datas and from the system controller of a plurality of POL adjuster receiving digital datas to a plurality of POL adjusters.System controller transmit data by universal serial bus in case with

coefficient

71,73 ..., 77 and 83 ..., 87 value programmes to digital filter transfer function G (z).

Referring now to Fig. 4,, there is shown POL control system 100 according to the embodiments of the invention design.Specifically, POL control system 100 comprises system controller 102, front-end regulator 104 and is configured to a plurality of POL adjusters 106,108,110,112 and 114 of an array.The POL adjuster that goes out shown here is including, but not limited to point-of-load regulator, electric adjuster, DC/DC converter, voltage adjuster and those skilled in the art every other programmable voltage or the current adjusting device known to usually.Between some independent POL adjusters, dispose the device interior interface, be used for controlling such as electric current share or concurrent working specific interaction, for example be configured in the shared interface (CS1) of electric current between POL0 106 and the POL1 108 and be configured in POL4 112 and POLn 114 between CS2.In this exemplary configuration shown in Figure 4, POL0 106 and POL1 108 produce the output voltage V that current capacity increases with parallel schema work _O1, POL2 110 produces output voltage V _O2, and POL4 112 and POLn 114 produce output voltage V also with parallel schema work _O3, certainly can understand, can use the POL adjuster of other POL adjuster combinations and other quantity valuably.

Front-end regulator 104 provides intermediate voltage by the intermediate voltage bus for these POL adjusters, and front-end regulator 14 can be exactly another POL adjuster.System controller 102 and front-end regulator 104 can be integrated in the individual unit, also can be configured to device separately.Perhaps, front-end regulator 104 can provide a plurality of intermediate voltages for these POL adjusters by a plurality of intermediate voltage buses.System controller 102 can obtain its power from middle voltage bus.

System controller 102 writes by the unidirectional or bidirectional linked list bus that is shown synch/data (synchronous/data) bus in Fig. 4 and/or no matter still asynchronously synchronously reading number data () communicate by letter with these POL adjusters.The Synch/data bus can comprise two-wire serial bus (for example, the I that allows the data asynchronous transmission ²C) or allow data sync to send the single serial bus of (that is, synchronous) with clock signal.For each POL of POL addressing to any appointment in the array labels with a unique address that can be hardwired or additive method are set.For example, system controller 102 is programmed with digital filter transfer function G (z) coefficient to each POL adjuster by the synch/data bus transmissioning data.System controller 102 is also communicated by letter with these POL adjusters by the second unidirectional or bidirectional linked list bus that is shown Ok/fault (correct/fault) bus in Fig. 4, carries out fault management.By a plurality of POL adjusters are received on the common OK/fault bus they are combined, allow these POL adjusters to have identical behavior under the situation of fault state having.In addition, system controller 102 is also communicated by letter with the custom system that POL control system 10 is programmed, is provided with and monitored by user interface bus.At last, system controller 102 is communicated by letter with front-end regulator 104 by independent line, to forbid front-end regulator work.

At length show the exemplary POL adjuster 106 of POL control system 10 among Fig. 5.Other POL adjusters among Fig. 4 have substantially the same configuration.POL adjuster 106 comprises that power converting circuit 142 (for example, for Fig. 1 switch mode power), serial line interface 144, POL controller 146, default configuration memory 148 and hardwired are provided with interface 150.Power converting circuit 142 according to the setting that receives by serial line interface 144, hardwired be provided with 150 or default setting with input voltage (V _i) be transformed to desirable output voltage (V _o).Power converting circuit 142 can also comprise that output voltage, electric current, temperature and other are used for carrying out local control and pass the monitoring sensor of the parameter of system controller by serial line interface 144 back.Also (power supply is good, and PG) output signal is so that provide the monitoring function of simplification for independent utility produces Power Good for power converting circuit 142.Serial line interface 144 sends order and message by synch/data and OK/fault universal serial bus to system controller 102.Default configuration memory 148 is stored in not the default configuration that the POL adjuster 106 under the situation that interface 150 receives programming signal is set by serial line interface 144 or hardwired.Default configuration is chosen to make POL adjuster 106 not having work under " safety " state under the situation of programming signal.

Hardwired is provided with interface 150 and is connected communication with outside, under without the situation of serial line interface 144 the POL adjuster is programmed.Hardwired is provided with the address setting (Addr) that interface 150 can comprise the POL of conduct input, with (promptly by the address, the identifier of POL) change or setting some settings wherein, for example, phase shift, enable/disable bit (En), finishing (TRIM), VID code bit, and select different (predefined) digital filter coefficient group different output filter structure optimizations.In addition, the address is also communicating operating period sign POL adjuster by serial line interface 144.The trim input allows to connect the non-essential resistance of one or more regulation POL adjuster output-voltage levels.Similarly, the VID code bit can be used to the programming of POL adjuster, to obtain desirable output voltage level.Enable/disable bit makes POL adjuster on/off by triggering into digital high/low level signal.

146 receptions of POL controller and priorization are to the setting of POL adjuster.If by hardwired interface 150 is not set or serial line interface 144 receives configuration information, POL controller 146 just inserts the parameter that is stored in the default configuration memory 148.Perhaps, receive configuration information if by hardwired interface 150 is set, POL controller 146 is just used those parameters.Therefore, default setting is applied to the parameter that all can not or not be provided with by hard wire.Hardwired is provided with the information overwrite that can be received by serial line interface 144 that is provided with that interface 150 receives.Therefore, the POL adjuster can be with the pattern work of stand-alone mode, complete programmable pattern or both combinations.This flexibility of programming can satisfy a plurality of different application of power with single general POL adjuster, thereby has reduced cost, has simplified the manufacturing of POL adjuster.

For instance, system controller 102 transmits data value by the synch/data bus to specific POL adjuster 106, uses for digital filter coefficient is programmed.Serial line interface 144 just sends POL controller 146 to after receiving these data values.The POL controller sends these data values to power converting circuit 142 with some instructions again, and digital filter coefficient is programmed.

Fig. 6 shows the example system controller 102 of POL control system 100.System controller 102 comprises user interface 122, POL interface 124, controller 126 and memory 128.User interface 122 sends to user and the message that receives from the user by user interface bus with message.User interface bus can be by the serial or parallel bidirectional interface that uses standard interface protocol I for example ²C interface provides.User profile such as monitor value or new system are provided with sends by user interface 122.The 124 pairs POL interfaces by synch/data and OK/fault universal serial bus give/carry out conversion from the data of POL adjuster.POL interface 124 sends by the synch/data universal serial bus and data is set and receives Monitoring Data, and receives the interrupt signal of the fault state at least one POL adjuster in the POL adjuster of pointing out to be connected by the Ok/fault universal serial bus.Memory 128 comprise the system that is used for storing to the POL adjuster that is connected with system controller 102 be provided with parameter (for example, output voltage, electric current restriction set-point, timing data, or the like) nonvolatile memory.Optional on demand is, an auxiliary external memory storage 132 can also be connected with user interface 122, so that for Monitoring Data or the memory span that data provide increase is set.

Controller 126 is connected with user interface 122, POL interface 124 and memory 128.Controller 126 has the outside port that disables (FE DIS) is sent to front-end regulator 104.When POL control system 100 started, controller 126 memory 128 (and/or external memory storage 132) read-out system setting was internally programmed by 124 pairs of POL adjusters of POL interface in view of the above.Each POL adjuster is provided with in the mode of stipulating according to system program design and starts.In normal work period, controller 126 pairs of any order or source codecs from user or POL adjuster are carried out.Controller 126 monitors the performance of POL adjuster, and this information is reported to the user by user interface 122.The POL adjuster can also be programmed to by controller 126 by the user fault such as overcurrent or overvoltage situation is carried out specific autonomic response.Perhaps, the POL adjuster can be programmed to and just fault state be reported to system controller 102, according to definite suitable counter-measure that is provided with of predesignating, for example turn-off front-end regulator by FE DIS control line by system controller 102.

Monitoring component 130 can be optional on demand, and what be used for monitoring power-supply system is not other the one or more voltages that are connected with controller 102 by synch/data or OK/fault bus or the state of current level.Monitoring component 130 can provide this information to controller 126, reports to the user in the mode identical with other information that relate to POL control system 10 by user interface.Like this, POL control system 10 can provide with electronic system in some back compatible of the power-supply system that existed.

As discussed above, system controller 102 has and the interface that the performance of POL control system is programmed and communicated by letter with the custom system that monitors.The computer that custom system comprises directly or is connected with interface by network, it has suitable suitable software of communicating by letter with system controller 102.Known in this technology, computer is equipped with such as based on MicrosoftWindows ^TMThe user interface based on figure at interface and so on (GUI) contains movable window, icon and mouse.GUI can comprise the expression text and the graphical format through pre-programmed of standard, known to common in this technical field.The information that receives from system controller 102 is presented on the computer screen by GUI, and the user can change the operation of POL control system is programmed and monitored by the specific screens of GUI being done some.

Fig. 7 illustration be used for simulating the exemplary screen of GUI of the operation of POL adjuster.Screen shows the POL adjuster that has with the illustrated exemplary switch mode power 10 corresponding layouts of the above Fig. 1 of combination.The POL adjuster comprises a pair of power switch, output inductor L with the MOSFET cell configuration _OWith a capacitor C _O18.The POL regulator output is by pi type filter and load resistance R _LConnect, pi type filter is by the inductance L of series connection ₁With internal resistance RL ₁, be in the capacitor C of pi type filter first end ₁With internal resistance RC ₁With the capacitor C that is in pi type filter second end ₂With internal resistance RC ₂Form.The POL adjuster also is included as power switch PWM drive signal and the output current IL that receives as feedback signal is provided _OAnd output voltage V _OControl circuit.Output voltage can detect from any end of transmission line by a switch is set.

GUI makes the user can define the value of each parameter of POL adjuster, so that simulate its working condition.The definable parameter of each user comprises a hurdle that allows the user to import desirable data value.The user can be such as the voltage V of first end that passes through the definition pi type filter ₁, pi type filter second end voltage V ₂, the width of voltage delay, rising and fall time and power switch driving pulse and the cycle parameter of selecting output voltage.The user also can select load distribution parameters, comprises the resistance, electric capacity and the inductance that define pi type filter.The user also can define load resistance and load current characteristic.

In case the user is for after the POL adjuster selected desirable parameter, GUI just can carry out simulation according to selected parameter.Fig. 8 illustration with figure the exemplary screen of GUI of the transfer function G (z) of POL adjuster is shown.Transfer function shows the amplitude of gain and the phase place change situation with frequency with figure.As the part of simulation, calculate the filter coefficient of the digital filter of digital PWM, be presented on the screen.The user can change the shape of gain curve with the slide potentiometer of the pole and zero of adjusting transfer function, can simulate the POL adjuster repeatedly, meets the demands up to results of property.So the user can select a suitable button that selected digital filter coefficient is used for single POL adjuster or a POL adjuster group or all POL adjuster groups on a specific printed circuit board (PCB).This operation can make selected filter coefficient be stored in the nonvolatile memory contained in the system controller 102, again by synch/data bus each suitable substance P OL adjuster that sends to as discussed above.

From the explanation of the preferred embodiment of the top system and method that the digital filter compensation coefficients of numerical control switch mode power in the distributed power supply system is programmed, the personnel that are familiar with this technical field obviously can see the certain advantage that had realized this system already.Also should be appreciated that, under the situation that does not deviate from scope and spirit of the present invention, can carry out various modifications, adjustment and replacement these embodiment.The present invention is further by following claims definition.

Claims

1. A power control system, the power control system comprising:

a plurality of point-of-load regulators, each point-of-load regulator comprising at least one power switch adapted to deliver power to a load and a digital controller adapted to control operation of the at least one power switch in response to feedback measurements, the digital controller further comprising a digital filter having a transfer function defined by a plurality of filter coefficients;

a serial data bus connected to the plurality of point-of-load regulators; and

a system controller coupled to said serial data bus and adapted to transmit digital data via said serial data bus to said plurality of point-of-load regulators, said digital data comprising parameters for said plurality of filter coefficients programmed programming data.

2. The power control system of claim 1, wherein said system controller further includes a user interface adapted to receive said programming data therefrom.

3. The power control system of claim 1, wherein said digital filter further comprises an infinite impulse response filter.

4. The power supply control system of claim 3, wherein said infinite impulse response filter provides the following transfer function G(z):

G G ((z z)) = = \frac{PWM PWM ((z z))}{VEd VEd ((z z))} = = \frac{{C C}_{00} + + {C C}_{11} \cdot &Center Dot; {z z}^{- - 11} + + {C C}_{22} \cdot &Center Dot; {z z}^{- - 22} + + . . . . . . + + {C C}_{n no} \cdot &Center Dot; {z z}^{- - n no}}{11 - - {B B}_{11} \cdot &Center Dot; {z z}^{- - 11} - - {B B}_{22} \cdot &Center Dot; {z z}^{- - 22} - - . . . . . . - - {B B}_{n no} \cdot &Center Dot; {z z}^{- - n no}}

Wherein PWM(z) is a digital control output, VEd(z) is an error signal, and the plurality of filter coefficients include C ₀ , ..., C _n as input side filter coefficients and output side filter coefficients B ₁ , . . . , B _n .

5. The power control system of claim 1, wherein said digital controller further comprises:

an analog-to-digital converter providing a digital error signal representing the difference between said feedback measurement and a reference value, said digital filter providing a digital control output based on the sum of the current and previous error signals and the previous control output;

an error controller adapted to modify the operation of said digital filter according to error conditions; and

a digital pulse width modulator providing a control signal to said at least one power switch, said control signal having a pulse width corresponding to said digital control output.

6. A method of controlling a plurality of point-of-load regulators, each point-of-load regulator comprising at least one power switch adapted to deliver power to a load and a digital controller adapted to control operation of said at least one power switch in response to feedback measurements device, said digital controller also includes a digital filter with a transfer function defined by a plurality of filter coefficients, said method comprising the steps of:

receiving programming data for programming the plurality of filter coefficients;

sending the programming data serially over a common data bus connected to the plurality of point-of-load regulators; and

The plurality of filter coefficients of a respective one of the plurality of point-of-load regulators is programmed according to the programming data.

7. The method of claim 6, wherein said receiving step further comprises receiving said programming data from a user.

8. The method of claim 6, wherein said programming step further comprises programming said digital filter to provide the following transfer function G(z):

G G ((z z)) = = \frac{PWM PWM ((z z))}{VEd VEd ((z z))} = = \frac{{C C}_{00} + + {C C}_{11} \cdot &Center Dot; {z z}^{- - 11} + + {C C}_{22} \cdot &Center Dot; {z z}^{- - 22} + + . . . . . . + + {C C}_{n no} \cdot &Center Dot; {z z}^{- - n no}}{11 - - {B B}_{11} \cdot &Center Dot; {z z}^{- - 11} - - {B B}_{22} \cdot &Center Dot; {z z}^{- - 22} - - . . . . . . - - {B B}_{n no} \cdot &Center Dot; {z z}^{- - n no}}

9. A point-of-load regulator comprising:

a power conversion circuit adapted to convert an intermediate voltage to an output voltage, said power conversion circuit comprising at least one power switch adapted to deliver power to a load and a digital controller adapted to control operation of said at least one power switch in response to feedback measurements , the digital controller further includes a digital filter having a transfer function defined by a plurality of filter coefficients;

a serial data bus interface adapted to transfer programming information from an external serial data bus connected to the serial data bus interface; and

a controller coupled to the serial data bus interface and the power conversion circuit, the controller adapted to determine the plurality of filter coefficients based on programming data received through the serial data bus interface.

10. The point-of-load regulator of claim 9, wherein said digital controller further comprises:

an analog-to-digital converter providing a digital error signal representing the difference between said output measurement and a reference value, said digital filter providing a digital control output based on the sum of the current and previous error signals and the previous control output;

11. The point-of-load regulator of claim 10, wherein said analog-to-digital converter is adapted to receive a reference voltage that is used to condition said analog-to-digital converter to convert a specified range of analog signals to digital signals.

12. The point-of-load regulator of claim 11, wherein said analog-to-digital converter provides a HIGH signal reflecting negative saturation of said analog-to-digital converter and a LOW signal reflecting positive saturation of said analog-to-digital converter.

13. The point-of-load regulator of claim 9, wherein said digital filter further comprises an infinite impulse response filter.

14. The point-of-load regulator of claim 13, wherein said infinite impulse response filter provides the following transfer function G(z):

G G ((z z)) = = \frac{PWM PWM ((z z))}{VEd VEd ((z z))} = = \frac{{C C}_{00} + + {C C}_{11} \cdot \cdot {z z}^{- - 11} + + {C C}_{22} \cdot &Center Dot; {z z}^{- - 22} + + . . . . . . + + {C C}_{n no} \cdot &Center Dot; {z z}^{- - n no}}{11 - - {B B}_{11} \cdot &Center Dot; {z z}^{- - 11} - - {B B}_{22} \cdot &Center Dot; {z z}^{- - 22} - - . . . . . . - - {B B}_{n no} \cdot \cdot {z z}^{- - n no}}

Among them, PWM(z) is a digital control output, VEd(z) is an error signal, C ₀ , ..., C _n are input side coefficients, and B ₁ , ..., B _n are output side coefficients.

15. The point-of-load regulator of claim 10, wherein said digital filter further includes a range limiter adapted to clip said digital control output when an upper or lower range limit is reached.

16. The point-of-load regulator of claim 15, wherein said range limiter provides a limit signal to said error controller when said upper or lower range limit is reached.

17. The point-of-load regulator of claim 10, wherein said digital controller further comprises a multiplexer connected to said error controller and said digital filter, said error controller to The multiplexer provides an alternate digital control output to the digital pulse width modulator.

18. The point-of-load regulator of claim 10, wherein said error controller is further adapted to preset at least one of said previous error signals with a predetermined value based on said error condition.

19. The point-of-load regulator of claim 10, wherein said error controller is further adapted to preset at least one of said previous control outputs with a predetermined value based on said error condition.

20. The point-of-load regulator of claim 10, wherein said error controller is further adapted to reset at least one of said previous error signals to an initial value based on said error condition.

21. The point-of-load regulator of claim 10, wherein said error controller is further adapted to reset at least one of said previous control outputs to an initial value based on said error condition.

22. The point-of-load regulator of claim 10, wherein said error condition further comprises saturation of said analog-to-digital converter.

23. The point-of-load regulator of claim 10, wherein said error condition further comprises said digital filter math overflow.

24. A method of programming a power supply control system comprising a plurality of point-of-load regulators, each point-of-load regulator comprising at least one power switch adapted to deliver power to a load and a power switch adapted to control said at least one power switch in response to feedback measurements A digital controller for the operation of a switch, said digital controller further comprising a digital filter having a transfer function defined by a plurality of filter coefficients, said method comprising the steps of:

displaying at least one screen simulating operation of an exemplary point-of-load regulator, the at least one screen including values selectable by a user for characteristics of the exemplary point-of-load regulator;

receiving user input to select said user-selectable value;

calculating digital filter coefficients corresponding to said user input; and

Data corresponding to the calculated filter coefficients is selectively communicated to at least one point-of-load regulator of the plurality of point-of-load regulators to program the digital filter.

25. The method of claim 24, wherein the user-selectable value includes at least one of a resistance value, an inductance value, a capacitance value, an output voltage, an output current, and a load resistance.

26. The method of claim 24, further comprising programming said digital filter of said at least one point-of-load regulator with said data corresponding to said calculated filter coefficients.

27. The method of claim 24, wherein said step of selectively transmitting further comprises receiving user input to selectively transmit said data to a selected one of said plurality of point-of-load regulators regulators, a plurality of point-of-load regulators of the plurality of point-of-load regulators assigned to a group, and all of the plurality of point-of-load regulators of the power supply control system.