CN100508066C - Method and apparatus for read phase correction for memory devices - Google Patents
Method and apparatus for read phase correction for memory devices Download PDFInfo
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- CN100508066C CN100508066C CNB2003101243430A CN200310124343A CN100508066C CN 100508066 C CN100508066 C CN 100508066C CN B2003101243430 A CNB2003101243430 A CN B2003101243430A CN 200310124343 A CN200310124343 A CN 200310124343A CN 100508066 C CN100508066 C CN 100508066C
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Abstract
The invention discloses a method and a related mechanism for performing read phase auto-calibration on a memory device. The method comprises the following steps: writing data of at least one preset mode into the storage device; reading data written to the memory device at one of a plurality of read phases; checking the correctness of the data read in the reading step corresponding to the predetermined pattern corresponding to one of the plurality of reading phases; and determining an optimum phase among the plurality of read phases based on the checking result of the checking step.
Description
Technical field
The present invention relates to a kind of memory storage, refer to that especially a kind of memory storage reads method for correcting phase and related mechanism.
Background technology
To reading in the process of a memory storage (as a dynamic RAM---DRAM:Dynamic RandomAccess Memory), need a reference signal (as the DQS signal) usually as the foundation that latchs the data stream of (latch) data-signal.This reference signal can be exchanged into the trigger pip that above-mentioned latch data flows through Cheng Suoxu through a comparer and a delay chain (delay chain), and this trigger pip one of is generally in the middle of at least one standard delay unit (standard delay cell) of this delay chain the output signal of standard delay unit.Wherein, the output signal of each standard delay unit reads phase place corresponding to one.For example have in the delay chain of four standard delay unit one, what the output terminal of this standard delay unit can be exported 90 degree, 180 degree, 270 degree, 360 degree in regular turn reads the pairing trigger pip of phase place.
The phase place that reads that reads the data that are stored in this memory storage with respect to this reference signal is a stationary phase.That is to say, use the system producer of this memory storage as element, at the beginning of design, must see through Correlated Case with ARMA Measurement and the experiment of examination mistake, in the middle of the output terminal of this standard delay unit, determine an output terminal to export this trigger pip, with the phase place that reads that determines that this memory storage is suitable for.Therefore the design process at product can expend many times, manpower and material cost, when these products when problem takes place in the volume production stage, also must expend time in, manpower, the printed circuit board (PCB) of each product be revised (rework) one by one to revise its phase place that reads to this memory storage with material cost.
Summary of the invention
Therefore, fundamental purpose of the present invention is, provides a kind of memory storage to read method for correcting phase and related mechanism, to address the above problem.
The invention provides and a kind of a memory storage is read the method for phase correction, this method has: the data that this memory storage write at least one preassigned pattern (predetermined pattern); Read phase place with a plurality of one of read in the middle of the phase place, read the data that are written into this memory storage; Read phase place corresponding to this a plurality of one of reads in the middle of the phase place, check that data that this read step reads correspond to the correctness of this preassigned pattern; And check the check result of step according to this, a plurality ofly determine a preferable phase place in the middle of reading phase place at this.
The present invention is in providing said method simultaneously, also provide a kind of accordingly a memory storage is read the circuit of phase place from normal moveout correction, this circuit has: a control module, be coupled to this memory storage, be used for determining a preferable phase place in the middle of reading phase place, and export a multiplex (MUX) according to this preferable phase place and select signal a plurality of; One delay chain is used for producing at least one inhibit signal; An and multiplexer, be coupled to this control module and this delay chain, be used for selecting signal multiplex (MUX) in the middle of the inhibit signal that this delay chain produced to select (multiplexing) inhibit signal, to latch the data stream that (latch) this memory storage is exported according to this multiplex (MUX).This multiplexer can also select the signal multiplex (MUX) to select the output signal of the input signal of this delay chain as this multiplexer according to this multiplex (MUX).
The present invention's method can read the correction of phase place, therefore can save time, manpower and the material cost of the design process of product.
Because the present invention's method can read phase place from normal moveout correction, so need not revise (rework) one by one to revise its phase place that reads to this memory storage to the printed circuit board (PCB) of each product.
Description of drawings
Fig. 1 reads the schematic flow sheet of the automatic bearing calibration of phase place for memory storage of the present invention,
Fig. 2 is the synoptic diagram of related elements of the method for Fig. 1.
Description of reference numerals
| 101,102 ..., 115 |
| 210 |
| 220 |
| 230 multiplexers |
| DQS, VREF, TD0, TD1 ..., TD15, SEL, TRIG signal |
Embodiment
Please also refer to Fig. 1 and Fig. 2, Fig. 1 reads the schematic flow sheet of one of method for correcting phase embodiment for memory storage of the present invention, and Fig. 2 is the synoptic diagram of related elements of method of the embodiment of Fig. 1.The present invention's embodiment provides a kind of method that a memory storage (be example with DDR:Double DataRate storer in the present embodiment, be not shown in relevant indicators) is read phase correction.Wherein step 10,20,30, with 40 all in the control module 210 of Fig. 2, carry out.Following steps order and non-limiting the present invention's scope, the method for present embodiment is described as follows:
Step 10: the data that this memory storage write at least one preassigned pattern (predetermined pattern);
Step 20: one of read in the middle of the phase place with a plurality of (being 16 in the present embodiment) and to read phase place, read the data that are written into this memory storage, wherein, these are a plurality of to read phase place for read the phase place that reads of the data that are stored in this memory storage with respect to a reference signal (reference signal), and this reference signal is a gating signal (strobesignal) or a clock signal;
Step 30: read phase place corresponding to this a plurality of one of reads in the middle of the phase place, check that data that this read step reads correspond to the correctness of this preassigned pattern;
Step 40: check the check result of step according to this, a plurality ofly determine a preferable phase place in the middle of reading phase place in this; And
Step 50: according to this preferable phase place, select at least one standard delay unit (standard delay cell of at least one delay chain (delaychain) 220 with multiplexer 230 multiplex (MUX)s, in Fig. 2 be 15 standard delay unit 101,102,103 ..., 15) in the middle of one of the output terminal of standard delay unit or input end signal as the trigger pip TRIG that latchs the data stream that (latch) this memory storage exports, to read the data that are stored in this memory storage in this optimum phase.
At least one preassigned pattern in the step 10 is a sexadecimal number 5 or a, i.e. binary number 0101 or 1010.In present embodiment, at least one preassigned pattern of step 10 is a sexadecimal number 5a or a5, i.e. binary number 01011010 or 10100101.For example repeat to carry out step 10 four times and can write 5a5a5a5a, a5a5a5a5 to address 0,1 respectively.Then step 20 can at 16 phase place n (n=15,14 ..., 0, clock CK=32-(n/2) * 4+2+1 in its correspondence) 0,1 data that read at least one preassigned pattern that is written into this memory storage from the address.And whether step 30 reexamines data that step 20 reads and coincide with at least one the preassigned pattern 5a or the a5 of step 10, its check result can be stored in two-dimensional array Result[m] [n] (m=3,2,1,0, correspond respectively to step 10 and repeat a secondary data 5a or an a5 in the middle of four times), check result Result[m wherein] [n]=1 representative data is correct, check result Result[m] [n]=0 representative data is wrong.Step 40 is for determining this preferable phase place of intermediate phase conduct in the continuous phase that reads no read error in the middle of the phase place at these 16.And be positioned at the centre that puts in order or the phase place of approximate centre in the middle of the continuous phase of this intermediate phase for these no read errors.For example when corresponding phase place n=15,14 ..., 0 check result Result[m] the sequence Result[m of [n]] [15:0]=0000111110000000, then be positioned at the centre that puts in order or the phase place n=9 of approximate centre in the middle of the continuous phase n=11,10,9,8,7 of these no read errors and be this optimum phase Best_phase.Corresponding computing definable starting point start_pt is sequence Result[m] 11 begin appearance place n=11 in the middle of [15:0], and definition end point end_pt is sequence Result[m] [15:0] central 110 begins appearance place n=7, so optimum phase Best_phase=start_pt+ (end_pt-start_pt)/2=(start_pt+end_pt)/2=(11+7)/2=9.
In the present embodiment, this memory storage is a dynamic RAM, and this reference signal is a DQS signal.The DQS signal is converted to a trigger pip TD0 through a comparer.And the multiplex (MUX) that control module 210 is exported selects the state of signal SEL can be corresponding to these a plurality of phase places that read, also corresponding to trigger pip TD0 and the trigger pip TD1, the TD2 that postpone back, TD3 ..., TD15, so step 50 be the optimum phase of selecting signal SEL representative according to the multiplex (MUX) by trigger pip TD0, TD1, TD2, TD3 ..., TD15 selects one of them as trigger pip TRIG.
Please once again with reference to figure 2.Present embodiment is providing said method simultaneously, also provide a kind of accordingly a memory storage (not being shown in relevant indicators) is read the circuit of phase place from normal moveout correction, in the present embodiment, this circuit includes: a control module 210 (being a numerical digit signal processor or a firmware in the present embodiment), be coupled to this memory storage, be used for determining an optimum phase in the middle of reading phase place, and export a multiplex (MUX) according to this preferable phase place and select signal SEL a plurality of; One delay chain 220, be used for producing at least one inhibit signal (be aforementioned trigger pip TD0, TD1, TD2, TD3 ..., TD15); An and multiplexer 230, be coupled to control module 210 and delay chain 220, be used for selecting signal SEL multiplex (MUX) in the middle of the inhibit signal that delay chain 220 is produced to select (multiplexing) inhibit signal, to latch the data stream that (latch) this memory storage is exported according to the multiplex (MUX).In the present embodiment, multiplexer 230 can also select signal SEL multiplex (MUX) to select the output signal TRIG of the input signal TD9 of delay chain 220 as multiplexer 230 according to the multiplex (MUX).
The above only is the present invention's preferred embodiment, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (9)
1. one kind is read the method for phase correction to a memory storage, and the method comprising the steps of:
This memory storage is write the data of at least one preassigned pattern;
With a phase place in the middle of a plurality of phase places, read the data of this memory storage;
The data that comparison is read and the data of this preassigned pattern; And
According to this comparative result, in the middle of these a plurality of phase places, read in the correct phase place and determine one to read phase place.
2. method according to claim 1, wherein, described a plurality of phase places are with respect to a reference signal.
3. as the method as described in the claim 2, wherein, described reference signal is a gating signal or a clock signal.
4. as the method as described in the claim 2, wherein, described memory storage is a dynamic RAM DRAM, and described reference signal is a DQS signal.
5. method according to claim 1, wherein, at least one preassigned pattern in the said write step is a sexadecimal number 5 or a or both combinations.
6. method according to claim 1, wherein, whether the described data that read of described comparison step bit comparison are identical with the data of described preassigned pattern.
7. method according to claim 1, wherein, described deciding step is for reading described a plurality of reading the phase place that is positioned at centre or approximate centre in the correct continuous phase in the middle of the phase place and read phase place as this, wherein choose during for odd number and be positioned at Centromedian phase place, choose during when the continuous phase number of no read error and be positioned at approximate Centromedian phase place for even number when the continuous phase number of no read error.
8. circuit, in order to memory storage is read phase correction, this circuit includes:
One control module, be coupled to this memory storage, be used for this memory storage is write the data of at least one preassigned pattern, read the data of this memory storage with a phase place in the middle of a plurality of phase places, the data that comparison is read and the data of this preassigned pattern, in the middle of a plurality of phase places, determine one to read phase place according to this comparative result, and read phase place output one according to this and select signal;
One delay chain is used for producing a plurality of phase signals; And
One multiplexer is coupled to this control module and this delay chain, is used for according to this selection signal, selects output one to read phase place in the middle of a plurality of phase places.
9. as the circuit as described in the claim 8, wherein, this control module is a processor or a firmware.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101243430A CN100508066C (en) | 2003-12-30 | 2003-12-30 | Method and apparatus for read phase correction for memory devices |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2003101243430A CN100508066C (en) | 2003-12-30 | 2003-12-30 | Method and apparatus for read phase correction for memory devices |
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| CN1635578A CN1635578A (en) | 2005-07-06 |
| CN100508066C true CN100508066C (en) | 2009-07-01 |
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| CNB2003101243430A Expired - Lifetime CN100508066C (en) | 2003-12-30 | 2003-12-30 | Method and apparatus for read phase correction for memory devices |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527164B (en) * | 2008-03-07 | 2011-11-09 | 瑞昱半导体股份有限公司 | Data reading circuit and data reading method |
| CN102081971A (en) * | 2009-11-27 | 2011-06-01 | 晨星软件研发(深圳)有限公司 | Method for adjusting memory signal phases |
| CN103812504B (en) * | 2012-11-06 | 2017-03-01 | 瑞昱半导体股份有限公司 | Phase correction device and phase correction method |
| CN104298627B (en) * | 2013-07-16 | 2017-08-04 | 晨星半导体股份有限公司 | Dynamic phase tracking method of memory signal and related control circuit thereof |
| CN104425019B (en) * | 2013-08-23 | 2018-07-06 | 慧荣科技股份有限公司 | Method for accessing memory cell in flash memory and device using the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066868A (en) * | 1990-08-13 | 1991-11-19 | Thomson Consumer Electronics, Inc. | Apparatus for generating phase shifted clock signals |
| US5245637A (en) * | 1991-12-30 | 1993-09-14 | International Business Machines Corporation | Phase and frequency adjustable digital phase lock logic system |
| CN1237041A (en) * | 1998-05-22 | 1999-12-01 | 南方通信(惠州)实业有限公司 | High-precision digital phase discriminator |
| CN1268698A (en) * | 1999-03-29 | 2000-10-04 | 日本电气株式会社 | Data processor and data processing method |
-
2003
- 2003-12-30 CN CNB2003101243430A patent/CN100508066C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066868A (en) * | 1990-08-13 | 1991-11-19 | Thomson Consumer Electronics, Inc. | Apparatus for generating phase shifted clock signals |
| US5245637A (en) * | 1991-12-30 | 1993-09-14 | International Business Machines Corporation | Phase and frequency adjustable digital phase lock logic system |
| CN1237041A (en) * | 1998-05-22 | 1999-12-01 | 南方通信(惠州)实业有限公司 | High-precision digital phase discriminator |
| CN1268698A (en) * | 1999-03-29 | 2000-10-04 | 日本电气株式会社 | Data processor and data processing method |
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