CN100499135C - Active element array substrate - Google Patents

Abstract

An active element array substrate comprises a substrate, a plurality of first wires, a plurality of second wires, a plurality of active elements, a plurality of pixel electrodes and a plurality of sharing wires, wherein the first wires and the second wires are arranged on the substrate, and a plurality of pixel areas are divided on the substrate. The active elements are respectively arranged in the pixel areas and are electrically connected to the corresponding first wirings and the first wirings. The pixel electrodes are respectively arranged in the pixel areas, and each pixel electrode is electrically connected to the corresponding active element. The shared wirings are approximately parallel to the first wirings, and the shared wirings and the first wirings are alternately arranged on the substrate. Each shared wiring has a plurality of branches extending outward from both side edges, and the branches are respectively overlapped with the second wirings.

Description

Active element array substrate

technical field

The invention relates to an element array substrate, and in particular to an active element array substrate.

Background technique

Due to the increasing demand for displays, the industry is fully committed to the development of related displays. Among them, the cathode ray tube (cathode ray tube, referred to as CRT) has been monopolizing the display market for many years because of its excellent display quality and technological maturity. However, due to the rise of the concept of green environmental protection, the characteristics of large energy consumption and large radiation, and the limited space for flat products, it cannot meet the market's requirements for lightness, thinness, shortness, smallness, beauty and low consumption. Power Market Trends. Therefore, thin film transistor liquid crystal displays (thin film transistor liquid crystal displays, referred to as TFT-LCDs), which have superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation, have gradually become the mainstream of the market.

FIG. 1 is a schematic top view of a known thin film transistor array substrate. Referring to FIG. 1 , the known thin film transistor array substrate 100 includes a substrate 110 , a plurality of scanning wires 120 , a plurality of data wires 130 , a plurality of shared wires 140 , a plurality of thin film transistors 150 and a plurality of pixel electrodes 160 . Wherein, the scan wires 120 and the data wires 130 are disposed on the substrate 100 , and define a plurality of pixel regions 110 a on the substrate 110 . The thin film transistors 150 are respectively disposed in the pixel regions 110 a, and each thin film transistor 150 is electrically connected to the corresponding scanning wiring 120 and data wiring 130 . The pixel electrodes 160 are respectively disposed in the pixel regions 110 a, and each pixel electrode 160 is electrically connected to the corresponding thin film transistor 150 .

The shared wires 140 are substantially parallel to the scan wires 120 , and the shared wires 140 and the scan wires 120 are arranged alternately on the substrate 110 . Each shared wire 140 has a plurality of branches 140a extending outward from two edges, wherein the branches 140a are respectively adjacent to the data wires 130 . In addition, since the branches 140a partially overlap with the edges of the pixel electrodes 160 , the branches 140a can not only increase the storage capacitance Cst, but also cover the abnormal alignment regions between the pixel electrodes 160 and the data lines 130 . However, because the branches 140a have the limitation of the minimum line width and the consideration of alignment accuracy of each layer in the known thin film transistor array substrate 100, the aperture ratio of the known thin film transistor array substrate 100 cannot be further increased.

Contents of the invention

In view of the above circumstances, the purpose of the present invention is to provide an active element array substrate to increase the aperture ratio.

In view of the above purpose or other purposes, the present invention proposes an active element array substrate, which includes a substrate, a plurality of first wirings, a plurality of second wirings, a plurality of active elements, a plurality of pixel electrodes and a plurality of The shared wires, wherein the first wires and the second wires are arranged on the substrate, and divide a plurality of pixel regions on the substrate. The active elements are respectively arranged in the pixel regions, and each active element is electrically connected to the corresponding first wiring and the first wiring. The pixel electrodes are respectively arranged in the pixel regions, and each pixel electrode is electrically connected to the corresponding active element. The shared lines are parallel to the first lines, and the shared lines and the first lines are arranged alternately on the substrate. Each shared wiring has a plurality of branches extending outward from the edges of both sides, and these branches overlap with the second wirings respectively.

According to an embodiment of the present invention, the first wirings may be scan wirings, and the second wirings may be data wirings.

According to an embodiment of the present invention, the branches may be respectively located under the second wires.

According to an embodiment of the present invention, the branches may be respectively located above the second wires.

According to an embodiment of the present invention, the first wires and the shared wires may belong to the same film layer.

According to an embodiment of the present invention, the branches may partially overlap with the edges of the pixel electrodes respectively.

According to an embodiment of the present invention, each active element may be a thin film transistor or a diode. In addition, the thin film transistor may be a thin film transistor with a bottom gate or a thin film transistor with a top gate.

According to an embodiment of the present invention, the material of the pixel electrode can be indium tin oxide (indium tin oxide) (hereinafter referred to as ITO), indium zinc oxide (indium zinc oxide) (hereinafter referred to as IZO) or zinc aluminum oxide (aluminum zinc oxide). oxide) (hereinafter referred to as AZO).

Based on the above, the present invention overlaps the branch of the shared wiring with the second wiring, so the active device array substrate of the present invention can have a higher aperture ratio and a higher storage capacitance Cst.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a known TFT array substrate.

FIG. 2 is a top view of an active device array substrate according to an embodiment of the present invention.

Description of main component marking:

100: known thin film transistor array substrate

110, 210: Substrate

110a, 210a: pixel area

120: Scan wiring

130: data wiring

140, 240: shared wiring

140a, 240a: branches

150: thin film transistor

160, 260: pixel electrode

200: active element array substrate

220: first wiring

230: Second wiring

250: active components

Detailed ways

FIG. 2 is a top view of an active element array substrate according to a preferred embodiment of the present invention. Please refer to FIG. 2, the active element array substrate 200 of this embodiment includes a substrate 210, a plurality of first wirings 220, a plurality of second wirings 230, a plurality of shared wirings 240, a plurality of active elements 250 and a plurality of pixel electrodes 260 . Wherein, the first wires 220 and the second wires 230 are disposed on the substrate 210 and define a plurality of pixel regions 210 a on the substrate 210 . In addition, these pixel regions 210a are arranged in an array. In this embodiment, the first wires 220 are scan wires, and the second wires 230 are data wires. However, in another embodiment, the first wires 220 may be data wires, and the second wires 230 may be scan wires. In addition, the substrate 210 may be a glass substrate, a quartz substrate or other transparent substrates.

The shared wires 240 are substantially parallel to the first wires 220 , and the shared wires 240 and the first wires 220 are alternately disposed on the substrate 210 . In addition, the first wires 220 and the shared wires 240 may belong to the same film layer. In addition, the active elements 250 are respectively disposed in the pixel regions 210 a, and each active element 250 is electrically connected to the corresponding scanning wiring 220 and data wiring 230 . For example, these active elements 250 may be thin film transistors, diodes or other suitable active elements. In this embodiment, the active devices 250 are thin film transistors, and the active devices 250 are thin film transistors with bottom gates. However, these active elements 250 may also be TFTs with top gates.

The pixel electrodes 260 are respectively disposed in the pixel regions 210 a, and each pixel electrode 260 is electrically connected to the corresponding active element 250 . In addition, the material of the pixel electrode 260 can be indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO) or other transparent conductor materials. It should be noted that each shared wiring 240 has a plurality of branches 240a extending outward from the two side edges, and these branches 240a overlap with the second wirings 230 respectively. Since the branches 240 a overlap with the second wires 230 respectively, the active device array substrate 200 can have a higher storage capacitance Cst.

In more detail, the branches 240a may be located above or below the second wires 230 . For example, when the active elements 250 are TFTs with bottom gates, the branches 240 a are located below the second wiring 230 (data wiring). Likewise, when the active elements 250 are TFTs with top gates, the branches 240a are located above the second wiring 230 (data wiring). It is worth mentioning that the branches 240a may partially overlap with the edges of the pixel electrodes 260 respectively. In other words, the branches 240a can also shield the abnormal alignment regions between the pixel electrodes 260 and the second wirings 230 .

It should be noted that since the branch 240 a of the shared wire 240 overlaps with the second wires 230 , the RC load of the second wire 230 also increases. Compared with the known technology, in the case of satisfying the maximum RC load of the driver IC, the active element array substrate 200 of the present invention can have a higher aperture ratio, a higher storage capacitance value Cst, and shield each pixel electrode 260 from these Advantages such as an alignment abnormal region between the second wires 230 .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (10)

1. active elements array substrates is characterized in that comprising:

Substrate;

Many first distributions are arranged on this substrate;

Many second distributions are arranged on this substrate, and above-mentioned these second distributions and above-mentioned these first distributions mark off most pixel regions on this substrate;

A plurality of active elements are arranged at respectively in above-mentioned these pixel regions, and respectively this active element is electrically connected to this first distribution and this second distribution of correspondence;

A plurality of pixel electrodes are arranged at respectively in above-mentioned these pixel regions, and respectively this pixel electrode is electrically connected to this active element of correspondence; And

Many shared wiring, parallel with above-mentioned these first distributions, and above-mentioned these shared wiring and above-mentioned these first distributions are arranged alternately on this substrate, wherein respectively this shared wiring have from both sides of the edge stretch out more than bar branch, and above-mentioned these branches are overlapping with above-mentioned these second distributions respectively.

2. the active elements array substrates according to claim 1 it is characterized in that above-mentioned these first distributions are scan wiring, and above-mentioned these second distributions is data wiring.

3. the active elements array substrates according to claim 2 is characterized in that above-mentioned these branches lay respectively at above-mentioned these second distribution belows.

4. the active elements array substrates according to claim 2 is characterized in that above-mentioned these branches lay respectively at above-mentioned these second distribution tops.

5. the active elements array substrates according to claim 2 is characterized in that above-mentioned these first distributions and above-mentioned these shared wiring belong to same rete.

6. the active elements array substrates according to claim 1 is characterized in that above-mentioned these branches overlap with above-mentioned these pixel electrode edges respectively.

7. the active elements array substrates according to claim 1 is characterized in that respectively this active element is thin-film transistor or diode.

8. the active elements array substrates according to claim 7 is characterized in that this thin-film transistor is the thin-film transistor with bottom grid.

9. the active elements array substrates according to claim 7 is characterized in that this thin-film transistor is the thin-film transistor with top grid.

10. the active elements array substrates according to claim 1 is characterized in that the material of above-mentioned these pixel electrodes comprises indium tin oxide, indium-zinc oxide or Zinc-aluminium.

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