CN100499125C - Semiconductor device - Google Patents

Abstract

The present invention provides a highly reliable semiconductor device capable of providing a semiconductor device under a pad. The semiconductor device comprises: a semiconductor layer (10), having a device formation region (10A) and a device isolation region (20) arranged around the device formation region (10A); a device (30), formed in the device formation region ( 10A); interlayer insulating layer (60), arranged on the top of the semiconductor layer (10); and electrode pads (62), arranged on the top of the insulating layer (60), and the planar shape is to have a short side and a rectangle with a long side, and at least partly overlaps with the device (30) in a plan view; wherein, in the semiconductor layer (10), from the vertical lower side of the short side of the electrode pad (62) toward The outer defined range is the device keep-out zone (12).

Description

Semiconductor device

technical field

The present invention relates to semiconductor devices.

Background technique

Conventionally, when semiconductor devices such as MOS transistors were arranged under pads (pad layers), the characteristics of semiconductor devices such as MOS transistors were often damaged due to stress during soldering. A portion and a region in which a semiconductor device is formed are formed. However, with the refinement and integration of semiconductor chips in recent years, it is strongly desired to arrange semiconductor devices under pads. An example of such a technique is disclosed in JP-A-2002-319587.

Patent Document 1: JP-A-2002-319587.

Contents of the invention

An object of the present invention is to provide a highly reliable semiconductor device in which a semiconductor device can be provided under an electrode pad.

(1) The semiconductor device of the present invention includes: a semiconductor layer having a device formation region and a device isolation region disposed around the device formation region; a device formed in the device formation region; a layer disposed on the semiconductor layer An interlayer insulating layer; and an electrode pad that overlaps with a part of the device in a plan view, the electrode pad is an electrode pad that is arranged on the interlayer insulating layer and has a planar shape of a rectangle with short sides and long sides; wherein , in the semiconductor layer, a predetermined range that is vertically lower than the short side of the electrode pad and faces outward is a device forbidden area.

In the semiconductor device of the present invention, at least a part of the semiconductor layer below the electrode pad is a device formation region, and a device prohibition region is provided on a predetermined region positioned outward from the short side of the electrode pad. In a predetermined region located outward from the short side of the electrode pad, strain is easily generated due to the formation of the electrode pad, and stress is easily induced. Therefore, cracks are likely to occur in the interlayer insulating layer arranged above this region, and, for example, when a semiconductor device such as a MOS transistor is provided in this region, it may cause deterioration of the characteristics of the MOS transistor. Therefore, in the semiconductor device of the present invention, the problem is avoided by making the predetermined region a device prohibition region, and the device formation region is provided on the semiconductor layer below the electrode pad, even if the device formation region is placed under the electrode pad. The semiconductor device is placed where there is no problem with setting the semiconductor device. In other words, according to the present invention, semiconductor devices are positively arranged under electrode pads where reliability is not affected even if semiconductor devices are installed, and semiconductor devices are not arranged at places where reliability is considered to be impaired. devices, whereby it is possible to provide a semiconductor device that strives to improve refinement and reliability.

In the present invention, the so-called device region refers to a region where various devices such as MIS transistors, diodes and resistors are formed. In addition, in the present invention, when referring to a specific B layer (hereinafter referred to as "B layer") provided on a specific A layer (hereinafter referred to as "A layer"), it is included on the A layer. The case of directly installing the B layer and the case of installing the B layer on top of the A layer via another layer.

The semiconductor device related to the present invention can employ the following embodiments.

(2) In the semiconductor device related to the present invention, the device forbidden region may be a range having a distance of 1.0 μm to 2.5 μm from vertically below the short side of the electrode pad toward the outside.

(3) In the semiconductor device of the present invention, a passivation layer is included, the passivation layer is located above the electrode pad, and has an opening that exposes at least a part of the electrode pad, wherein the device forbidden area can be There is a range of a distance corresponding to the film thickness of the passivation layer from vertically below the short side of the electrode pad toward the outside.

(4) In the semiconductor device related to the present invention, a protrusion provided on the opening may be included.

(5) A semiconductor device related to the present invention, comprising: a semiconductor layer having a device formation region and a device isolation region disposed around the device formation region; a device formed in the device formation region; a device formed in the semiconductor layer the upper interlayer insulating layer; and an electrode pad disposed above the interlayer insulating layer and overlapping with the device in plan view; wherein, in the semiconductor layer, vertically from the end of the electrode pad The specified range from below towards the outside is the device keep-out zone.

In the semiconductor device according to the present invention, the semiconductor layer located under the electrode pad is the device region, and the forbidden region is provided on a predetermined region directed outward from the end of the electrode pad. In other words, according to the present invention, the semiconductor device described above has the same advantages, and the semiconductor device is positively arranged under the electrode pad at a place where reliability will not be affected even if the semiconductor device is installed, and it is considered that By not arranging semiconductor devices where reliability is compromised, it is possible to provide a semiconductor device that seeks to improve the degree of refinement and reliability.

(6) In the semiconductor device related to the present invention, the device forbidden region is a range having a distance of 1.0 μm to 2.5 μm from vertically below the end of the electrode toward the outside.

(7) In the semiconductor device related to the present invention, further comprising a passivation layer located above the electrode pad and having an opening exposing at least a part of the electrode pad; wherein the device prohibits The region may be a range having a distance corresponding to the film thickness of the passivation layer from below the end of the electrode pad toward the outside.

(8) In the semiconductor device according to the present invention, a protrusion provided at the opening may be further included.

(9) In the semiconductor device related to the present invention, the device may be a transistor.

(10) In the semiconductor device related to the present invention, the device keepout region may be a keepout region of a low-voltage drive transistor (low-voltage drive transistor).

(11) In the semiconductor device related to the present invention, a high-voltage transistor may be provided in the device keepout region.

Description of drawings

FIG. 1 is a schematic diagram illustrating a semiconductor device related to a first embodiment.

FIG. 2 is a schematic diagram illustrating a semiconductor device related to the first embodiment.

FIG. 3 is a schematic diagram illustrating a semiconductor device related to the first embodiment.

FIG. 4 is a schematic diagram illustrating a semiconductor device related to the second embodiment.

FIG. 5 is a schematic diagram illustrating a semiconductor device according to a modification example of the first and second embodiments.

FIG. 6 is a schematic diagram illustrating a semiconductor device according to a modification example of the first and second embodiments.

Detailed ways

An example of an embodiment of the present invention will be described below with reference to the drawings.

1. The first embodiment

1 is a cross-sectional view schematically showing a semiconductor device according to this embodiment, and FIG. 2 is a plan view schematically showing the relationship between the shape of an electrode pad and a forbidden region in the semiconductor device according to this embodiment. FIG. 3 is a plan view for explaining the device formation region 10A, and the cross-section in FIG. 1 is a cross-sectional view taken along line X-X in FIG. 2 .

As shown in FIG. 1 , the semiconductor device related to this embodiment has a semiconductor layer 10 . As the semiconductor layer 10, a single-crystal silicon substrate is used. The semiconductor layer (SOI: Silicon Insulator: silicon-on-insulator) is provided on an insulating layer, and the semiconductor layer is a substrate of a silicon layer, a germanium layer, and a silicon germanium layer.

A device separation insulating layer 20 is provided on the semiconductor layer 10 . The device separation insulating layer 20 may be formed by an STI method, a LOCOS method, and a semi-buried LOCOS method. In addition, the device isolation insulating layer 20 formed by the STI method is shown in FIG. 1 . By providing the device separation insulating layer 20 in this way, the device formation region 10A and the device prohibition region 12 where devices are formed can be defined. The device formation region 10A will be described later, and is a region provided under the electrode pads. The device forbidden region 12 is a gray region in FIG. 2 , and is a region within a predetermined range from the end of the electrode pad toward the outside of the semiconductor layer 10 , and this region will also be described later. In addition, the semiconductor device related to the present embodiment also provides the device formation region 10B outside the device forbidden region 12 .

In the device formation region 10A, a low-voltage-driven MIS (Metal Insulator Semiconductor: Metal Insulator Semiconductor) transistor 30 with no insulating layer provided on the compensation region is provided. Also, in the device formation region 10B, the MIS transistor 40 is provided in the same manner as in the device formation region 10A. The MIS transistor 30 includes: a gate insulating layer 32 , a gate electrode 34 provided on the gate insulating layer 32 , and an impurity region (doped region) 36 provided on the semiconductor layer 10 . The impurity region 36 functions as a source region or a drain region. The MIS transistor 40 has the same structure as the MIS transistor 30 , including a gate insulating layer 42 , a gate electrode 44 and an impurity region 46 , and is a low-voltage driven transistor without an insulating layer on the compensation region. Note that the device formation region 10A in the present invention is a region surrounded by the device isolation insulating layer 20 in plan view as shown in FIG.

An interlayer insulating layer 50 and an interlayer insulating layer 60 provided to cover the MIS transistors 30 and 40 are provided in this order on the upper surfaces of the MIS transistors 30 and 40 . Known general materials can be used for the interlayer insulating layer 50 and the interlayer insulating layer 60 . A wiring layer 52 having a predetermined pattern is provided on the interlayer insulating layer 50 , and the wiring layer 52 is electrically connected to the impurity region 36 of the MIS transistor 30 through a contact layer 54 .

An electrode pad 62 is provided on the interlayer insulating layer 60 , and the electrode pad 62 can be electrically connected to the wiring layer 52 through a contact layer 64 . The electrode pad 62 can be formed of metal such as aluminum or copper.

As shown in FIG. 1 , the semiconductor device according to this embodiment further includes a passivation layer 70 , and an opening 72 exposing at least a part of the electrode pad 62 is formed in the passivation layer 70 . The opening 72 can also expose only the central area of the electrode pad 62 as shown in FIGS. 1 and 2 . That is, the passivation layer 70 may be formed to cover the peripheral portion of the electrode pad 62 . The passivation layer may be formed using, for example, SiO ₂ , SiN, polyimide resin, or the like. In addition, in the semiconductor device according to the present embodiment, the electrode pad includes the region where the opening 72 is provided and is wider than the wiring portion.

The semiconductor device related to the present embodiment is provided with the protrusion 80 at least in the opening 72 . That is, the raised portion 80 is provided on the exposed surface of the electrode pad 62 . In the semiconductor device related to the present embodiment, the case where the protruding portion 80 is formed so as to reach on the passivation layer 70 is illustrated. The protruding part 80 can be formed in one or more layers, and can be formed of metals such as gold, nickel or copper, and the shape of the protruding part is not particularly limited, and can also be formed in a rectangle (including square and rectangle) or a circle. In addition, the outer shape of the protrusion 80 may be smaller than that of the electrode pad 62 . In this case, the raised portion 80 may be formed only in a region overlapping with the electrode pad 62 .

In addition, although not shown, a barrier layer may be provided on the lowermost layer of the protrusion 80 . The barrier layer is used to prevent the diffusion of both the electrode pad 62 and the protrusion 80 . The barrier layer may be formed in one or more layers. The barrier layer can also be formed by sputtering. In addition, the barrier layer may also have a function of improving the adhesion between the electrode pad 62 and the protrusion 80 . The barrier layer may also have a titanium tungsten (TiW) layer. In the case of a multilayer structure, the uppermost surface of the barrier layer may be a metal layer (for example, an Au layer) for electroplating and power supply on which the protrusions 80 are deposited.

Next, the device keepout area 12 will be described. As described above, the device forbidden region 12 is a region of the semiconductor layer 10 extending from the end of the electrode pad 62 vertically downward toward the outside, and is a region within a predetermined range. A device formation region is prohibited from being arranged on the device prohibited region 12 .

The range of the device forbidden region 12 can be defined as a range having a distance corresponding to the film thickness of the passivation layer 70 from the end of the electrode pad 62 toward the outside (the side opposite to the opening 72 ). For example, the distance from the end of the electrode pad 62 toward the outside can be in a range of 1.0 μm to 2.5 μm. The reason for defining the range of the forbidden area 12 in this way is as follows.

First, the provision of the electrode pad 62 causes stress on the interlayer insulating layer 60 where the end portion of the electrode pad 62 is located. Then, as shown in FIG. 1 , continuous stress caused by the internal stress of the protrusion 80 is applied to the interlayer insulating layer due to the provision of the protrusion 80 already provided on the electrode pad 62 . The interlayer insulating layers 50, 60 are affected by these stresses, and tend to generate cracks from the locations where these stresses are generated (the ends of the electrode pads 62). Such cracks tend to reach the lowermost interlayer insulating layer, deteriorating the characteristics of semiconductor devices disposed on this region. For example, if an MIS transistor is provided, the gate insulating layer and the like will be deteriorated, causing a leakage current.

In addition, the passivation layer 70 is not arranged on the surfaces whose upper surfaces have the same height, of course, different step differences will be produced with the different shapes of the electrode pads 62 . Due to this step difference, as described above, for example, in the case of COF mounting, when the connection wire (lead wire) provided on the film is connected to the protrusion 80, it is easy to cause strain concentration due to contact and bonding. This becomes a cause of cracks in the interlayer insulating layers 50 and 60 , and this step is likely to occur at a position that is approximately equivalent to the film thickness of the passivation layer 70 toward the outside from the end of the electrode pad 62 . This is the reason for specifying the range of the device keepout region 12 by taking the above-mentioned problems into consideration.

In the semiconductor device according to this embodiment, the semiconductor layer below the electrode pad 62 is the device formation region 10A, and the device prohibition region 12 is provided on a region defined outward from the end of the electrode pad 62 . Since strain and stress are easily generated in a predetermined region from the end of the electrode pad 62 to the outside, cracks are likely to occur on the interlayer insulating layers 50 and 60 disposed above the device prohibition region 12, for example, in this region. When a semiconductor device such as a MOS transistor is provided, it may cause deterioration of the characteristics of the MOS transistor. Therefore, in the semiconductor device according to the present embodiment, the above-mentioned problems can be avoided by setting the device keepout region 12 within the predetermined range. In addition, the semiconductor layer 10 located under the electrode pad 62 is used as the device formation region 10A, and the semiconductor device is arranged in a place where there is no problem even if the semiconductor device is provided under the electrode pad 62 . That is, according to this embodiment, the semiconductor device is positively arranged under the electrode pad, even if the semiconductor device is installed, the reliability will not be affected, and the semiconductor device is not arranged at the place where the reliability is considered to be damaged, thereby providing A semiconductor device capable of fine-tuning the map while maintaining reliability.

In addition, when the contact layer constituting the gate electrode 34 is used as a wiring for connecting to other devices such as the MIS transistor 40, a part of the contact layer for this wiring may be formed on the device prohibition region 12.

2. The second embodiment

Next, a second embodiment of the present invention will be described with reference to FIG. 4 . 4 is a cross-sectional view schematically showing a semiconductor device according to a second embodiment of the present invention. In the semiconductor device related to the second embodiment, the point that the semiconductor device is provided in the device forbidden region 12 is an example different from the semiconductor device related to the first embodiment. In the following description, differences from the semiconductor device according to the first embodiment will be described.

The semiconductor device related to the second embodiment has, as shown in FIG. 4 , a device formation region 10A and a device prohibition region 12 provided around it. In the semiconductor device according to this embodiment, although not shown in FIG. 4 , like the semiconductor device according to the first embodiment, device formation region 10B is also formed outside device forbidden region 12 .

In the semiconductor device related to the present embodiment, a high-voltage-resistant MOS transistor is provided on the device forbidden region 12 . Specifically, a MOS transistor 100 having a LOCOS compensation structure is provided. The MOS transistor 100 is disposed in the semiconductor layer 10, and has: a compensation insulating layer 22 for attenuating an electric field; a gate insulating layer 102 disposed on the semiconductor layer 10; a part of the compensation insulating layer 22 and the gate insulating layer 102 The gate electrode 104 on the gate electrode 104, and the impurity region 106 as a source region or a drain region disposed on the semiconductor layer outside the gate electrode 104. A compensation impurity region 108 having the same conductivity type as the impurity region 106 and having a low doping concentration is disposed under the compensation insulating layer 22 .

In the semiconductor device according to this embodiment, a part of the constituent elements of the MOS transistor 100 is provided on the semiconductor layer 10 in the device forbidden region 12 . The end of the gate electrode 104 of the MOS transistor 100 is arranged on the compensation insulating layer 22 . That is, it was decided not to provide a structure in which the end of the gate electrode 104 is disposed on the upper surface of the semiconductor 10 via a thin insulating layer in the forbidden region 12 , the first layer of which is a conductive layer. Here, the problem in the case where the MIS transistor 30 having a structure provided on the device region is provided on the device forbidden region 12 will be described. Unlike the MOS transistor 100 , the MIS transistor 30 has a structure in which the end of the gate electrode 34 is provided on the semiconductor layer 10 . Therefore, stress is easily generated on the semiconductor layer 10 where the end portion of the gate electrode 34 is located. As described in the first embodiment, cracks are easily generated on the interlayer insulating layers 50, 60 above the device forbidden region 12, thereby easily causing film degradation. This influence tends to affect the end portion of the gate electrode 34 where stress occurs, causing deterioration of the gate insulating layer 32 . And it must cause a leakage current in the MIS transistor.

In addition, according to the semiconductor device related to the second embodiment, since the end of the gate electrode 104 is arranged on the compensation insulating layer 22 on the device forbidden area 12, the above-mentioned stress is not caused to the semiconductor layer 10, and the gate electrode 104 can be suppressed. Deterioration of the pole insulating layer 102. Therefore, as long as the semiconductor device has a predetermined structure, it can be arranged not only in the device formation region 10A provided under the electrode pad 62, but also in the device forbidden region 12, so that the level of refinement can be further improved. . This increases the number of semiconductor chips obtained from one semiconductor wafer and reduces manufacturing costs.

In addition, although in FIG. 4 , the case where the MIS transistor 100 is provided in the device forbidden region 12 is described, it is not limited thereto, and the case where a part of the configuration of the MOS transistor 100 is provided is also included. In this case, also It can be a MOS transistor with a single-sided compensation structure.

Variation

A modified example of the semiconductor device related to the first embodiment and the second embodiment will be described below with reference to FIG. 5 . The feature of this modification is that the shape of the protrusion 80 is a rectangle having short sides and long sides. FIG. 5 is a plan view schematically showing the positional relationship between the electrode pad 62 and the device forbidden area 12 . In addition, in the following description, only the points of difference from the semiconductor device according to the first embodiment and the second embodiment will be described.

In the semiconductor device according to this modified example, as shown in FIGS. 1 and 4 , a protrusion 80 is provided on the opening 72 in the electrode pad 62 . In this modified example, the electrode pad 62 has a rectangular shape. Furthermore, an opening 72 is provided in a part of the electrode pad 62 . A raised portion 80 is provided on the opening 72 . The protruding portion 80 has a smaller pattern than the electrode pad 62, and as shown in FIG. 5, the protruding portion 80 is preferably disposed inside the electrode pad when viewed from a plan view. In this modified example, the device forbidden region 12 is provided on the region from the short-side end of the electrode pad 62 toward the outside. In this manner, for example, when mounting with the TAB technique, the extension direction of the connection wire (lead wire) 13 provided on the film made of polyimide resin is along the direction of the long side of the electrode pad 62, there are the following advantages . At this time, the electrode pad 62 is in a state of tension in the direction in which the connection wires extend, and particularly strain is generated on the short sides of the electrode pad 62 . Therefore, as described above, the problem that cracks are likely to occur in the interlayer insulating layers 50 and 60 is particularly likely to occur at the ends of the short sides of the electrode pads 62 . In this modified example, by providing the device prohibition region 12 on the short side of the electrode pad 62, it is possible to surely prohibit the semiconductor device from being disposed at a place where reliability is low. In addition, because the device forbidden region 12 is not provided on the semiconductor layer below the long side of the electrode pad 62, the semiconductor device can be provided on the semiconductor layer below the long side of the electrode pad 62, and a semiconductor device with a high degree of refinement can be provided. device.

In particular, as shown in FIG. 6 , it is often urgent to form the opening 72 and the protrusion 80 in a rectangular shape with many openings 72 on the semiconductor chip 200 that has been miniaturized. In this modified example, even in a semiconductor device having such a rectangular electrode pad 62 (protrusion 80), by providing a device prohibition region 12 on an appropriate region, it is possible to provide a refined and highly reliable semiconductor device. device.

In addition, although in the above-mentioned embodiment, the case where two layers of interlayer insulating layers 50, 60 are formed and one wiring layer 52 is provided between these two layers is illustrated, it is not limited thereto, and may be Three or more (three or more) interlayer insulating layers are stacked, and wiring layers corresponding to the number of the interlayer insulating layers are provided between all the interlayer insulating layers.

The present invention is not limited to the above-mentioned embodiments, and there are various possible modifications. For example, the present invention includes substantially the same configurations as those described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and results). In addition, the present invention includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that produce the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which known techniques are added to the configurations described in the embodiments.

Explanation of reference signs

10 Semiconductor layer 10A, 10B device formation area

12 Device forbidden area 20 Device separation insulating layer

22 compensation insulation layer 30, 40 MIS transistor

32, 42 Gate insulating layer 34, 44 Gate electrode

36, 46 impurity region 50 interlayer insulating layer

52 Wiring layer 60 Interlayer insulating layer

62 Electrode Pads 62 Electrode Pads

70 passivation layer 72 opening

80 bumps 100 MIS transistors

102 Gate insulating layer 104 Gate electrode

106 Impurity area 108 Compensation impurity area

Claims (9)

1. A semiconductor device, characterized in that comprising: a semiconductor layer having a device formation region and a device separation region disposed around the device formation region; a device formed in the device formation region; an interlayer insulating layer disposed on the semiconductor layer; and An electrode pad is arranged on the interlayer insulating layer, and has a planar shape of a rectangle with short sides and long sides, and the electrode pad overlaps with a part of the device in a plan view; Wherein, in the semiconductor layer, the specified range from the vertical lower side of the short side of the electrode pad toward the outside is a device forbidden area, The device forbidden area is a range having a distance of 1.0 μm to 2.5 μm from the vertical lower side of the short side of the electrode pad toward the outside. 2. A semiconductor device, characterized in that comprising: a semiconductor layer having a device formation region and a device separation region disposed around the device formation region; a device formed in the device formation region; an interlayer insulating layer disposed on the semiconductor layer; and An electrode pad is arranged on the interlayer insulating layer, and has a planar shape of a rectangle with short sides and long sides, and the electrode pad overlaps with a part of the device in a plan view; Wherein, in the semiconductor layer, the specified range from the vertical lower side of the short side of the electrode pad toward the outside is a device forbidden area, The semiconductor device also includes: a passivation layer overlying the electrode pad and having an opening exposing at least a portion of the electrode pad, Wherein, the device prohibited region is a range from the vertically below the short side of the electrode pad toward the outside with a distance equivalent to the film thickness of the passivation layer. 3 . The semiconductor device according to claim 2 , further comprising: a raised portion disposed on the opening. 4 . 4. A semiconductor device, characterized in that it comprises: a semiconductor layer having a device formation region and a device separation region disposed around the device formation region; a device formed in the device formation region; an interlayer insulating layer disposed on the semiconductor layer; and electrode pads disposed on the interlayer insulating layer and repeating the device in plan view; Wherein, in the semiconductor layer, a predetermined range from the vertically downward side of the end of the electrode pad toward the outside is a device forbidden area, The device forbidden area is a range with a distance of 1.0 μm to 2.5 μm from the vertical lower side of the electrode end toward the outside. 5. A semiconductor device, characterized in that it comprises: a semiconductor layer having a device formation region and a device separation region disposed around the device formation region; a device formed in the device formation region; an interlayer insulating layer disposed on the semiconductor layer; and electrode pads disposed on the interlayer insulating layer and repeating the device in plan view; Wherein, in the semiconductor layer, a predetermined range from the vertically downward side of the end of the electrode pad toward the outside is a device forbidden area, The semiconductor device also includes: a passivation layer overlying the electrode pad and having an opening exposing at least a portion of the electrode pad; Wherein, the device prohibited region is a range having a distance corresponding to the film thickness of the passivation layer from the bottom of the end of the electrode pad toward the outside. 6 . The semiconductor device according to claim 5 , further comprising: a raised portion disposed on the opening. 7. The semiconductor device according to any one of claims 1 to 6, wherein the device is a transistor. 8. The semiconductor device according to any one of claims 1 to 6, wherein the device keepout region is a keepout region of a low-voltage drive transistor. 9. The semiconductor device according to claim 8, wherein a high-voltage transistor is provided in the device forbidden region.

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