CN100498689C - Hardware circuit for realizing data sequencing and method - Google Patents
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Abstract
本发明公开了一种实现数据排序的硬件电路及方法，所述电路主要用于从m个数据中找出n个最大(或最小)的数据，m≥n，并且同时实现对这n个最大(或最小)的值进行大小排序。具体包括：一组寄存器，一组比较器，一组n+1选1的多路选择器，两组2选1的多路选择器，一组极值指针寄存器，一个2选1的多路选择器，一个当前采样(新采样)写指针寄存器，一个地址译码器。所述的方法和装置，采用硬件电路来实现数据的排序，此电路每个时钟可以处理一个数据，如果使用多套排序电路并行工作，排序时间还可以成倍减少，所以本电路的实时处理性强，可以满足对处理时间要求比较高的场合。
The invention discloses a hardware circuit and a method for realizing data sorting. The circuit is mainly used to find out n largest (or smallest) data from m data, m≥n, and at the same time realize the sorting of the n largest (or smallest) value to sort by size. Specifically include: a set of registers, a set of comparators, a set of n+1 to 1 multiplexers, two sets of 2 to 1 multiplexers, a set of extreme value pointer registers, and a 2 to 1 multiplexer selector, a current sample (new sample) write pointer register, and an address decoder. The method and device described above use a hardware circuit to implement data sorting. This circuit can process one data per clock. If multiple sets of sorting circuits are used to work in parallel, the sorting time can also be reduced exponentially. Therefore, the real-time processing performance of this circuit Strong, which can meet the occasions that require relatively high processing time.
Description
Technical field
The present invention relates to digital processing field, be specifically related to a kind of hardware circuit and method that realizes data sorting.
Background technology
In digital signal processing, often need sort to a series of data, such as will the size order of m data being sorted, perhaps from m data, find out the data of n maximum (or minimum), m 〉=n is to determine the priority level of these data.
Existing technology is mainly the software ordering.Though the algorithm of software ordering is a lot because the arithmetic speed of software is slower, can't requirement of real time than higher environment.Such as the base station of communication system when carrying out Cell searching, need from lot of data, find real signal, and rapidly to the portable terminal feedback information, this time interval requires very short, usually about 1ms, when sub-district bigger at radius of society or search is many, need the data volume of processing very huge, often reach 100,000 magnitude, software can't so realized the so multidata ordering of searching in the short time.
Summary of the invention
The object of the invention is to overcome the long shortcoming of software ordering spended time, uses hardware circuit to realize the ordering of data, can requirement of real time than higher occasion.
In order to realize the foregoing invention purpose, the present invention specifically is achieved in that
A kind of hardware circuit of realizing data sorting comprises:
First registers group (A), one group of comparer (B), one group of n+1 selects 1 first MUX (C), select 1 second MUX (D) for one group 2, select 1 the 3rd MUX (E) for one group 2, secondary extremal pointer register set (F), one 2 is selected 1 the 3rd MUX (EN), the 3rd current sampling write pointer register (FN), an address decoder (G); The input data are connected to first registers group (A) and comparator bank (B), are output as the output of first registers group (A) and secondary extremal pointer register set (F);
The output of described address decoder (G) is connected to the input Enable Pin of first registers group (A); The output of first registers group (A) is the input of device group (B) as a comparison; The output of comparator bank (B) is as the input of the first MUX group (C), and the output of secondary extremal pointer register set (F) is as the control end of the first MUX group (C); The output of the first MUX group (C) is as the control end of the second MUX group (D), and the 3rd current sampling write pointer register (FN) and secondary extremal pointer register set (F) are as the input end of the second MUX group (D); The output of the first MUX group (C) is as the control end of the 3rd MUX group (E) and the 4th MUX (EN), the extreme value pointer register output of secondary extremal pointer register set (F) and the output of the 3rd current sampling write pointer register (FN) is as the input of the 4th MUX (EN), the middle input end that remains the output of extreme value pointer register as the 3rd MUX group (E) of the part output of the second MUX group (D) and secondary extremal pointer register set (F); A selector switch output of the output of the 3rd MUX group (E) and the second MUX group (D) is as the input end of secondary extremal pointer register set (F); The output of the 4th MUX (EN) is as the input end of the 3rd current sampling write pointer register (FN), and the 3rd current sampling write pointer register (FN) is as the input end of address decoder (G).
Have an extra space to deposit current sampling input in first registers group (A), its memory location is specified by the 3rd current sampling write pointer register (FN).
A kind of above-mentioned hardware circuit is realized the method for data sorting, comprising:
Step 2, select the number m of data source to be found, with the working time of determining circuit be m clock;
Step 3, basis are searched value type, select the output type of the arbitrary comparer of comparator bank (B);
Step 5, each the time clockwise circuit input data;
Step 6, through stopping this circuit behind m clock, that preserves in first registers group this moment (A) is n extreme value, the interior preservation of secondary extremal pointer register set (F) be the size order of these extreme values.
In the described step 1:
First registers group (A) and comparator bank (B) degree of depth are n+1;
N+1 selects 1 the first MUX group (C), and 2 select 1 the second MUX group (D), and the degree of depth of secondary extremal pointer register set (F) is n;
2 to select the degree of depth of 1 the 3rd MUX (E) be n-1;
It is 1 that n+1 selects the width of 1 the first MUX group (C);
2 select 1 the second MUX group (D) and the 3rd MUX group (E), secondary extremal pointer register set (F), and 2 width that select 1 the 4th MUX (EN) and the 3rd current sampling write pointer register (FN) are for more than or equal to log
2(n+1) smallest positive integral.
In the described step 4:
Secondary extremal pointer register set (F) and the 3rd current sampling write pointer register (FN) will reset respectively, and the value after resetting has nothing in common with each other; When searching maximal value, first registers group (A) all is reset to its minimum value, otherwise first registers group (A) all is reset to its maximal value.
Adopt method and apparatus of the present invention, compared with prior art, it is long that the present invention has overcome software ordering spended time, can not be used for the shortcoming of the demanding occasion of real-time.The present invention uses hardware circuit to realize the ordering of data, each clock of this circuit can be handled data, present integrated circuit generally can be operated in more than the 100MHz, the time that 100,000 data are sorted is less than 1ms, if use the concurrent working of many cover ranking circuits, the ordering time can also reduce at double, so the real-time processing of this circuit is strong, can satisfy the processing time requirement than higher occasion.
Description of drawings
Fig. 1 is the synoptic diagram of a single linked list;
Fig. 2 is for rearranging Fig. 1 and removing the single linked list that obtains behind the null pointer;
Fig. 3 is one 2 and selects 1 MUX;
Fig. 4 is one 16 and selects 1 MUX;
Fig. 5 is a circuit structure block diagram of the present invention;
Fig. 6 is a specific embodiment of the present invention;
Fig. 7 is the process flow diagram of the method for the invention.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Before explanation the present invention, briefly bright to one in principle work of the present invention earlier.
The single linked list of main thought source in software data structure of this method, single linked list are a kind of structures of storage data, when visiting the data that are stored in the chained list, need one group of pointer of inquiry, and content of this group pointer is the memory location of these data.
Accompanying drawing 2 is for rearranging accompanying drawing 1 and removing the single linked list that obtains behind the null pointer.
Below some elements of using among the present invention are described the present invention in order better to explain.
Accompanying drawing 3 is one 2 and selects 1 MUX, i
0, i
1Be data-in port, s is for selecting control port, and z is an output port, and when s was 0, z was output as i
0, when s was 1, z was output as i
1
Accompanying drawing 4 is one 16 and selects 1 MUX, and i is a data-in port, and s is for selecting control port, and z is an output port.The bit wide of i is 16, and i is by i
15, i
14, i
13..., i
1, i
0Form; The bit wide of s is 4, and span is 0
-15.When the value of s was j, z was output as i
j, the span of j is 0 here
-15.If the input bit wide of a MUX is other values, it is similar that its principle of work and 16 is selected 1 MUX.Can select 1 MUX to build 16 with 2 and select 1 the MUX or the MUX of other types.
General comparer generally has two input A and B, three outputs, and whether an output judges A greater than B, judges whether A equals B for one, another judges that whether A is less than B.
The comparer of using among the present invention only needs an output, can be as required whether to judge A greater than B, also can be to judge that whether A is less than B.
Ranking circuit of the present invention is mainly used in the data of finding out n maximum (or minimum) from m data, m 〉=n, and realize simultaneously the value of this n maximum (or minimum) is carried out the size ordering.This circuit mainly is made up of following components: one group of register A, one group of comparer B, one group of n+1 selects 1 MUX C, select 1 MUX D for one group 2, select 1 MUX E for one group 2, one group of extreme value pointer register F, one 2 is selected 1 MUX EN, a current sampling (new sampling) write pointer register FN, an address decoder G.
The input of this circuit is connected to registers group A and comparator bank B, and this circuit is output as registers group A and extreme value pointer register set F.
The output of address decoder G is connected to the input Enable Pin of registers group A; The output of registers group A is the input of device group B as a comparison; The output of comparator bank B is as the input of MUX group C, and extreme value pointer register set F is as the control end of MUX group C; The output of MUX group C is as the control end of MUX group D, write pointer register FN and the extreme value pointer register set F input end as D of newly sampling; The output of MUX group C is as the control end of MUX group E, and the output of MUX group D and extreme value pointer register set F are as the input end of E; The output of MUX group E is as the input end of extreme value pointer register set F; The output of MUX group C is as the control end of MUX EN, write pointer register FN and the extreme value pointer register set F input end as EN of newly sampling; The output of MUX EN is as the input end of new sampling write pointer register FN, the input end of write pointer register FN as address decoder G of newly sampling.As shown in Figure 5.
Utilize the foregoing circuit life to carry out the method for data sorting, comprise the following steps:
The degree of depth of A and B is n+1, and the degree of depth of C, D, F is n, and the degree of depth of E is n-1, and the width of C is 1, and the width of D, E, EN, F, FN is more than or equal to log
2(n+1) smallest positive integral;
Step 2, select the number m of data source to be found, with the working time of determining circuit be m clock,
Step 3, basis are searched type, that is, search maximal value still is the output type that minimum value is selected comparer;
F and FN will be reset to 0,1,2 respectively ..., n will guarantee that they have nothing in common with each other at the value after resetting; When searching maximal value, registers group A all is reset to its minimum value, otherwise registers group A all is reset to its maximal value.
Step 5, each the time clockwise circuit of the present invention input data (sampling);
Step 6, through stopping this circuit behind m clock, preserve among the registers group A this moment is n extreme value, the interior preservation of extreme value pointer register set F be the size order of these extreme values.
Use registers group A to preserve n current extreme value, extreme value pointer register set F is used for writing down the size order of each extreme value of A, has a space to be used to write down new sampling among the registers group A in addition.
New sampling simultaneously with A in all value compare, judge according to the comparative result of extreme value pointer register set F and comparator bank B whether new sampling is a new extreme value, and judge the size order that makes new advances simultaneously.
If current sampling is not new extreme value, original size order is constant, the writing position of next current sampling in A be with current identical, otherwise have one will no longer be extreme value in the middle of original extreme value, and its memory location in A will become the writing position of next current sampling in A.
The operation that the adjustment of above-mentioned extreme value size order and current sampling writing position are judged selects 1 MUX group C, 2 to select 1 MUX group D, 2 to select that 1 MUX group E, extreme value pointer register set F, 2 select 1 MUX EN, newly sample write pointer register FN and address decoder G realizes jointly by n+1.
Be example from 1000 data without signs, to select 15 maximal values below, explain circuit of the present invention in detail.
Search the principle of minimum value and search peaked principle roughly the same.
The detailed structure of this circuit as shown in Figure 6,15 extreme value pointer registers have write down current 15 memory locations of maximal value in registers group A, pointer register F-0 writes down current peaked position, pointer register F-1 writes down the position of current second largest value, ..., pointer register F-13 writes down the position of current sub-minimum, and pointer register F-14 writes down the position of current minimum value.Though stored 15 maximal values among the storer A, be not sequential storage by size necessarily, its size order comes record by these 15 extreme value pointer registers.Have an extra space to be used for depositing current sampling input among the storer A, its memory location is specified by new sampling write pointer register FN.
Current sampling come in the back simultaneously with registers group A in 16 values compare, whether be a new extreme value to judge it.If current sampling does not have the minimum value in current 15 maximal values big, then the writing position of next sampling remains unchanged and still is the value of FN; If current sampling is bigger than in preceding 15 maximal values any one, then the writing position of next sampling is replaced with the position of minimum value in original 15 maximal values, and adjust the content of 15 extreme value pointers simultaneously, promptly adjust the size order of each data among the registers group A simultaneously.
The circuit here is embodied as: the selection control end of MUX EN is the output of C-14, and EN is input as FN and F-14, and EN is output as the input of FN, and when the C-14 value was 0, EN was output as FN, and the C-14 value is 1 o'clock, and EN is output as F-14.
After system reset, 15 pointer register F and new sampling write pointer register FN are resetted, pointer 0 is reset to 15 here, pointer 1 is reset to 14, and pointer 2 is reset to 13 ..., pointer 14 is reset to 1, the pointer FN position 0 that resets; And registers group A all is reset to 0.Shown in rightmost among Fig. 6.
16 value A-0 among the registers group A, A-1 ..., A-15 (comprising current 15 maximal values) compares with current sampling simultaneously, uses 16 comparer B-0 in the time of relatively, B-1 ..., B-15 is if current sampling is bigger than A-s, B-s is output as 1, otherwise B-s is output as 0, s=1 ... 15.Extreme value pointer register F-i has write down peaked memory location i number, i=1 ... 14, therefore can obtain the comparative result of i maximal value and current sampling by extreme value pointer register F-i.There are 15 16 to select 1 MUX among the MUX group C, with the selection control end of extreme value pointer register F-i as C-i, with B-0, B-1, ..., B-15 is as the input of C-i, and C-i is output as the extreme value of extreme value pointer register F-i correspondence and the big or small comparative result of current sampling, as shown in accompanying drawing 6.
In 15 peaked pointer registers, what extreme value pointer register F-i write down is current i peaked memory location, i=0, ..., 14, i.e. extreme value pointer 0 corresponding current maximal value, extreme value pointer 1 corresponding current second largest value, ..., the minimum value in extreme value pointer 14 corresponding current 15 maximal values.
If current sampling does not have among the registers group A minimum value in current 15 maximal values big, then the writing position of next sampling still is the value of new sampling write pointer register FN, and the content of 15 extreme value pointers also need not be adjusted; If current sampling is bigger than in current 15 maximal values among the registers group A any one, then the writing position of next sampling is the position of minimum value in original 15 maximal values, the i.e. value of extreme value pointer register F-14.
For any one the pointer register F-i in 15 extreme value pointer registers, if current sampling does not have own corresponding value big, then the content of pointer register F-i does not need change; If current sampling has just substituted original i peaked big or small position, then pointer register F-i replaces with the value of current sampling pointer, promptly replaces with the content of new sampling write pointer register FN; If current sampling is also bigger than the value of pointer register F-i-1 correspondence, then the content of pointer register F-i will replace with the content of pointer register F-i-1; Here, current sampling and i-1 peaked comparative result priority is higher than current sampling and i peaked comparative result.
In the present invention, its circuit is embodied as: with the comparative result C-i of i maximal value and the current sampling selection control end as MUX D-i, FN and F-i are as the input of D-i, and C-i is that 1 o'clock D-i is output as FN, otherwise is output as F-i; With the comparative result C-i-1 of i-1 maximal value and the current sampling selection control end as MUX E-i, D-i and F-i-1 are as the input of E-i, and C-i-1 is that 1 o'clock E-i is output as F-i-1, otherwise is output as D-i; The output of E-i is as the input of pointer F-i, as shown in accompanying drawing 6.
Therefore for pointer 0, because pointer 0 correspondence is 15 maximal values in the maximal value, do not need E-0, directly with the output of D-0 input, as shown in accompanying drawing 6 as F-0.
The writing position of current sampling is the output of new sampling write pointer register FN, and current sampling is connected to the input port of all registers among the registers group A, and each register among the registers group A all has the enable port.4-16 code translator G is sent in the output of the write pointer register FN that newly samples, by enabling of each register among the G generation registers group A.The output bit wide of address decoder G is 16, and its output signal is respectively G
15, G
14..., G
1, G
0.When the input value of 4-16 code translator was s, it exported G
sFor effectively, other are output as invalid, s=0, and 1 ... 15, G
sBe connected to the enable port of A-s, current like this sampling is just only to write in the indicated register of FN.
By top operation, after 1000 clocks, just 15 maximal values can be picked out, these values are stored among the registers group A, their memory location in registers group A is stored in 15 extreme value pointer registers, the corresponding maximal value of extreme value pointer register F-0, the corresponding second largest value of pointer storage F-1, ..., the minimum value in corresponding 15 maximal values of pointer storage F-14.
Utilize the device among Fig. 6 to search peaked process, comprise the following steps:
Step 2, according to the number 1000 of data source to be found, be 1000 clocks the working time of determining circuit,
Step 3, basis are searched type,, search the output type that maximal value is selected comparer that is;
Step 5, each the time clockwise circuit of the present invention input data (sampling);
Step 6, through stopping this circuit behind 1000 clocks, this moment, 15 maximal values were stored among the registers group A, what preserve in the extreme value pointer register set F is the size order of these extreme values.
Claims (5)
1, a kind of hardware circuit of realizing data sorting is characterized in that, comprising:
First registers group (A), one group of comparer (B), one group of n+1 selects 1 the first MUX group (C), select 1 the second MUX group (D) for one group 2, select 1 the 3rd MUX group (E) for one group 2, secondary extremal pointer register set (F), one 2 is selected 1 the 4th MUX (EN), the 3rd current sampling write pointer register (FN), an address decoder (G); The input data are connected to first registers group (A) and comparator bank (B), are output as the output of first registers group (A) and secondary extremal pointer register set (F);
The output of described address decoder (G) is connected to the input Enable Pin of first registers group (A); The output of first registers group (A) is the input of device group (B) as a comparison; The output of comparator bank (B) is as the input of the first MUX group (C), and the output of secondary extremal pointer register set (F) is as the control end of the first MUX group (C); The output of the first MUX group (C) is as the control end of the second MUX group (D), and the 3rd current sampling write pointer register (FN) and secondary extremal pointer register set (F) are as the input end of the second MUX group (D); The output of the first MUX group (C) is as the control end of the 3rd MUX group (E) and the 4th MUX (EN), the extreme value pointer register output of secondary extremal pointer register set (F) and the output of the 3rd current sampling write pointer register (FN) is as the input of the 4th MUX (EN), the middle input end that remains the output of extreme value pointer register as the 3rd MUX group (E) of the part output of the second MUX group (D) and secondary extremal pointer register set (F); A selector switch output of the output of the 3rd MUX group (E) and the second MUX group (D) is as the input end of secondary extremal pointer register set (F); The output of the 4th MUX (EN) is as the input end of the 3rd current sampling write pointer register (FN), and the 3rd current sampling write pointer register (FN) is as the input end of address decoder (G).
2, the hardware circuit of realization data sorting as claimed in claim 1 is characterized in that:
Have an extra space to deposit current sampling input in first registers group (A), its memory location is specified by the 3rd current sampling write pointer register (FN).
3, a kind of above-mentioned hardware circuit is realized the method for data sorting, it is characterized in that:
Step 1, according to will the value of searching number n, determine first registers group (A), comparator bank (B), n+1 selects 1 the first MUX group (C), 2 select 1 the second MUX group (D) and the 3rd MUX group (E), the degree of depth of secondary extremal pointer register set (F), and determine that two group 2 is selected 1 MUX group, secondary extremal pointer register set (F), 2 to select 1 the 4th MUX (EN) and the width of the 3rd current sampling write pointer register (FN);
Step 2, select the number m of data source to be found, with the working time of determining circuit be m clock;
Step 3, basis are searched value type, select the output type of the arbitrary comparer of comparator bank (B);
Step 4, first registers group that resets (A), secondary extremal pointer register set (F) and the 3rd current sampling write pointer register (FN);
Step 5, each the time clockwise circuit input data;
Step 6, through stopping this circuit behind m clock, that preserves in first registers group this moment (A) is n extreme value, the interior preservation of secondary extremal pointer register set (F) be the size order of these extreme values.
4, the method for realization data sorting as claimed in claim 3 is characterized in that, in the described step 1:
First registers group (A) and comparator bank (B) degree of depth are n+1;
N+1 selects 1 the first MUX group (C), and 2 select 1 the second MUX group (D), and the degree of depth of secondary extremal pointer register set (F) is n;
2 to select the degree of depth of 1 the 3rd MUX group (E) be n-1;
It is 1 that n+1 selects the width of 1 the first MUX group (C);
2 select 1 the second MUX group (D) and the 3rd MUX group (E), secondary extremal pointer register set (F), and 2 width that select 1 the 4th MUX (EN) and the 3rd current sampling write pointer register (FN) are for more than or equal to log
2(n+1) smallest positive integral.
5, as the method for claim 3 or 4 described realization data sortings, it is characterized in that, in the described step 4:
Secondary extremal pointer register set (F) and the 3rd current sampling write pointer register (FN) will reset respectively, and the value after resetting has nothing in common with each other; When searching maximal value, first registers group (A) all is reset to its minimum value, otherwise first registers group (A) all is reset to its maximal value.
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| CN101470553B (en) * | 2007-12-27 | 2011-11-16 | 比亚迪股份有限公司 | Data preprocessing ranking circuit and method of touch screen controller |
| CN101989847A (en) * | 2009-07-29 | 2011-03-23 | 联咏科技股份有限公司 | Numerical value judging device |
| CN102184214B (en) * | 2011-05-04 | 2013-07-31 | 东南大学 | Data grouping quick search positioning mode |
| CN105512179B (en) * | 2015-11-25 | 2017-06-09 | 中国科学院计算技术研究所 | Hard-wired data sorting device, method and data processing chip |
| CN109460210B (en) * | 2018-10-22 | 2020-11-03 | 重庆中科云从科技有限公司 | Sorting system and data processing method |
| CN111260042B (en) * | 2018-11-30 | 2022-12-02 | 上海寒武纪信息科技有限公司 | Data selector, data processing method, chip and electronic equipment |
| CN111340229B (en) * | 2018-11-30 | 2022-12-09 | 上海寒武纪信息科技有限公司 | Data selector, data processing method, chip and electronic equipment |
| CN111260043B (en) * | 2018-11-30 | 2022-12-02 | 上海寒武纪信息科技有限公司 | Data selector, data processing method, chip and electronic equipment |
| CN110780840B (en) * | 2019-10-30 | 2023-10-31 | 湖南国科微电子股份有限公司 | Method and system for realizing multipath sequencer |
| CN113094020B (en) * | 2021-03-15 | 2023-03-28 | 西安交通大学 | Hardware device and method for quickly searching maximum or minimum N values of data set |
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