CN100495922C - P-domino output latch with accelerated evaluation path and evaluation method thereof - Google Patents

Abstract

The invention relates to a P-domino output latch with an accelerated evaluation path and an evaluation method thereof. The apparatus includes P-evaluation logic, latching logic, holding logic, and acceleration logic, wherein the P-evaluation logic is coupled to a first N-channel device at a precharge node for evaluating a logic function according to at least one input data signal circuit providing an input data signal; the latch logic circuit is coupled and responds to a clock signal circuit and the pre-charge node, the clock signal circuit provides a clock signal, and the latch logic circuit controls the state of a latch node according to the state of the pre-charge node in an evaluation period, wherein the evaluation period is between a first edge and a second edge of the clock signal, and the latch logic circuit provides a tri-state to the latch node; the hold logic circuit is coupled to the latch node and maintains the state of the latch node when the tri-state exists, and provides the latch node with a complementary state at a complementary node; the acceleration logic is coupled to and responsive to the precharge node and the complementary latch node and is configured to control a state of an output node.

Description

P-Domino Output Latch with Accelerated Estimation Path and Its Estimation Method

The priority of this application is cited from US patent application 10/834900 filed April 28, 2004, the content of which is incorporated herein by reference.

This application is related to the following pending U.S. Patent Application No. 10/833,493, filed February 28, 2004, the contents of which are incorporated herein by reference, to the same assignee as this application, and having at least 1. The same inventor as the inventor in this case.

technical field

The invention relates to a dynamic logic circuit and a domino logic circuit, in particular to a P-domino output latch with an accelerated estimation path and an estimation method thereof.

Background technique

In recent years, the use of domino circuits has become more common due to the speed advantages they provide to integrated circuit design. A typical domino output latch consists of three stages: (1) An evaluation stage (evaluation stage), where an evaluation node is precharged to a specific state during half of a clock cycle, and the state of the evaluation node is Half the time after the cycle, the state of at least one input to the function evaluation logic in the evaluation stage is changed. (2) A latch stage, which latches the estimated state representation of the evaluating node of a latching node. (3) A buffering or inverting stage (buffering or inverting stage), used to adjust the state of the latch node, so as to disperse the input to the subsequent logic circuit as an output signal. Since the signal on which the output signal is based (that is, the state of the evaluation node) has been precharged to a logic circuit level, and because the function evaluation logic circuit is composed of logic circuit elements of the same type (that is, w is both N-channel elements or both P channel element), so the domino circuit has the advantage of fast operation. The speed advantage of the domino circuit is obtained in the traditional complementary metal-oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) static logic circuit, because of its lower input capacitance, lower switching threshold level, and function evaluation logic There are no parasitic diffusion capacitances on the output of the circuit. Circuit designers have found that domino circuits are particularly suitable for ultra-high-speed and time-critical applications, such as those used in microprocessors and digital signal processing.

Although domino circuits are useful for speeding up conventional CMOS logic circuits, the inventors have observed that the data output time of today's domino latches is a result of three-level component delays (also known as gate delays): a. One delay is caused by passing through the evaluation stage, one delay is caused by passing through the latch stage, and the last delay is caused by passing through the buffer stage. In today's integrated circuits made with 90nm manufacturing technology, the delay of each gate is about 15 to 20 picoseconds (picoseconds, pc), so the overall data output time is about 45 to 60ps, which is about equal to today's high One-third of the clock cycle of integrated circuits in high-order applications.

Therefore, it is necessary to provide a domino latch which has all the advantages mentioned above and which also has a lower data output time than all current domino latches.

In addition, there is a need to provide a P-domino latch with an accelerated evaluation path for time-critical applications.

It can be seen that the above-mentioned existing domino output latch obviously still has inconvenience and defects in use, and needs to be further improved urgently. In order to solve the problems of the domino output latch, the related manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above problems. Obviously, it is a problem that relevant industry players are eager to solve. Therefore, how to create a new domino output latch has become a goal that the current industry needs to improve.

In view of the above-mentioned defects in the existing domino output latch, the inventor actively researches and innovates on the basis of years of rich practical experience and professional knowledge in the design and manufacture of this type of product, and cooperates with the application of academic theory, in order to create a new one. The P-domino output latch with accelerated estimation path can improve the general existing domino output latch and make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The purpose of the present invention is to overcome the defective that existing domino output latch exists, and provide a kind of P-domino output latch of the tool acceleration estimation path of novel structure and the P-domino output latch of estimation method thereof, to be solved The technical problem is to make it an object of the present invention to reduce the data output time of the P-domino output latch under estimated conditions. The reason for reducing the data output time is that the P-domino output latch is usually a domino circuit string The final stage in which the input signal to the domino string can change state such that the P-domino output latch is evaluated at a very late time in the estimated second half cycle of signal CLKB, that is, on the first edge of the second half cycle Estimation between the second edge and the second edge greatly increases the execution speed of the component, which is more suitable for practical use.

Another object of the present invention is to overcome the defects of the existing domino output latch, and provide a novel structure of the P-domino output latch with accelerated estimation path and the P-domino output latch of the estimation method thereof, The technical problem to be solved is to reduce the data output time of the P-domino output latch under the estimation condition, and the P-estimation logic circuit of the P-domino output latch is further set as two parallel P channel elements for A two-input AND function is evaluated during evaluation. A first input node is coupled to the gate of the P-channel device and provides a first input signal; a second input node is coupled to the gate of the P-channel device and provides a second input signal. If either of the two input signals is asserted as a logic low level during evaluation, the AND function in execution performs an evaluation action, and the precharge node is charged to a high level via the associated actuated P-channel element and P-channel element . More than two P-channel components can be arranged in parallel to form a multi-input AND output latch without increasing the data output time, which is more suitable for practical use.

Another object of the present invention is to overcome the defects of the output method of the existing domino output latch, and provide a new estimation method of the P-domino output latch with accelerated estimation path, the technical problem to be solved is The data output time is lower than that of all current domino latches, and the execution speed of the components is greatly increased, so that it is more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A P-domino output latch with an accelerated evaluation path according to the present invention, which includes: a P-estimation logic circuit, coupled to a first N-channel element at a pre-charged node, for at least one input data A logic circuit function for signal estimation, and the input data signal is provided by an input data signal circuit; the latch logic circuit is coupled to and responds to a clock signal circuit and the pre-charge node, and is used for an evaluation period according to the pre-charge node The charge node controls the state of a latch node and provides a tri-state state to a latch node at other times while providing a clock signal at the clock signal circuit, wherein the evaluation period is between a first of the clock signal between an edge and a second edge; hold logic coupled to the latch node for maintaining the state of the latch node when the tri-state condition exists and for providing the latch at a complementary latch node a complementary state of the lock node; and an acceleration logic circuit coupled to and responsive to the precharge node and the complementary latch node for controlling the state of an output node.

The purpose of the present invention and the solution to its technical problems also adopt the following technical measures to further realize.

The aforementioned P-domino output latch, wherein the first N-channel element includes: a gate, a source and a drain, wherein the gate is used to receive the clock signal, the source and the drain The pole is coupled between a ground voltage and the precharge node.

In the aforementioned P-domino output latch, wherein the P-estimation logic circuit pulls up the precharge node to a logic circuit high level when the logic circuit function evaluation is true.

The aforementioned P-domino output latch, wherein the latch logic circuit includes: a second N-channel element having a first gate, a first source and a first drain, wherein the first gate The pole is coupled to the pre-charge node, the first source and the first drain are coupled between a ground voltage point and the latch node; a first P-channel element has a second gate and a a second source and a second drain, wherein the first gate receives the clock signal, the second source and the second drain are coupled between the latch node and the precharge node; and a The second P-channel element has a third gate, a third source and a third drain, wherein the third gate is coupled to the pre-charge node, the third source and the third drain are coupled connected between the precharge node and a voltage source.

The aforementioned P-domino output latch, wherein the holding logic circuit includes: a first inverter having a first input and a first output, wherein the first input is coupled to the latch node, the The first output is coupled to the complementary latch node; and a second inverter has a second input and a second output, wherein the second input is coupled to the complementary latch node, the second output Coupled to the latch node.

In the aforementioned P-domino output latch, the acceleration logic circuit includes a logic circuit NOR element.

The aforementioned P-domino output latch further includes a first P-channel element having a first gate, a first source and a first drain, wherein the first gate receives The clock signal, the second source and the second drain are coupled between the P-estimation logic circuit and a voltage source.

The aforementioned P-domino output latch, wherein said P-estimation logic circuit includes: a second P-channel element with a second gate, a second source and a second drain, wherein the second The gate receives a first input signal, the second source and the second drain are coupled between the precharge node and the first P-channel element; and a third P-channel element has a third gate Pole and a third source and a third drain, wherein the third gate receives a second input signal, the third source and the third drain are coupled to the precharge node and the first P between channel elements.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A P-domino output latch with an accelerated evaluation path according to the present invention, which includes: a P-logic circuit coupled to a first N-channel element at a precharge point node, for at least one input data The signal circuit evaluates a logic circuit function, and the input data signal circuit provides an input data signal, the first N-channel element includes: a gate, a source and a drain, wherein the gate is coupled to a clock signal circuit , the source and drain are coupled between a ground voltage point and the precharge node, and the clock signal circuit provides a clock signal; a latch logic circuit is coupled to and responds to the clock signal circuit and the a precharge node for controlling a latch node based on the state of the precharge point node during an evaluation period between the clock signal and for providing a tri-state state to the latch node at other times The time between a first edge and a second edge of , hold logic maintains the state of the latch node while the tri-state condition exists, and wherein the hold logic provides the latch node at a complementary latch node a complementary state of; and acceleration logic coupled to and responsive to the precharge node and the complementary latch node for controlling the state of an output node.

The purpose of the present invention and the solution to its technical problems also adopt the following technical measures to further realize.

In the aforementioned P-domino output latch, wherein the P-estimation logic circuit pulls up the precharge node to a logic circuit high level when the logic circuit function evaluation is true.

The aforementioned P-domino output latch, wherein the latch logic circuit includes: a second N-channel element having a first gate, a first source and a first drain, wherein the first gate The pole is coupled to the pre-charge node, the first source and the first drain are coupled between a ground voltage point and the latch node; a first P-channel element has a second gate and a first Two sources and a second drain, wherein the second gate receives the clock signal, the second source and the second drain are coupled between the latch node and the pre-charge node; and a first Two P-channel elements have a third gate, a third source and a third drain, wherein the third gate is coupled to the pre-charge node, the third source and the third drain are coupled connected between the precharge node and a voltage source.

The aforementioned P-domino output latch, wherein the holding logic circuit includes: a first inverter having a first input and a first output, wherein the first input is coupled to the latch node, the The first output is coupled to the complementary latch node; and a second inverter has a second input and a second output, wherein the second input is coupled to the complementary latch node, the second output Coupled to the latch node.

In the aforementioned P-domino output latch, the acceleration logic circuit includes a logic circuit NOR element.

The aforementioned P-domino output latch further includes: a first P-channel element having a first gate, a first source and a first drain, wherein the first gate receives the clock signal , the first source and the first drain are coupled between the P-estimation logic circuit and a voltage source.

The aforementioned P-domino output latch, wherein said P-estimation logic circuit includes: a second P-channel element with a second gate, a second source and a second drain, wherein the second The gate receives a first input signal, the second source and the second drain are coupled between the precharge node and the first P-channel element; and a third P-channel element has a third gate Pole and a third source and a third drain, wherein the third gate receives a second input signal, the third source and the third drain are coupled to the precharge node and the first P between channel elements.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to the estimation method of a P-domino output latch with accelerated estimation path proposed by the present invention, it includes the following steps: preset a pre-charge node, when a clock signal circuit is in a first logic circuit state, and the clock signal circuit provides a clock signal; dynamically evaluates a P logic circuit function to control the first node when the clock signal changes to a second logic circuit state; determines the precharge node latch according to an estimation period locking a logic circuit state of a latch node, wherein the evaluation period starts when the clock signal transitions to the second logic circuit state and ends when the clock signal next transitions to the first logic circuit state ; complementing the logic state of the latch node to provide a complementary latch node; and speeding up representation of the speedup output by responding to the state of the precharge node during the evaluation.

The purpose of the present invention and the solution to its technical problems also adopt the following technical measures to further realize.

In the aforementioned P-domino output latch estimation method with an accelerated estimation path, the presetting step includes precharging the precharging node to a high-low logic circuit state.

The aforementioned method for estimating a P-domino output latch with an accelerated evaluation path further includes the following steps: maintaining the logic circuit state of the latch node by providing a tri-state state to the latch node, and coupling a hold circuit to the latch node.

By virtue of the above-mentioned technical solution, the P-domino output latch with accelerated estimation path and its estimation method of the present invention have at least the following advantages:

The P-domino output latch with accelerated estimation path of the present invention can reduce the data output time of the P-domino output latch under estimation conditions, and the reason why it can reduce the data output time is that the P-domino output latch is usually a The final stage of the domino string, where the input signal to the domino string can change state such that the P-domino output latch is evaluated at a very late time in the second half cycle of the estimated signal CLKB, that is, in the second half cycle of Estimates are made between the first edge and the second edge. Therefore, the P-domino output latch of the present invention eliminates the gate delay associated with the evaluation condition of the latch stage in the conventional N-domino latch, thereby greatly increasing the execution speed of the components.

The P-domino output latch with accelerated estimation path of the present invention can overcome the defective that existing domino output latch exists, and it reduces the data output time of P-domino output latch under estimation condition, and its P-domino output The latched P-evaluation logic is configured as two parallel P-channel elements to evaluate a two-input AND function during evaluation. A first input node is coupled to the gate of the P-channel device and provides a first input signal; a second input node is coupled to the gate of the P-channel device and provides a second input signal. If either of the two input signals is asserted as a logic low level during evaluation, the AND function in execution performs an evaluation action, and the precharge node is charged to a high level via the associated actuated P-channel element and P-channel element . More than two P-channel elements can be arranged in parallel to form a multi-input AND output latch without increasing the data output time.

The estimation method of the P-domino output latch with accelerated estimation path of the present invention can overcome the defective that the output method of existing domino output latch exists, and its data output time is lower than the data of all domino latches now The output time greatly increases the execution speed of the component.

To sum up, the special P-domino output latch with accelerated estimation path of the present invention and its estimation method eliminate the associated gate delay of the latch stage in the traditional N-domino latch under estimation conditions, thus making the execution speed of the components greatly increase. It has the above-mentioned many advantages and practical value, and there is no similar structural design and method publicly published or used in similar products and methods, so it is indeed innovative, and it has great advantages no matter in product structure, method or function. Improvement, great progress has been made in technology, and has produced easy-to-use and practical effects, and has improved multiple functions compared with the existing domino output latch, so it is more suitable for practical use, and has wide application value in the industry , Sincerely a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic illustration of an example of a P-domino output latch illustrating the characteristics of a P-domino circuit.

FIG. 2 is a timing diagram illustrating the operation of the P-domino output latch of FIG. 1. Referring to FIG.

FIG. 3 is a schematic diagram of an embodiment of a P-domino output latch with an accelerated evaluation path according to the present invention.

FIG. 4 is a schematic diagram of another embodiment of a P-domino logic circuit AND latch with an accelerated evaluation path according to the present invention.

FIG. 5 is an operation timing diagram of the P-domino AND latch in FIG. 4 .

100 P-Domino output latch 101 Estimation level

102 Latch level 103 Buffer level

104 Semi-Hold Circuit 105 Weak Hold Circuit

106 P-estimation logic circuit 107 input node

109 Precharge Node 300 P-Domino Output Latch

301 Estimation level 302 Latch level

303 Acceleration Logic Circuit 305 Weak Hold Circuit

306 P-estimation logic circuit 307 input node

308 Clock Node 309 Precharge Node

310 Latch Node 311 Complementary Latch Node

312 Output Node Lock 400 P-Domino AND Latch

401 Estimation level 402 Latch level

403 Acceleration Logic Circuit 404 Semi-Holding Circuit

405 Weak Hold Circuit 406 First Input Node

407 Second input node 410 Latch node

412 output node

Detailed ways

For further elaborating the technical means and effect that the present invention takes for reaching the intended invention purpose, below in conjunction with accompanying drawing and preferred embodiment, to the P-domino output latch of the tool acceleration estimation path that proposes according to the present invention and its estimation method Its specific implementation, structure, method, steps, features and effects thereof are described in detail below.

The following description is provided to enable those skilled in the art to make and use the invention, where the invention is described for a particular application and its requirements. However, those skilled in the art will readily be able to make various changes to the preferred embodiments of this invention, and the broad theory defined herein may be applied to other embodiments. Accordingly, the present invention is not limited to the embodiments described and illustrated herein, and its scope is to be regarded as corresponding to the widest scope having the principles and novel features disclosed herein.

Since the inventors of the present case have realized the need for a better domino latch for speed-critical logic circuits, they have developed a P-domino latch with an accelerated evaluation path that provides the latched The output of the lock is a variety of simple to complex logic circuit estimation functions. This type of latch is significantly faster than existing designers, and will be further described below with reference to FIGS. 1 to 5 . A P-domino latch embodiment of the present invention provides a significant increase in overall device operation speed when used in pipelined or other high-level architectures that rely heavily on the evaluation of logic circuit functions in multiple subsequent stages.

Please refer to FIG. 1 , which is a schematic diagram of an example of a P-domino output latch 100 . P-domino output latch 100 (P-domino output latch) comprises an evaluation stage (evaluationstage) 101, and this evaluation stage 101 is composed of P channel element P1, N channel element N1 and P-estimation logic circuit (P- evaluation logic) 106, wherein the P-estimation logic circuit 106 is coupled between the P-channel element P1 and the N-channel element N1, the source of the P-channel element P1 is coupled to a voltage source VDD, and the drain of the P-channel element P1 The pole is then coupled to the P-estimation logic circuit 106 . In addition, the P-estimation logic circuit 106 is also coupled to the drain of the N-channel device N1 at a pre-charge node 109 , and the source of the N-channel device N1 is coupled to the ground voltage "ground". And the precharge node 109 provides a signal EQLO. A clock signal (clock signal) CLKB is provided to the gates of the P-channel element P1 and the N-channel element N1 through a clock node (clock node) 108; at least one input data signal circuit IN[N: 1] is provided through at least one input node ( input nodes) 107 are provided to the P-estimation logic circuit 106, and the input data signal circuit provides an input data signal; the precharge node 109 is coupled to a half keeper circuit (half keeper circuit) 104, and the half keeper circuit 104 is composed of an inverse The phase device (inverter) U4 is composed, the output of the inverter U4 is coupled to the gate of a P-channel element P4; the source of the P-channel element P4 is coupled to the voltage source VDD; and the drain of the P-channel element P4 is coupled to To the input of inverter U4 and precharge node 109.

The configuration of the P-estimation logic circuit 106 depends on the particular logic circuit function to be evaluated. However, it should be noted that in keeping with domino circuit design principles, the P-estimation logic circuit 106 includes at least one P-channel element. For example, a simple P-domino latch 100 can be obtained by providing a single P-channel element (not shown), wherein the drain of the single P-channel element is connected to the pre-charge node 109, and its source is connected to the P-channel element The drain of P1, and its gate is coupled to a single input signal IN1. Or, when designing according to the setting of FIG. 1, a P-domino dual-input NAND latch is set by providing two parallel P-channel elements (not shown), wherein the gates of the two P-channel elements are controlled by two Driven by input signals IN1 and IN2. A P-domino dual-input NOR latch is configured by stacking two P-channel elements (not shown) and driving their gates with two input signals IN1, IN2. The same applies to others.

The evaluation stage 101 is coupled to a latching stage 102, the latching stage 102 includes stacked P-channel elements P2, P3 and N-channel element N2, wherein the source of P2 is coupled to a voltage source VDD, the drain of the P-channel element P2 is coupled to the source of the P-channel element P3, the drain of the P-channel element P3 is coupled to the drain of the N-channel element N2, wherein the drain of the N-channel element N2 constitutes a latch node (latch node) 110, and the latch node 110 provides a latch signal QB; the source of the N-channel element N2 is coupled to ground, the gate of the P-channel element P3 is coupled to the clock node 108, and the P-channel element The gates of P2 and N-channel device N2 are coupled to the pre-charge node 109 .

The latch stage 102 is coupled to a buffering stage 103, which includes an inverter U1, wherein the input of the inverter U1 is coupled to the latch node 110 and is coupled to a weak hold circuit (keeper circuit) 105, and the weak hold circuit 105 includes inverters U2 and U3. The input of the inverter U2 is coupled to the latch node 110 and coupled to the output of the inverter U3, and the output of the inverter U2 is coupled to the input of the inverter U3. The output of the buffer stage 103 forms an output node 111, which provides an output signal EQUAL. Although an inverter U1 is used in the buffer stage 103 of the P-domino output latch, it is known to those skilled in the art that the inverter U1 can be replaced by a non-inverting buffer so that the desired output state is distributed to subsequent logic circuit.

Those skilled in the art also know that a typical application of the P-domino output latch 100 of FIG. 1 is on the last domino stage in a series of domino stages. All internal estimators. In addition, those skilled in the art can also understand that the immediately preceding domino stage with the output signal coupled with node 107 has to be set with only one evaluation stage similar to the evaluation stage 101, so it is generally called "header ( The component P1 of “header device)” does not need to be used, and the “headless device” setting of the P-domino output latch 100 may not include P1.

Referring now to FIG. 2, there is shown a timing diagram 200 illustrating the operation of the P-domino output latch 100 of FIG. for time. At time T0, the signal CLKB is at a high level, the P-channel element P1 is turned off and the N-channel element N1 is turned on, and the signal EQLO is precharged to a low level of a logic circuit to prepare for the falling edge of the signal CLKB. Signal IN[N:1] is evaluated. During the half period when the signal CKLB is at a high level, the P-channel device P2 is turned on and the P-channel device P3 and the N-channel device N2 are turned off, thus providing a tri-state state for the latch node 110 . Therefore, when the latch node 110 is in the tri-state state, the signal QB maintains its previous state by the weak hold circuit 105 , ie the weak hold circuit 105 shown in the pulse diagram 200 acts as a logic high level. Therefore, the signal EQUAL of the output node 111 is at a logic low level. When the signal CLKB is at a high level half cycle, the signal IN[N:1] is typically at a high level at time T0 (as shown in Figure 1), this is due to the domino circuit shown in Figure 1 100 is typically set up in a cascaded setup (as discussed above) where the output signal of a preceding domino circuit is connected to the input signal of a subsequent stage circuit. Therefore, since the IN[N:1] signal is at the high level of the logic circuit at the time point T1, the P-channel element in the P-estimation logic circuit 106 is turned off. For the purpose of teaching the present invention, at least one input signal IN[N:1] is regarded as a single signal IN1, which determines the low level of a logic circuit, so that the logic circuit function performed by the P-estimation logic circuit 106 is Estimated to be true.

At a subsequent time point T1, the signal CLKB is switched to a logic circuit low level, and turns on the P-channel elements P1 and P3, and turns off the N-channel element N1. Since the signal IN[N:1] is at a high level at the time point T1, the P-channel element of the P-estimation logic circuit 106 is turned off, so that the signal EQLO is not driven by the P-estimation logic circuit 106 . However, during this time, the half-hold circuit 104 maintains the signal EQLO at a logic low level. If any one of the at least one input signal IN[N:1] is driven to a logic circuit level during the half period in which the signal CLKB is low, the P-estimation logic circuit evaluates the logic circuit function as true (eg Subsequent time point T2), the N-estimation logic circuit 106 is turned on during at least one P-channel element P1 conduction period, and its efficiency is higher than that of the half-hold circuit 104, so the signal EQLO passes through the P-estimation logic circuit 106 and the P-channel element P1 is charged to a high logic circuit level, as shown at time point T3. Wherein, a gate delay stage via the P-estimation logic circuit 106 is shown.

When the signal EQLO becomes a high logic circuit level (or is in the "evaluation" stage), the P-channel element P2 is turned off and the N-channel element N2 is turned on, and the latch signal QB is thus driven to a logic circuit low state, such as the time point Shown in T4. An additional gate delay stage is added via the latch stage 102 when the state of the signal EQLO is transmitted to the signal QB.

The inverter U1 responds to the signal QB by driving the output signal EQUAL to a logic high state, as shown at time point T5. When the state of the latch signal QB is transmitted to the input signal EQUAL through the inverter U1 , a third gate delay stage is added through the buffer stage 103 .

Since the domino circuit is typically set in series, the input signal IN[N:1] can be at any time point of the signal CLKB. This time point is set after the signal CLKB becomes a low level and before the signal CLKB returns to a high level. The period of time between the signal CLKB falling to a low level and returning to a high level is generally called an "estimation period".

Then, the signal CLKB becomes a high level, and the input signal IN[N:1] is also driven to a high level. The signal EQLO is again precharged to a low level by the N-channel device N1, and the latch node 110 is tri-stated. The weak hold circuit 105 maintains the original state of the signal QB, and the complementary state of QB is provided to the signal EQUAL by the inverter U1.

At the subsequent time point T6, the signal CLKB changes to a logic circuit low level again, while the input signal IN[N:1] is a high logic circuit level, so the P-channel element P1 is turned on, and the P-estimation logic circuit 106 is not Make an estimate. Therefore, the signal EQLO is not charged to a logic high level, and thus provides the signal EQUAL for the charging path of the signal QB of the P-channel elements P2 and P3 to the voltage source VDD. When the signal QB becomes a high level at the time point T7, the signal EQUAL is driven to a low level at the time point T8. However, those skilled in the art know that at any time point within the half cycle of the signal CLKB after the time point T6, the correct combination of the driving input signal IN[N:1] (so that the logic circuit function performed by the P logic circuit 106 Estimated to be true), the signal EQLO can be charged to a high level, and the signal QB can be driven to a low level, and the signal EQUAL can be driven to a high level.

Domino circuits, exemplified by P-domino output latch 100 of FIG. charging) to a logic circuit state due to the reduced input capacitance of the evaluation logic circuit 106 , the lower switching threshold level, and the absence of parasitic diffusion capacitance on the output of the evaluation logic circuit 106 . Since the timing mechanisms (eg, P-channel device P1 and N-channel device N1 ) are integrated in the evaluation stage 101 with evaluation logic 106 , the data settling time is substantially eliminated. Those skilled in the art will understand that more complex evaluation logic circuits (such as multiple input multiplexers) can be configured as P evaluation logic circuit 106 in P-domino output latch 100, while constraints do not slow down or affect its speed. related power.

Although the domino output latch has high speed, the inventors of the present case have realized that it is necessary to provide the P-domino output latch 100 with a data output time much lower than that of all current devices. As shown in Figure 2, the data output time of a current P-domino output latch 100 is the result of three gate delays, one of which is caused by the estimation stage 101, and one of the delays is caused by the latch stage 102, another amount of delay is caused by the buffer stage 103. Therefore, the inventors of the present application have developed a P-domino output latch with an accelerated evaluation path that can reduce data output time, wherein the time is shortened to one-third of the conventional P-domino output latch 100 . Hereinafter, the present invention will continue to be described with reference to FIG. 3 to FIG. 5 as follows.

Please refer to FIG. 3 , which illustrates an example of a P-domino output latch 300 of the present invention. Same as the traditional P-domino output latch 100 described in conjunction with FIG. 1, the P-domino output latch 300 of the present invention has an estimation stage 301, and the estimation stage 301 is estimated by the P channel element P1, the N channel element N1 and the P-channel element N1. The logic circuit 306 is stacked, wherein the P-estimation logic circuit 306 is coupled between the elements P1 and N1, the source of the P-channel element P1 is coupled to a voltage source VDD, and the drain of the P-channel element P1 is coupled to Connected to P-estimation logic circuit 306. Similarly, the source of the N-channel element N1 is coupled to ground, and the P-estimation logic circuit 306 is coupled to the drain of the N-channel element N1 at a pre-charge node 309, and the pre-charge node 309 provides a signal EQLO, a clock The signal CLKB is provided to the gates of the P-channel device P1 and the N-channel device N1 through a clock node 308, and at least one input data signal IN[N:1] is provided to the P-estimation logic circuit through at least one input node 307. 306. The pre-charge node 309 is coupled to the half-hold circuit 304, wherein the half-hold circuit 304 is composed of an inverter U4, and the output of the inverter U4 is coupled to the gate of a P-channel device P4. The source of the P-channel device P4 is coupled to the voltage source VDD, and the drain of the P-channel device P4 is coupled to the input of the inverter U4 and the pre-charge node 309 .

The setting of the P-estimation logic circuit 306 depends on the particular logic circuit to be evaluated in a manner substantially similar to that of the P-domino latch 100 in FIG. The principles are consistent and contain at least one P-channel element. For example, a simple P-domino latch 300 is provided with a single P-channel device (not shown), the drain of which is connected to pre-charge node 309, and the source of which is coupled to P-channel device P1 The drain and the gate are coupled to a single input signal circuit, and the input signal circuit provides an input signal IN1. Alternatively, a P-domino dual-input AND latch is provided by providing two parallel P-channel elements (not shown), wherein the gates of the two P-channel elements are respectively driven by two input signals IN1 and IN2. Such elements will be described below with reference to FIG. 4 . The setup of a P-domino dual-input OR latch is accomplished by stacking two P-channel elements (not shown) and driving their gates with two input signals IN and IN2. So on and so forth.

The estimation stage 301 is coupled to a latch stage 302, and the latch stage 302 is formed by stacking P-channel elements P2, P3 and N-channel element N2, wherein the source of the P-channel element P2 is coupled to the voltage source VDD, and the P The drain of the pass element P2 is coupled to the source of the P-channel element P3, and the drain of the P-channel element P3 is coupled to the drain of the N-channel element N2 to form a latch node 310, which provides a The latch signal circuit provides a latch signal QLI. The source of the N-channel device N2 is coupled to ground, the gate of the P-channel device P3 is coupled to the clock node 308 , and the gates of the P-channel device P2 and N-channel device N2 are coupled to the pre-charge node 309 .

Latch node 310 is coupled to a weak hold circuit 305, which includes inverters U2 and U3, wherein the input of inverter U3 is coupled to latch node 310 and the output of inverter U2, and the inverter The output of the phaser U3 is coupled to the input of the inverter U2, and constitutes a complementary latch node 311 and provides a complementary latch signal circuit, and the complementary latch signal circuit provides a complementary latch signal QLIB.

Compared with the conventional P-domino output latch 300 , the evaluation stage 301 and the latch stage 302 of the present invention are both coupled to the acceleration logic circuit 303 . In one embodiment, the acceleration logic 303 includes a NOR logic gate, but in other embodiments it is different. A first input of the inverter U1 is coupled to the complementary latch node 311 , and a second input of the inverter U1 is coupled to the precharge point node 309 . The output of the acceleration logic circuit 303 forms an output node 312, and the output node 312 provides an output signal circuit, and the output signal circuit provides an output signal EQUALB. Although the speed-up logic circuit 303 of the P-domino output latch 300 example of the present invention uses a dual-input NOR gate U1, the inventor of the present case claims that other different embodiments exist, such as different logic circuit elements (such as NAND and exclusive OR (exclusive -OR), etc.) and logic circuit elements that provide more than two inputs and whose qualifying signals are sent to other inputs.

A typical application of the P-domino output latch 300 of the present invention is as the last domino stage in a row of domino stages, where all outputs of the domino stage are evaluated during the same period of signal CLKB. In addition, similar to the P-domino latch 100 of FIG. 1, those skilled in the art will understand that an evaluation stage similar to the evaluation stage 301 can be set immediately before the domino stage with an output signal coupled to the node 307, so it is not necessary to Requires the presence of header element P1. Therefore, the present invention also includes a headerless embodiment without the header element P1.

An accelerated evaluation path is provided in the P-domino latch 300 of the present invention by directly coupling the precharge node 309 to the accelerated logic circuit 303, thereby bypassing the latch stage 302, thus obtaining The gate delay caused by the latch stage is removed when the P evaluation logic circuit 306 evaluates to true, and precharges the node 309 to a logic high level.

Referring now to FIG. 4 , it is a schematic diagram of another P-domino AND latch 400 with an accelerated evaluation path according to the present invention, wherein the components of the P-domino AND latch 400 are the same as those of the P-domino output latch 300 of FIG. 3 The parts and components of the same class are the same, but the hundreds digit of the drawing number is changed from 3 to 4. In addition, the P-estimation logic circuit 306 of the P-domino output latch 300 in FIG. 3 is further configured as two parallel P-channel elements P5 and P6 for evaluating a dual-input AND function during evaluation. A first input node 406 is coupled to the gate of the P-channel element P5 and provides a first input signal IN1; a second input node 407 is coupled to the gate of the P-channel element P6 and provides a second input Signal IN2. If any one of the two input signals IN1, IN2 is asserted as logic circuit low level during the evaluation period, the AND function in execution performs the evaluation action, and the pre-charge node 409 passes through the relevant activated P-channel elements P5, P6 and P The channel element P1 is charged to a high level. What the inventor of the present invention should explain is that more than two P-channel elements can be arranged in parallel to form a multi-input AND output latch without prolonging the data output time. The operation principle of the P-domino dual-input AND latch 400 will be described in detail below with reference to FIG. 5 .

Referring now to FIG. 5, it is an operation timing diagram 500 of the dual-input P-domino AND latch 400 of FIG. The signal circuit also provides signals CKLB, IN1, IN2, EQLO, QLI and EQUALB. At the time point T0 when the signal CLKB is at a high level, P1 is turned off and N1 is turned on, thereby pre-charging the signal EQLO to a low level of a logic circuit to prepare for evaluating the signals IN1 and IN2 at the falling edge of the signal CLKB. During the half period when the signal CLKB is high, the P-channel device P2 is turned on and the P-channel device P3 and the N-channel device N2 are turned off, thus providing a tri-state state for the latch node 410 . Therefore, when the latch node 410 is in the tri-state state, the signal QLI maintains the original state for the weak hold circuit 405, wherein the weak hold circuit 405 is at a logic circuit high level in the timing diagram 500, and also the complementary signal QLIB of the signal QLI Maintain the low level of the logic circuit. Therefore, the signal EQUALB at the output node 412 is at a logic high level due to the low state of the EQLO and QLIB signals. Typically, the input signals IN1 and IN2 are at a high level when the signal CLKB is at a high level in half a cycle, as shown at time point T0. Therefore, at the time point T1, since the input signals IN1 and IN2 are at the high level of the logic circuit, the P-channel elements P5 and P6 are turned off.

At time T1, the signal CLKB is determined to be at the low level of the logic circuit, and the P-channel elements P1 and P3 are turned on and the N-channel element N1 is turned off. Since the signals IN1 and IN2 are at a high level at time T1 and the P-channel elements P5 and P6 are turned off, the signal EQLO is not driven to a high level by the P-channel elements P5 or P6. During this period of time, the half-hold circuit 404 maintains the signal EQLO at a low logic circuit level. During the half period when the signal CLKB is low level, if the signal IN1 or IN2 (or both IN1 and IN2) is determined to be low level, the logic circuit function to be executed is turned on and determined to be low level input signal IN1, IN2 The P-channel components P6, P5 are estimated. At the time point T2, the signal IN1 is judged to be low level, while the signal IN2 maintains the high level of the logic circuit. At this time, the P-channel element P6 is driven to be turned off, and EQLO is established, which is charged to the voltage source through the P-channel elements P5 and P1. The charging path of VDD; since the charging efficiency is higher than that of the half-hold circuit 404, the signal EQLO is charged to a high logic circuit level, as shown at time point T3. A gate delay stage is presented via the evaluation stage 401 .

When the signal EQLOB is charged (or “evaluated”), the P-channel device P2 is turned off and the N-channel device N2 is turned on, and drives the latch signal QLI to a logic low state, as shown at time point T4. When the signal EQLO is transmitted to the signal QLI, an additional gate delay stage can be added via the latch stage 402, as shown at time point T4. Unlike the conventional P-domino output latch 100, the signal EQLO directly drives the second input to the speed-up logic circuit 403, and simultaneously Drive the output signal EQUALB to a low level of a logic circuit at the time point T4. Therefore, the present invention only passes through the second gate delay amount during the evaluation, thus reducing the data output time to one-third of the conventional P-domino output latch 100 .

At time point T5, the complementary latch signal QLIB is driven to a logic high level, which ensures that the output signal EQUALB remains low when the signal EQLO is precharged to a low level.

As shown in Figure 2 above, since the domino circuit is typically connected in series, the output signals IN1 and IN2 can be determined to be low at any point in the evaluation period, where the evaluation time occurs when the signal CLKB changes to a low level After that and back to the high level again.

Afterwards, the signal CLKB changes to a high level, the first input signal IN1 is also driven to a high level, the signal EQLO precharges N1 to a low level, and a tri-state is added to the latch node 410 . The weak hold circuit 405 maintains the states of the signals QLI and QLIB, and the output signal EQUALB also maintains the original level because EQLO is at the low level of the logic circuit, so the signal QLIB can control the state of the output signal EQUALB.

At a subsequent time point T6, the signal CLKB is determined to be low again when both IN1 and IN2 are high, so the P-channel element P1 is turned on, and the P-channel elements P5 and P6 are turned off. Therefore, the signal EQLO is not discharged, thus providing a charging path for the signal QLI to be charged to the voltage source VDD through the P-channel elements P2 and P3. When the signal QLI turns to a high level at the time point T7, the signal QLIB is driven to a low level at a time point T8; and since both EQLO and QLIB are at a low level, the output signal EQUALB is driven to a high level at a time point T9. It should be noted that driving IN1 or IN2 (or both) at any point in the half cycle of the CLKB signal after time T6 causes the signal EQLO to be charged high and the signal EQUALB to be driven low.

The invention has been described in detail above with respect to certain preferred embodiments, but the invention also has other different embodiments. For example, the P-estimation logic can be made simple or complex and implemented in any suitable manner known to those skilled in the art. Furthermore, although the present invention is disclosed to be implemented using complementary metal-oxide-semiconductor devices (such as NMOS and PMOS transistors, etc.), different or similar technologies and configurations of other bipolar devices can also be used in a similar manner.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims (18)

1. A P-domino output latch with accelerated estimation path, characterized in that it comprises: P-estimation logic circuit coupled to a first N-channel element at a precharge node for estimating a logic circuit function based on at least one input data signal provided by an input data signal circuit; Latch logic circuit, coupled to and responsive to a clock signal circuit and the pre-charge node, for controlling the state of a latch node according to the pre-charge node during an evaluation period, and providing a tri-state state to the latch at other times lock node, and a clock signal is provided at the clock signal circuit, wherein the evaluation period is between a first edge and a second edge of the clock signal; hold logic coupled to the latch node for maintaining the state of the latch node in the presence of the tri-state condition and for providing a complementary state of the latch node at a complementary latch node; and The acceleration logic circuit is coupled to the precharge node and the complementary latch node, and its output is an output node. The acceleration logic circuit controls the state of the output node according to the output of the precharge node and the complementary latch node. 2. The P-domino output latch according to claim 1, wherein said first N-channel element comprises: A gate, a source and a drain, wherein the gate is used to receive the clock signal, the source and the drain are coupled between a ground voltage and the precharge node. 3. The P-domino output latch according to claim 1, wherein said P-estimation logic circuit pulls the precharge node to a logic circuit high level when the logic circuit function estimation is true allow. 4. The P-domino output latch according to claim 1, wherein said latch logic circuit comprises: A second N-channel element having a first gate and a first source and a first drain, wherein the first gate is coupled to the precharge node, the first source and the first drain pole coupled between a ground voltage point and the latch node; A first P-channel element having a second gate, a second source and a second drain, wherein the second gate receives the clock signal, and the second drain is coupled to the latch node ;and A second P-channel element having a third gate, a third source and a third drain, wherein the third gate is coupled to the precharge node, the third source and the third drain coupled between a voltage source and the second source. 5. The P-domino output latch according to claim 1, wherein said holding logic circuit comprises: a first inverter having a first input and a first output, wherein the first input is coupled to the latch node, and the first output is coupled to the complementary latch node; and A second inverter has a second input and a second output, wherein the second input is coupled to the complementary latch node, and the second output is coupled to the latch node. 6. The P-domino output latch as claimed in claim 1, wherein said acceleration logic circuit comprises a logic circuit NOR element. 7. The P-domino output latch according to claim 1, further comprising: A first P channel element has a first gate, a first source and a first drain, wherein the first gate receives the clock signal, the first source and the first drain A drain is coupled between the P-estimation logic circuit and a voltage source. 8. The P-domino output latch according to claim 7, wherein said P-estimation logic circuit comprises: A second P-channel element having a second gate, a second source and a second drain, wherein the second gate receives a first input signal, the second source and the second drain coupled between the precharge node and the first P-channel element; and A third P-channel element having a third gate, a third source and a third drain, wherein the third gate receives a second input signal, the third source and the third drain coupled between the precharge node and the first P-channel device. 9. A P-domino output latch with an accelerated estimation path, characterized in that it comprises: P-estimation logic circuit coupled to a first N-channel element at a precharge point node for estimating a logic circuit function based on at least one input data signal circuit providing an input data signal, the The first N-channel element contains: A gate, a source and a drain, wherein the gate is coupled to a clock signal circuit, the source and drain are coupled between a ground voltage point and the precharge node, and the clock signal circuit provide a clock signal; a latch logic circuit, coupled to and responsive to the clock signal circuit and the precharge node, for controlling a latch node according to the state of the precharge point node during an evaluation period, and for providing a tri-state state at other times to the latch node, wherein the evaluation period is the time between a first edge and a second edge of the clock signal, hold logic maintains the state of the latch node while the tri-state condition exists, and wherein the hold logic circuit provides a complementary state of the latch node at a complementary latch node; and The acceleration logic circuit is coupled to the precharge node and the complementary latch node, and its output is an output node. The acceleration logic circuit controls the state of the output node according to the output of the precharge node and the complementary latch node. 10. The P-domino output latch according to claim 9, wherein said P-estimation logic circuit pulls the precharge node to a logic circuit high level when the logic circuit function is estimated to be true allow. 11. The P-domino output latch according to claim 9, wherein said latch logic circuit comprises: A second N-channel element having a first gate and a first source and a first drain, wherein the first gate is coupled to the precharge node, the first source and the first drain coupled between a ground voltage point and the latch node; A first P-channel element having a second gate, a second source and a second drain, wherein the second gate receives the clock signal, and the second drain is coupled to the latch node ;and A second P-channel element having a third gate, a third source and a third drain, wherein the third gate is coupled to the precharge node, the third source and the third drain The pole is coupled between a voltage source and the second source. 12. The P-domino output latch according to claim 9, wherein said holding logic circuit comprises: a first inverter having a first input and a first output, wherein the first input is coupled to the latch node, and the first output is coupled to the complementary latch node; and A second inverter has a second input and a second output, wherein the second input is coupled to the complementary latch node, and the second output is coupled to the latch node. 13. The P-domino output latch as claimed in claim 9, wherein said acceleration logic circuit comprises a logic circuit NOR element. 14. The P-domino output latch according to claim 9, characterized in that it further comprises: A first P channel element has a first gate, a first source and a first drain, wherein the first gate receives the clock signal, the first source and the first drain are coupled Connected between the P-estimation logic circuit and a voltage source. 15. The P-domino output latch according to claim 14, wherein said P-estimation logic circuit comprises: A second P-channel element having a second gate, a second source and a second drain, wherein the second gate receives a first input signal, the second source and the second drain coupled between the precharge node and the first P-channel element; and A third P-channel element having a third gate, a third source and a third drain, wherein the third gate receives a second input signal, the third source and the third drain coupled between the precharge node and the first P-channel device. 16. A method for estimating a P-domino output latch with an accelerated estimating path, comprising the following steps: A pre-charge node is preset to be low when a clock signal circuit is in a first logic circuit state, and the clock signal circuit provides a clock signal; dynamically estimating a P logic circuit function to control the precharge node when the clock signal transitions to a second logic circuit state; a logic circuit state of the precharge node latching a latch node determined according to an evaluation period starting when the clock signal transitions to the second logic circuit state and ending at the clock signal upon a transition to the first logic circuit state; complementing the logic circuit state of the latch node to provide a complementary latch node; and Responding to the state of the precharged node during the evaluation speeds up the representation of the output. 17. The method of claim 16, wherein said presetting step comprises precharging the precharge node to a high-low logic circuit state. 18. The method of claim 16, further comprising the steps of: The logic circuit state of the latch node is maintained by providing a tri-state state to the latch node and coupling a hold circuit to the latch node.

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