CN100495917C - A surge separation circuit - Google Patents

Abstract

A surge separation circuit uses the clock signal inside the integrated circuit to separate the surge appearing on the input signal at the edge of the clock signal. The surge separation circuit includes an edge signal generating device, an OR gate, an AND gate, a selection device, a first trigger and a second trigger. By utilizing the specific connection relationship and functions of the above-mentioned components, the surge separation circuit can filter out surges with a period equivalent to half of the internal clock signal.

Description

A surge separation circuit

technical field

The invention relates to a signal processing circuit, in particular to a surge separation circuit capable of separating surges at any moment.

Background technique

In the design of an integrated circuit (IC, Integrated Circuit), there are usually some unforeseen glitches passing through the designed circuit, which leads to the wrong logic output of the circuit, especially the signal input from the outside of the integrated circuit ( This is especially true when a surge occurs, such as some control signals). Therefore, how to eliminate the surge in the designed circuit so that the circuit can have a correct logic output is a very important issue.

A kind of known technology is to adopt internal clock signal to come synchronous external signal, to avoid because external signal appears surge, and cause the logical output of design circuit to appear wrong, yet this known technology has following shortcoming: chip control logic disorder; affect the stability of chip performance; and when the surge appears on the edge of the internal clock signal, it will still cause the wrong logic output of the designed circuit; as shown in Figure 1.

Fig. 1 is a timing diagram of an internal clock signal, an external signal and a synchronous output signal in the known technology, and Fig. 1 shows that when the external signal has a surge (as shown in 102) on the rising edge of the internal clock signal, the internal clock signal will The synchronous output signal generated after the external signal is synchronized still cannot eliminate the surge, and will also amplify the surge (as shown in 104 ).

In addition, there is also a known technology, which is a digital filter disclosed in US Patent No. US20030091135. This digital filter is used to receive a digital input signal with a surge. This digital filter includes: a delay line, which is used to The digital input signal is time-delayed to generate a delayed digital input signal; the rising edge detector is used to make the delayed digital input signal generate a rising edge identification signal; the falling edge detector is used to make the delayed digital input signal generate Falling edge identification signal; the first mixing device is used to generate the mixed signal of the rising edge filtered identification signal and the digital input signal; the second mixing device is used to generate the mixed signal of the falling edge filtered identification signal and the digital input signal; The three-mixing device is used to receive the mixed signal output by the first mixing device and the second mixing device to generate a digital output signal without a surge on the rising edge and falling edge of the clock signal, so that the digital filter can output without Burst digital output signal.

Although this digital filter overcomes the three shortcomings caused by the use of an internal clock signal to synchronize external signals, this digital filter still has a shortcoming, that is, it cannot filter out surges whose period is greater than that of the delayed digital input signal.

Contents of the invention

The object of the present invention is to provide a surge separation circuit, so that the surge can be separated at any time.

Based on the above and other objectives, the present invention proposes a surge separation circuit, which includes an edge signal generating device, an OR gate, an AND gate, a selection device, a first flip-flop and a second flip-flop. Wherein, the edge signal generator generates a rising edge signal from the input signal and the first clock signal, generates a falling edge signal from the input signal and the second clock signal, and the rising edge signal is latched at the first state of the first clock signal The input signal is obtained, and the falling edge signal is obtained by latching the input signal at the first state of the second clock signal, and the second clock signal is an inverse signal of the first clock signal.

The input of the OR gate is a rising edge signal and a falling edge signal, and the output of the OR gate is an OR logic signal. The input of the AND gate is a rising edge signal and a falling edge signal, and the output of the AND gate is an AND logic signal. The selection device receives the OR logic signal and the AND logic signal, and outputs the OR logic signal or the AND logic signal according to the selection signal. The first flip-flop receives the third clock signal and the output of the selection device to generate a selection signal, wherein the selection signal is obtained by latching the output of the selection device at the first state of the third clock signal, and the third clock signal is obtained by applying the first state of the third clock signal The signal generated by the time delay of the second clock signal. The second flip-flop receives the first clock signal and the output of the selection device, and generates a surge separation output signal, which is obtained by latching the output of the selection device when the first clock signal is in the first state.

The present invention uses the internal clock signal of the integrated circuit to separate the surge appearing on the input signal at the edge of the clock signal. The surge separation circuit of the present invention includes an edge signal generating device, an OR gate, an AND gate, and a selection gate. device, first trigger and second trigger. Utilizing the specific connection relationship and functions of the above-mentioned components, the present invention can filter out the surge whose cycle is equivalent to half of the internal clock signal, so that no matter whether the external input signal appears on the rising edge or the falling edge of the internal clock signal, No surge will appear in the output signal output of the surge separation, so as to overcome the shortcomings of the prior art.

In order to make the above-mentioned content and other objects, features and advantages of the present invention more comprehensible, an embodiment is given below and described in detail in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is the timing diagram of internal clock signal, external input signal and synchronous output signal of known technology;

Fig. 2 is a schematic diagram of a surge separation circuit according to an embodiment of the present invention;

FIG. 3 , FIG. 4 , FIG. 5 and FIG. 6 are timing diagrams of various signals in the surge separation circuit according to an embodiment of the present invention.

Detailed ways

As shown in FIG. 2 , it is a schematic diagram of a surge separation circuit, which is composed of an edge signal generating device 210 , an OR gate 220 , an AND gate 230 , a selection device 240 , a first flip-flop 250 and a second flip-flop 260 . Wherein, the edge signal generating device 210 generates a rising edge signal rs and a falling edge signal fs according to the input signal input, the first clock signal clk1 and the second clock signal clk2, and the rising edge signal rs is generated at the first time of the first clock signal clk1. state (in this embodiment, the positive edge end of the first clock signal clk1, the first state is represented by the positive edge end hereinafter) when the latch input signal input is obtained, and the falling edge signal fs is obtained at the positive edge end of the second clock signal clk2 It is obtained by latching the input signal input along the edge, wherein the second clock signal clk2 is an inverted signal of the first clock signal clk1.

The input of the OR gate 220 is the rising edge signal rs and the falling edge signal fs, and the output of the OR gate 220 is the OR logic signal os. The input of the AND gate 230 is the rising edge signal rs and the falling edge signal fs, and the output of the AND gate 230 is the AND logic signal as. The selection device 240 receives the OR logic signal os and the AND logic signal as, and outputs the OR logic signal os or the AND logic signal as according to the selection signal cs. The first flip-flop 250 generates the selection signal cs according to the third clock signal clk3 and the output es of the selection device 240, and the selection signal cs is obtained by latching the output es of the selection device 240 at the positive edge of the third clock signal clk3, The third clock signal clk3 is a signal generated by time delaying the second clock signal clk2. The second flip-flop 260 generates a burst separation output signal output according to the first clock signal clk1 and the output es of the selection device 240, and the burst separation output signal output is latched to the selection device 240 at the positive edge of the first clock signal clk1 The output es obtained.

The edge signal generating device 210 in FIG. 2 includes a first D-type flip-flop 211 and a second D-type flip-flop 212 . Wherein, the input end of the first D-type flip-flop 211 receives the input signal input, and the clock input end of the first D-type flip-flop 211 receives the first clock signal clk1, and the output end of the first D-type flip-flop 211 outputs a rising edge signal rs. The input terminal of the second D-type flip-flop 212 receives the input signal input, and the clock input terminal of the second D-type flip-flop 212 receives the second clock signal clk2, and the output terminal of the second D-type flip-flop 212 outputs the falling edge signal fs.

In addition, the selection device 240 in FIG. 2 may use a two-to-one multiplexer, and the first flip-flop 250 and the second flip-flop 260 may use D-type flip-flops. In other embodiments, the surge separation circuit further includes an inversion device 270 and a delay device 280, wherein the inversion device 270 inverts the first clock signal clk1 to generate the second clock signal clk2, and the delay device 280 inverts the first clock signal clk1 to generate the second clock signal clk2, and the delay device 280 converts The second clock signal clk2 is time-delayed to generate the third clock signal clk3.

Figure 3 is a timing diagram of each signal in the surge separation circuit. In this embodiment, when the selection signal cs=0, the output es of the selection device 240 is an AND logic signal as; when the selection signal cs=1, the output es of the selection device 240 is an OR logic signal os.

As shown in Figure 3, when the input is normal high (normal high), that is, normal logic 1, under normal circumstances, the rising edge signal rs=1, the falling edge signal fs=1, or the logic signal os=1, and The logic signal as=1, the output of the selection device 240 es=1, the selection signal cs=1, and the burst separation output signal output=1.

If at the rising edge of the first clock signal clk1, a surge of 0 occurs in the input signal input (as shown in 302 in FIG. 3 ), then the rising edge signal rs=0, the falling edge signal fs=1, or logic Signal os=1, and logic signal as=0, at this moment, because selection signal cs=1, then the output es=or logic signal os=1 of selection device 240, after the next falling edge after the surge arrives, When the first flip-flop 250 was triggered according to the third clock signal clk3, the selection signal cs=the output es=0 of the selection device 240, at this time, the output es=and logic signal as=0 of the selection device 240, and after the surge After the next rising edge of , when the second flip-flop 260 is triggered according to the first clock signal clk1, the output signal output=the output of the burst separation=the output es of the selection device 240=1.

Fig. 4, Fig. 5 and Fig. 6 are also timing diagrams of each signal of the surge separation circuit. In this embodiment, when the selection signal cs=0, the output es of the selection device 240 is an AND logic signal as; when the selection signal cs=1, the output es of the selection device 240 is an OR logic signal os. Wherein, as shown in FIG. 4, when the input is a normal high potential (normal high), that is, a normal logic 1, and at the falling edge of the first clock signal clk1, a surge of 0 appears in the input signal input ( A timing diagram of each signal shown in 402 of FIG. 4 ). As shown in FIG. 5, when the input is a normal low potential (normal low), that is, a normal logic 0, and at the rising edge of the first clock signal clk1, a surge of 1 appears in the input signal input (such as A timing diagram of each signal shown in 502 of FIG. 5 . As shown in Figure 6, when the input is a normal low potential (normal low), that is, a normal logic 0, and at the falling edge of the first clock signal clk1, a surge of 1 appears in the input signal input (as shown in the figure The timing diagram of each signal shown in 602 of 6), and the action mode of each signal in Figure 4, Figure 5 and Figure 6 can be described according to the action mode of each signal described in Figure 3, and will not be repeated here.

It can be seen from Fig. 3, Fig. 4, Fig. 5 and Fig. 6 that no matter whether the external input signal has a surge on the rising edge or the falling edge of the internal clock signal, the output signal output of the surge separation will not have any surge.

In summary, the present invention adopts the internal clock signal of the integrated circuit, and separates the surge appearing on the input signal at the edge of the clock signal, so the present invention can filter out the surge equivalent to half a cycle of the internal clock signal. surge. Therefore, use the integrated circuit of the present invention to no longer appear following shortcoming: the chip control logic disorder that uses known technology to take place; Affect the stability of chip performance; The designed circuit has wrong logic output.

Although the present invention discloses preferred embodiments as above, it is not intended to limit the present invention, and those skilled in the art can easily realize other advantages and make modifications, so without departing from the claims and the equivalent scope Without limiting the spirit and scope of the general concepts, the invention is not limited to the specific details, representative apparatus, and illustrative examples shown and described herein.

Claims (7)

1. A surge separation circuit, characterized in that, the surge separation circuit comprises: An edge signal generating device generates a rising edge signal according to an input signal and a first clock signal, and generates a falling edge signal according to the input signal and a second clock signal, and the rising edge signal is generated on the first clock signal The falling edge signal is obtained by latching the input signal at a first state of the second clock signal, wherein the second clock signal is the first clock signal The inverse signal of the signal; An OR gate, the OR gate receives the rising edge signal and the falling edge signal, and outputs an OR logic signal; An AND gate, the AND gate receives the rising edge signal and the falling edge signal, and outputs an AND logic signal; A selection device receives the OR logic signal and the AND logic signal, and outputs one of the OR logic signal and the AND logic signal according to a selection signal; A first flip-flop receives a third clock signal and the output signal of the selection device, and generates the selection signal, which is generated by latching the output signal of the selection device when the third clock signal is in the first state. Obtaining, wherein the third clock signal is a signal generated by time delaying the second clock signal; and A second flip-flop receives the first clock signal and the output signal of the selection device, and generates a burst separation output signal, and the burst separation output signal is latched at the first state of the first clock signal Select the output signal of the device obtained. 2. surge separation circuit as claimed in claim 1, is characterized in that, described edge signal generation device comprises: A first edge trigger, the input end of which receives the input signal, the clock input end receives the first clock signal, and the output end outputs the rising edge signal; The input terminal of a second edge trigger receives the input signal, the clock input terminal receives the second clock signal, and the output terminal outputs the falling edge signal. 3. The surge separation circuit according to claim 2, wherein both the first edge trigger and the second edge trigger are D flip-flops. 4. The surge separation circuit according to claim 1, wherein the selection device is a two-to-one multiplexer. 5. The surge separation circuit according to claim 1, wherein both the first flip-flop and the second flip-flop are D flip-flops. 6. The surge separation circuit according to claim 1, characterized in that, the surge separation circuit further comprises an inversion device, and the inversion device inverts the first clock signal to generate the second clock signal . 7. The surge separation circuit as claimed in claim 1, further comprising a delay device, the delay device delays the second clock signal to generate the third clock signal.

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