CN100492898C - Transmission Line Termination Compensation Circuit - Google Patents

Abstract

The invention provides a compensation circuit of a terminal resistor in a chip, which can generate accurate terminal impedance to compensate errors of the terminal impedance caused by changes of manufacturing process, temperature, voltage and the like. The invention is characterized in that n +1 signals with 2 are adjusted in a digital mode⁰×k×r、2¹×k×r、2²×k×r、…、2ⁿThe invention discloses a parallel resistor array with resistance values of multiplied by k multiplied by r, which is characterized in that n +1 switching devices connected with the n +1 resistors in series are opened or closed, so that the resistor array presents terminal impedance which is k/m times (k is more than 0, m is more than or equal to 1) of external impedance, and the parallel resistor array is not limited to only generating the terminal impedance which is equal to the external impedance or a fixed multiple of the external impedance.

Description

Transmission Line Termination Compensation Circuit

technical field

The present invention relates to a terminal resistance of a transmission line, in particular to a terminal resistance compensation circuit in a digital adjustment mode.

Background technique

In the past two decades, fueled by the proliferation of various computing devices, computing power has grown at a geometric progression rate. With the improvement of computing power, the speed of signal transmission between various devices has also begun to reach above GHz, and at such a high speed, any wire for signal transmission, such as coaxial cable, microstrip line, etc. , can be regarded as a so-called transmission line with a resistance component and an inductance component connected in series, and a capacitance component and a conductance component connected in parallel between the wires.

When the signal reaches the end point at high speed on the transmission line and wants to enter the terminal component (such as CPU, memory, etc. IC) to work, the characteristic impedance of the transmission line itself must match the internal impedance of the terminal component to make the reflection coefficient is zero, so as not to cause signal reverberation (ringing) and distortion (distortion). Generally speaking, the impedance matching of the transmission line is to provide a termination resistor with the same impedance at the end of the transmission line to the ground, as shown in Figure 1, if the characteristic impedance Zo of the transmission line T is 28 ohms (ohm) , and the impedance Zt of the terminal resistor R is also 28 ohms (ohm), the signal S will experience minimal reflection and distortion, so the integrity of the signal under high-speed transmission can be greatly improved. However, with such an arrangement, only 50% of the power of the signal S will reach the end of the transmission line, so in practice, more careful arrangements will be made for the impedance of the terminal resistor in order to achieve a balance within several conditions such as power and distortion.

There are two known configurations of terminal resistors: off-chip and on-chip or on-die. The off-chip approach will increase the complexity of the circuit board layout. At the same time, due to the difference in the circuit (trace), there will be a so-called impedance discontinuity, and these impedance discontinuities will cause reflections to occur. In contrast, the on-chip approach generally has better signal integrity and is suitable for higher-speed applications. The key point of using the terminal resistor in the chip is to be able to accurately adjust (calibrate) the impedance of the terminal resistor, but because of the variation in temperature, process, and voltage (affected by noise), generally known terminal resistors using CMOS process The error can reach 30%.

Contents of the invention

The main purpose of the present invention is to propose a compensation circuit for terminal resistors to solve the disadvantages of known internal terminal resistors. The terminal resistance compensation circuit proposed by the present invention can generate accurate terminal impedance to compensate the error of terminal impedance caused by changes in manufacturing process, temperature and voltage.

Another object of the present invention is to propose a compensation circuit for terminal resistance, the terminal impedance produced is k/m times (k>0, m≥1) of the external impedance Re _{ext (} that is, the characteristic impedance of the transmission line to be matched) ), not limited to only produce a terminal impedance equal to the external impedance, or a fixed multiple of the external impedance, so there is greater flexibility in the design when weighing factors such as power and distortion.

The biggest feature of the present invention is to digitally adjust the resistor array comprising n+1 (n≥1) resistors connected in parallel, and the n+1 resistors have 2 ⁰ ×k×r, 2 ¹ ×k×r, 2 ² ×k×r, ..., 2 ⁿ ×k×r and other impedance values, where r and k are impedance values and multiples determined in advance. In the present invention, the n+1 switch devices connected in series with the n+1 resistors are turned on or off, so that the resistor array exhibits a terminal impedance of R _ext ×k/m.

The present invention will be described in detail in conjunction with the accompanying drawings and specific embodiments.

Description of drawings

FIG. 1 shows a schematic diagram of a transmission line and a terminating resistor;

2 is a schematic diagram of a terminal resistor array according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a calibration circuit according to an embodiment of the invention.

in the picture

1 chip

10 Switching device 12 Switching device

20 Resistor 22 Resistor

30 Contact pad 40 Comparison counting device

50 reference resistor 60 resistor

V _DD internal power supply 70 resistor

_R oTerminal impedance b ₀ ～b _nControl signal

S signal R _o1 impedance

Zt Termination Resistance Impedance Zo Transmission Line Characteristic Impedance

Detailed ways

The terminal resistance compensation circuit proposed by the present invention is implemented inside the chip 1 to provide a terminal impedance matching the high-speed I/O transmission line outside the chip. The terminal resistance compensation circuit mainly includes a calibration circuit and a terminal resistance array.

FIG. 2 is a schematic diagram of a termination resistor array according to an embodiment of the invention. As shown in Figure 2, the terminal resistor array of the present invention includes n+1 (n≥1) resistors 20 connected in parallel, and the impedances of the n+1 resistors 20 are respectively 2 ⁰ ×k×r, 2 ¹ × ^k ×r, 2 ² ×k×r, . Each resistor 20 is connected in series with a switching device 10 . The n+1 switching devices 10 may be switching switches implemented by PMOS or NMOS. These switches 10 are in a short-circuit or open-circuit state, which are determined by b ₀ , b ₁ , b ₂ , . . . , b Controlled by _{the n} control signal. R _o is the terminal impedance of the resistor array seen from the outside of the chip to compensate the external impedance R _ext . A contact pad (pad) 30 is a contact point between a transmission line (not numbered) and the chip 1 .

Please note that the control signals b ₀ , b ₁ , b ₂ ,..., b _n are output by the tuning circuit, that is to say, the opening or closing of each switching device is determined by the tuning circuit . For example, if the output signal of the adjustment circuit is b ₀ short circuit, b ₁ open circuit, b ₂ open circuit, and b ₃ ~ b _n are all short circuited, the terminal impedance R _o generated by the present invention will be 2 ⁰ × k × r , 2 ³ ×k×r, 2 ⁴ ×k×r, ..., 2 ⁿ ×k×r are connected in parallel. The tuning circuit described in detail below will make R _o and the external impedance R _ext have the following relationship:

R _o =R _ext ×k/m

Among them, m (m≥1) and k are parameters determined in advance. By properly selecting these parameter values, the terminal impedance R _o generated by the present invention can be flexibly changed according to the needs of the designer. _Therefore , the present invention is not limited to generating the terminal impedance R o equal to the external impedance R _ext or a fixed multiple of the external impedance R _ext , so the design can balance factors such as power and distortion and have greater flexibility.

FIG. 3 is a schematic diagram of a calibration circuit according to an embodiment of the invention. As shown in Figure 3, the calibration circuit also includes a comparison resistor array with the same structure as the terminal resistor array. This comparison resistor array also includes n+1 resistors 22 connected in parallel. The impedances of the n+1 resistors 22 are respectively 2 ⁰ ×r, 2 ¹ ×r, 2 ² ×r, ..., 2 ⁿ ×r, the n+1 resistors 22 are arranged in sequence according to the magnitude of impedance. Each resistor 22 is connected in series with a switching device 12 . The n+1 switching devices 12 and the switching devices 10 shown in FIG. 2 are all switched by control signals b ₀ , b ₁ , b ₂ , . . . , b _n . R _o1 is the impedance presented by this resistor array. Please note that the resistor 20 of the terminal resistor array and the resistor 22 of the comparison resistor array are arranged in the same size order, so the control signal b _j (0≤j≤n) controls the sum resistor 2 ^j ×k×r at the same time Switching device 10 connected in series, and switching device 12 connected in series with resistor 2 ^j ×r.

The other parts of the calibration circuit constitute a comparison and counting circuit (not labeled), wherein the comparison and counting device 40 takes the voltages of points A and B as input, and uses the control signals b ₀ , b ₁ , b ₂ , . . . , b _n are outputs. The comparison and counting device 40 contains a counter (not shown in the figure). When the voltages of points A and B are not equal, the counter will start counting up from 0. The comparison and counting device 40 will convert the value of the counter in binary form from b ₀ , b ₁ , b ₂ , . . . , b _n output. That is to say, the comparing and counting device 40 sequentially outputs 000..000, 000...001, 000...010, 000...011, etc. from b ₀ , b ₁ , b ₂ ,..., b _n wait. However, b ₀ , b ₁ , b _{2 , .} The counter will continue to count until R _o1 reaches a certain value, making the voltages of A and B equal.

In the comparison and counting circuit, the resistor 50 adopts the same impedance as the external impedance R _ext to be matched, and the resistor 70 adopts 1/m (m≥1) of the resistor 60 . With such an arrangement and the action of the aforementioned counter, when the voltages at points A and B are equal, the short circuit or disconnection of each switching device 12 caused by b ₀ , b ₁ , b ₂ ,..., b _n would result in:

R _o1 = R _ext /m

And because each resistor 20 of the terminal resistor array is k times the resistor 22 corresponding to the position in the comparison resistor array, and both share control signals b0, b1, b2, ..., bn, so:

Ro=Rext×k/m

The comparison and counting circuit can have multiple implementations. For example, the counter of the comparison and counting device 40 can use any suitable counter circuit, and the comparison of voltages can use known technologies such as differential amplifiers, which can be easily inferred by those skilled in the art. Therefore, This will not be repeated. The resistors 50, 60, 70 can adopt PMOS or other suitable implementations.

In general, the present invention uses b ₀ , b _{1 ,} b _{2 ,} . /m. Furthermore, the _same control _signals of b ₀ , b ₁ , b ₂ , _.

Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent modifications all falling within the protection scope of the present invention.

Claims (3)

1. A transmission line termination resistance compensation circuit is implemented inside a chip to provide a termination impedance matched with an external impedance of an external transmission line of the chip, the transmission line termination resistance compensation circuit comprising: A terminal resistor array, the terminal resistor array includes n+1 parallel first resistors, where n is greater than or equal to 1, and the impedances of the n+1 first resistors are 2 ⁰ ×k×r, 2 ¹ ×k respectively ×r, 2 ² ×k×r, ..., 2 ⁿ ×k×r, wherein, k and r are both greater than zero, the n+1 first resistors are arranged in sequence according to the impedance, each of the first The resistors are each connected in series with a first switching device, and the n+1 first switching devices are each in a short-circuit or open circuit state, and each of the n+1 first switching devices is connected to the n+1 first switching devices respectively. Each of the first switch devices is controlled by corresponding control signals b ₀ , b ₁ , b ₂ , ..., b _n , and the impedance of the terminal resistor array is the terminal impedance; and A calibration circuit, the calibration circuit further includes a comparison resistor array and a comparison counting circuit; the comparison and counting circuit is based on the n+1 control signals b ₀ , b ₁ , b ₂ , ..., b _n Output; the comparison resistor array includes n+1 second resistors connected in parallel; the impedances of the n+1 second resistors are 2 ⁰ ×r, 2 ¹ ×r, 2 ² ×r, ..., 2 ⁿ ×r; the n+1 second resistors are arranged in the same order as the impedance and the first resistors of the terminal resistor array; each second resistor is connected in series with a second switch device; the n+1 second switches Each of the devices is in a short-circuit or open-circuit state, and each of the n+1 second switching devices is controlled by a control signal b 0 , _{b 1 corresponding} to each of the n+1 second switching devices. , b ₂ ,..., b _n are controlled by; Wherein, the control signal b _j output by the comparison and counting circuit simultaneously controls the first switch device connected in series with the first resistor 2 ^j × k × r, and the second switch device connected in series with the second resistor 2 ^j × r, wherein , j is greater than or equal to 0, less than or equal to n; the comparison and counting circuit automatically converts the value of the counter included in the comparison and counting circuit to b ₀ , b ₁ , b ₂ , ..., according to the external impedance to be matched. b _n is output sequentially, and then the corresponding first and second switching devices are turned on and off until the impedance of the comparison resistor array is equal to 1/m of the external impedance, so that the voltages at both ends of the counter are equal, and then the terminal resistor array is obtained. The impedance is equal to k/m of the external impedance, where m is greater than or equal to 1. 2. The transmission line termination resistance compensation circuit as claimed in claim 1, wherein the first switch device is implemented in one of two modes: PMOS and NMOS. 3. The transmission line termination resistance compensation circuit as claimed in claim 1, wherein the second switching device is implemented in one of two modes: PMOS and NMOS.

Images