CN100490143C - Non-gated diode, manufacturing method and electrostatic discharge protection circuit applying non-gated diode - Google Patents

Abstract

An soi (silicon on insulator) ungated diode structure comprising: an insulator-based epitaxial silicon substrate having a substrate, an insulating layer and a silicon layer stacked in this order; the pair of isolation structures are positioned in the silicon layer, so that a well region is formed between the pair of isolation structures and in the silicon layer; the first type ion implantation area and the second type ion implantation area are positioned in the well region and are respectively adjacent to each isolation structure. The non-gated diode structure can be applied to an electrostatic discharge protection circuit to improve the electrostatic discharge protection capability of an integrated circuit product. In addition, the invention provides a manufacturing method of the NOT gate control diode structure.

Description

Non-gated diode, manufacturing method and electrostatic discharge protection circuit using the same

technical field

The present invention relates to a non-gated diode element, a manufacturing method and an electrostatic discharge protection circuit using the same, and in particular to a non-gated diode element utilizing a silicon on insulator (SOI) manufacturing process technology, A manufacturing method and an electrostatic discharge protection circuit applying the same.

Background technique

Silicon-on-insulator (SOI) manufacturing process technology is a potential main competitive technology in current low-voltage and high-speed applications, because compared with general large-scale (bulk) CMOS manufacturing processes, SOI manufacturing process technology has high isolation ( isolation), freedom from latch-up effects and lower junction capacitance, etc. Currently, for the SOI manufacturing process, electrostatic discharge protection (electrostatic discharge, ESD) is a technology that needs to be developed.

The level of protection an ESD protection circuit can provide depends on the amount of current that the ESD circuit can carry while clamping the voltage to a small voltage. During the entry of ESD pulses, thermal runaway and continuous crack damage can cause serious damage to internal circuit components. In SOI components, the thermal conductivity of the buried oxide layer of SOI is only about one percent of that of silicon; this makes the components more susceptible to overheating due to ESD, which accelerates thermal runaway .

Figure 1 shows a cross-sectional view of an SOI gated diode, which is an ESD protection circuit with CMOS on SOI. This structure was published by S. Voldman et al. in the journal "Proc. of EOS/ESD Symp.", 1996, pp.291-301. As shown in FIG. 1 , the SOI-gated diode is formed on an SOI substrate, which includes a substrate 10 , a buried oxide layer 12 and a silicon layer. A shallow trench isolation (STI) structure 14 is formed in the silicon layer. There is a P-type diffusion region (P+) 20 and an N-type diffusion region (N+) 16 between the STI isolation structures. Between the P-type diffusion region 20 and the N-type diffusion region 16 is an N-type well or a P-type well region 18 . If the well region 18 is implanted with N-type ions (N-), the P-type diffused region (P+) 20 and the N well (N-) 18 form an SOI diode; otherwise, if the well region 18 is implanted with P-type ions (P -), then the N-type diffusion region 20 (N+) and the P well (P-) 18 form an SOI diode. There is also a gate structure on the well region 18, which includes a P+ region 24 and an N+ region 22 (both function as a gate), a spacer wall 26, a gate oxide layer 28, and the like.

The P-type diffused region (P+) 20 and the N-type diffused region (N+) 16 are respectively connected to voltages V1 and V2, each serving as two voltage application terminals of the SOI diode. Taking the SOI diode formed by the P-type diffusion region (P+) 20 and the N well (N-) 18 as an example, if the voltage V1 is positive relative to the voltage V2, the SOI diode is forward biased; otherwise, if the voltage V2 is positive relative to the voltage V2 If the voltage V1 is positive, the SOI diode is reverse biased.

If the heat generated by the ESD voltage at the junction between the P-type diffusion region (P+) 20 /N-type well (N-) 18 is small, the SOI diode can withstand a relatively high ESD voltage. Heat is generated in a localized area of the PN junction. Most of the heat on the PN junction is Joule heat. Secondary breakdown occurs when the maximum temperature in the SOI diode reaches its intrinsic temperature T _intrinsic . Therefore, in order to obtain a better ESD protection level, it is necessary to reduce the power density without joule heating.

Contents of the invention

It is therefore an object of the present invention to propose a non-gated diode element with a low power density, a manufacturing method and an electrostatic discharge protection circuit using the same.

Another object of the present invention is to propose a non-gated diode element, manufacturing method and its electrostatic discharge protection circuit, this non-gated diode can be applied to the electrostatic protection circuit of the SOI circuit, and can improve its ESD withstand voltage Spend.

Another object of the present invention is to provide a non-gated diode element, a manufacturing method and an electrostatic discharge protection circuit using the same. The non-gated diode can be applied to SOI manufacturing process or large-scale CMOS manufacturing process.

In order to achieve the above and other objects, the present invention proposes a non-gated diode element structure, an electrostatic discharge protection circuit and a non-gated diode element manufacturing method using the non-gated diode element, which are briefly described as follows:

The present invention provides a non-gated diode structure of epitaxial silicon on insulator, comprising: an epitaxial silicon substrate on insulator, which has a substrate, an insulating layer and a silicon layer stacked in sequence; the isolation structure is located in the silicon layer, so that There is a well area between the pair of isolation structures and in the silicon layer; the first type ion implantation area and a second type ion implantation area are located in the well area and adjacent to each isolation structure respectively.

The present invention also proposes another non-gated diode structure of epitaxial silicon on insulator, including: epitaxial silicon on insulator substrate, which has a substrate, an insulating layer and a silicon layer stacked in sequence; for the isolation structure, located in the silicon layer, There are a first well region and a second well region between the pair of isolation structures and in the silicon layer, wherein the first well region is adjacent to the second well region; the first type ion implantation region and the second type ion implantation region are respectively Located in the first and second well regions and adjacent to each isolation structure respectively, so that the junction of the non-gated diode element of EPISI is the junction of the first and second well regions.

The invention also provides an electrostatic discharge protection circuit of the non-gated diode element, which is coupled between the input pad and the internal circuit. This protection circuit consists of the following components. The high voltage power supply line and the low voltage power supply line are both coupled to the internal circuit; the first diode has its anode coupled to the high voltage power supply line and its cathode coupled to a node; the second diode has its cathode coupled to to the low voltage power supply line and its anode is coupled to the node; the first diode string is composed of a plurality of diodes connected in series, wherein its anode is coupled to the high voltage power supply line and its cathode is coupled to the node; the second diode string , consisting of a plurality of diodes connected in series, the cathode of which is coupled to the low voltage supply line and the anode of which is coupled to a node, wherein each diode in the first diode string, each diode in the second diode string, At least one of the first diode and the second diode is a non-gated diode.

The ESD protection circuit of the non-gated diode element provides a discharge path through the first diode to the high voltage supply line when a positive voltage is applied to the input pad relative to the high voltage supply line. When a negative voltage is applied to the input pad with respect to the low voltage supply line, the electrostatic discharge protection circuit of the non-gated diode element provides a discharge path through the second diode to the low voltage supply line. When a negative voltage is applied to the input pad with respect to the high voltage supply line, the ESD protection circuit of the non-gated diode element provides a circuit via the second diode, the second diode string and the first diode string to Discharge path of high voltage supply lines. When a positive voltage is applied to the input pad with respect to the low voltage supply line, the ESD protection circuit of the ungated diode element provides an Discharge path to the low voltage supply line.

The invention also provides an electrostatic discharge protection circuit of the non-gated diode element, which is coupled between the output solder block and the pre-driver. This protection circuit consists of the following components. A high-voltage power supply line and a low-voltage power supply line are respectively coupled to the pre-driver; a first diode, whose anode is coupled to the high-voltage power supply line and whose cathode is coupled to a node; a second diode, whose The cathode is coupled to the low-voltage power supply line and its anode is coupled to the node; the first diode string is composed of a plurality of diodes in series, its anode is coupled to the high-voltage power supply line and its cathode is coupled to the node; the second diode The tube string is composed of a plurality of diodes connected in series, its cathode is coupled to the low voltage power supply line and its anode is coupled to the node; the first type MOS transistor, its source is coupled to the high voltage power supply line, and its drain is coupled to the node, the gate of which is coupled to the pre-driver; and a second type MOS transistor, the source of which is coupled to the low voltage supply line, the drain of which is coupled to the node, and the gate of which is coupled to the gate of the first type MOS transistor. wherein at least one of each diode in the first diode string, each diode in the second diode string, the first diode, and the second diode is a non-gated diode .

Wherein the ESD protection circuit of the non-gated diode element provides a discharge path via the first diode to the high voltage supply line when a positive voltage is applied to the output pad relative to the high voltage supply line. The ESD protection circuit of the ungated diode element provides a discharge path through the second diode to the low voltage supply line when a negative voltage is applied to the output pad relative to the low voltage supply line. When a negative voltage is applied to the input pad with respect to the high voltage supply line, the ESD protection circuit of the non-gated diode element provides an Discharge path to the high voltage supply line. When a positive voltage is applied to the output pad with respect to the low voltage supply line, the ESD protection circuit of the non-gated diode element provides a circuit through the first diode, the first diode string and the second diode string to Discharge path for low voltage supply lines.

The invention also proposes an electrostatic discharge protection circuit of the non-gated diode element, which is coupled between the input pad and the internal circuit. This protection circuit includes the following components. The high-voltage power supply line and the low-voltage power supply line are both coupled to the internal circuit; the first diode and a second diode are connected in series, wherein the anode of the first diode is coupled to a node, and the second and second diodes are connected in series. The cathode of the diode is coupled to the high-voltage power supply line; the third diode is connected in series with the fourth diode, wherein the anode of the third diode is coupled to the low-voltage power supply line, and the cathode of the fourth diode is coupled to the low-voltage power supply line. connected to the node; the first end of the resistor is coupled to the node and the second end is coupled to the internal circuit; the gate and source of the MOS transistor are coupled to the low voltage power supply line, and the drain is coupled to the first end of the resistor Two terminals; and an electrostatic discharge clamping circuit, coupled between the high-voltage power supply line and the low-voltage power supply line, wherein the above-mentioned electrostatic discharge clamping circuit is composed of a plurality of diodes connected in series, and its anode is coupled to the high-voltage power supply line and its anode is coupled to the high-voltage power supply line and its The cathode is coupled to a low voltage supply line, wherein each diode in the first diode string, each diode in the second diode string, at least one of the first diode, the second diode One of them is a non-gated diode.

The invention also provides a method for forming a non-gated diode of epitaxial silicon on insulator. Firstly, an epitaxial silicon substrate on insulator is provided, and the substrate, insulating layer and silicon layer are sequentially stacked; a pair of isolation structures are formed in the silicon layer, so that there is a well region between the pair of isolation structures and in the silicon layer. A first-type ion implantation region and a second-type ion implantation region are formed in the well region, and are respectively adjacent to each isolation structure.

The invention also provides a method for forming a non-gated diode of epitaxial silicon on insulator. Firstly, an epitaxial silicon-on-insulator substrate is provided, and the substrate, the insulating layer and the silicon layer are sequentially stacked. A pair of isolation structures are formed in the silicon layer. A first well region and a second well region are formed between the pair of isolation structures and in the silicon layer, wherein the first well region is adjacent to the second well region. Forming a first-type ion implantation region and a second-type ion implantation region, respectively located in the first and the second well region, and respectively adjacent to each isolation structure, so that the junction of the non-gated diode element of EPISI is The junction of the first and second well regions.

The present invention also provides a large-scale CMOS non-gated diode structure, including: a substrate with a well; a pair of isolation structures located in the substrate and in the well; a first-type ion implantation region located in the above-mentioned well Middle: a pair of second-type ion implantation regions located in the well and adjacent to each of the isolation structures, wherein the pair of second-type ion implantation regions are separated from the first-type ion implantation region by the well.

The present invention also provides a method for forming a large-scale CMOS non-gated diode, comprising: providing a substrate, forming a well in the substrate; forming a pair of isolation structures on the substrate, and the isolation structures are located in the well ; forming a first-type ion implantation region and the well, and between the pair of isolation structures; forming a pair of second-type ion implantation regions in the well region, and respectively adjacent to each of the isolation structures, each of the second The type ion implantation area is separated from the first type ion implantation area by the well respectively.

In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and understandable, preferred embodiments are listed below, accompanied by accompanying drawings, and described in detail as follows:

Description of drawings

Fig. 1 shows the sectional view of the gated diode (gated diode) of SOI, which is an ESD protection circuit with CMOS on SOI;

2 is a schematic cross-sectional view of a non-gated diode with an STI-blocking structure according to an embodiment of the present invention;

3A and 3B respectively show the top views of the STI isolation structure and the STI barrier structure;

4A to 4G show that the isolation structure with STI is produced by SOI manufacturing process;

5A to 5G show that the SOI manufacturing process is used to produce an isolation structure without STI;

6A to 6G show that the isolation structure with STI is produced by a large-scale CMOS manufacturing process;

7A to 7G show that the isolation structure without STI is produced by a large-scale CMOS manufacturing process;

Figure 8 shows a graph comparing the perimeter and ESD voltage of gated and non-gated SOI diodes;

9 is a schematic cross-sectional view of a non-gated diode with an STI blocking structure according to another embodiment of the present invention;

Fig. 10 shows the application of the non-gated diode element of the present invention on the input electrostatic discharge protection circuit;

Fig. 11 shows the application of the non-gated diode element of the present invention on the output electrostatic discharge protection circuit;

Fig. 12 shows another application of the non-gated diode element of the present invention on the input electrostatic discharge protection circuit; and

FIG. 13 shows that the ESD clamping circuit of FIG. 12 is realized by using the non-gated diode element of the present invention.

Label description

10 Substrate 12 Insulation layer

14 STI structure 16 N+ diffusion area

18 N-(or P-) well 20 P+ diffusion region

22 N+ area (gate) 24 P+ area (gate)

26 gap wall

40 Substrate 42 Insulation layer

44 STI structure 46 N+ diffusion region

48 N-(or P-) well 50 P+ diffusion region

60, 70 STI structure 62, 72 Insulation layer

64, 66, 68 ion implantation area

74, 76, 78 ion implantation area

100a/b Substrate 102a/b Insulation layer

104a/b Silicon layer 106a/b Silicon nitride layer

108a/b photoresist 110a/b STI structure

112a/b photoresist 114a/b well region

116a/b photoresist 118a/b ion implantation area

120 well area

200a/b substrate 202a/b well area

204a/b Silicon nitride layer 206a/b Photoresist

208a/b STI structure 210a/b Photoresist

212a/b ion implantation area 214a/b photoresist

216a/b ion implantation area 218 well area

300 Input bump 302 First diode string

304 Second diode string 306 Internal circuit

310 Output solder bump 312 First diode

314 Second diode string 316 Pre-driver circuit

320 Input solder block 322 Internal circuit

324 ESD clamp circuit

330 Input solder block 332 Internal circuit

334 diode string

Detailed ways

2 is a schematic cross-sectional view of a non-gated diode with an STI-blocking structure according to an embodiment of the present invention. As shown in FIG. 2 , the SOI gated diode is formed on an SOI substrate, which includes a substrate 40 , an insulating layer 42 and a silicon layer. The substrate 40 can be a P-type or N-type substrate, and the insulating layer 42 can be such as a buried oxide layer. SOI diodes with STI barrier structures are formed in the silicon layer. In the silicon layer, the SOI diode is formed between two STI structures 44 , that is, the ion-implanted regions constituting the SOI diode are separated by the two STI structures. A well region 50 of P-type or N-type ions (P-well or N-well) with a relatively light concentration is formed on the insulating layer 42 and between the two STI structures. In addition, a P-type diffusion region (P+) 48 and an N-type diffusion region (N+) 46 with higher concentrations are respectively formed at the corner of the P- or N-well 50 and adjacent to the two STI structures 44 .

Next, it will be explained that there are two types of STI structures formed in the SOI manufacturing process: STI-isolating structures and STI-blocking structures without STI. 3A and 3B respectively show the top views of the two structures. The following description will point out that the STI-isolating structure (STI-isolating structure) cannot form an SOI diode, because each ion-implanted region is isolated by the STI structure. As shown in FIG. 3A, several STI structures 60 are formed in the silicon layer on the insulating layer (buried oxide layer) 62, and the ion implantation regions 64 (N+), 66 (P+) and 68 (N+) are individually formed. Two of the STI structures 60 are not connected to each other, so the P-N junction of the diode cannot be formed. Next, as shown in FIG. 3B, two STI structures 70 are formed in the silicon layer on the insulating layer (buried oxide layer) 72, and the ion implantation regions 74 (N+), 76 (P+) and 78 (N+) are Both are formed between two STI structures 70, so a P-N junction of a diode can be formed.

4A to 4G show that the isolation structure with STI is manufactured by SOI manufacturing process, and FIG. 5A to FIG. 5G show that the isolation structure without STI is manufactured by SOI manufacturing process. It can be seen from the results that the ion implantation regions in the manufacturing process of the STI isolation structure are not connected to each other, so the P-N junction of the diode cannot be formed.

Referring to FIG. 4A and FIG. 5A , a substrate 100a, 100b is provided first. Next, insulating layers 102a, 102b are formed on the substrates 100a, 100b, respectively. Afterwards, a silicon layer is formed on the insulating layers 102a, 102b. The insulating layers 102a, 102b may be buried oxide layers. In addition, P-type ions are implanted into the silicon layer to form P-type well regions 104a and 104b. So far, the steps of the two manufacturing processes are still the same.

Next, referring to FIG. 4B and FIG. 4C , continue to form a pad oxide layer (pad oxide) 106b and a photoresist 108b, and expose the area where the STI structure is to be formed. Next, using the solder oxide layer 106b and the photoresist 108b as a mask, the P-type well (silicon layer) 106 is etched to form a trench, and then the solder oxide layer 106b and the photoresist 108b are removed. After that, the trench is filled with insulating material and planarized to form the STI structure. Referring to FIG. 4D, a photoresist 112b is then formed on part of the P-type well 104b and part of the STI structure 110b, and a P-type well region 104b surrounded by the STI structure is exposed. Next, an ion implantation step is performed to implant P-type ions into the exposed P-type well region 104b to form a P+-type region 114b. Finally, as shown in FIG. 4E, the photoresist 112b is removed. Next, as shown in FIG. 4F, a photoresist 116b is formed on the P+ region 114b, and an ion implantation step is performed. N-type ions are implanted into the exposed P-type well region to form an N+ region 118b. Finally, the photoresist 116b is removed, as shown in FIG. 4G.

Next, referring to FIG. 5B and FIG. 5C , continue to form a solder bump oxide layer 106 a and a photoresist 108 a, and expose the area where the STI structure is to be formed. Next, using the solder oxide layer 106b and the photoresist 108a as a mask, the P-type well (silicon layer) 104a is etched to form a trench, and then the solder oxide layer 106a and the photoresist 108a are removed. After that, the trench is filled with insulating material and planarized to form the STI structure. Referring to FIG. 5D, a photoresist 112a is then formed on part of the P-type well 104a and part of the STI structure 110a, and part of the P-type well region 104a is exposed. Next, an ion implantation step is performed to implant P-type ions into the exposed P-type well region 104a to form a P+-type region 114a. Finally, as shown in FIG. 5E, the photoresist 112a is removed. Next, as shown in FIG. 5F, a photoresist 116a is formed on the P+ region 114a, and an ion implantation step is performed. The photoresist 116a is slightly wider than the underlying overlying P+ region 114a. Next, N-type ions are implanted into the exposed P-type well region 104a to form an N+ region 118a. Finally, the photoresist 116a is removed, as shown in FIG. 5G. Since the photoresist 116a is slightly wider than the underlying overlying P+ region 114a, there will be a P-well region 120 between the N+ region 118a and the P+ region 114a, having a width SP.

As mentioned above, comparing FIG. 4G with FIG. 5G, it can be seen that only the STI-blocking structure (STI-blocking structure) manufacturing process can form the SOI diode.

The main parameters affecting the diode of the non-gated STI barrier structure applied to the SOI CMOS manufacturing process of the ESD protection circuit are the diode size, the ion implantation concentration in the well region, and the spacing (spacing, SP) between the cathode node and the anode node of the diode. The parameter of the interval SP not only affects the on-resistance of ESD discharge under forward bias of the diode, but also affects the reverse breakdown voltage of the diode. Therefore, by properly controlling the value of the spacing SP, any suitable reverse breakdown voltage value in the ESD protection circuit can be produced.

Figures 6A to 6G show that a diode element with an STI isolation structure is produced by a large-scale CMOS manufacturing process, and Figures 7A to 7G show that a diode element without an STI isolation structure is produced by a large-scale CMOS manufacturing process .

Referring to FIG. 6A and FIG. 7A, a substrate 200a, 200b is provided first. Next, P-type well regions 202a, 202b are respectively formed on the substrates 200a, 200b. So far, the steps of the two manufacturing processes are still the same.

Next, referring to FIG. 6B and FIG. 6C , continue to form a pad oxide layer (pad oxide) 204b and a photoresist 206b, and expose the area where the STI structure is to be formed. Next, using the solder oxide layer 204b and the photoresist 206b as a mask, the P-type well 202b is etched to form a trench, and then the solder oxide layer 204b and the photoresist 206b are removed. After that, the trench is filled with insulating material and planarized to form the STI structure. Referring to FIG. 6D, a photoresist 210b is then formed on part of the P-type well 202b and part of the STI structure 208b, and a P-type well region 202b surrounded by the STI structure is exposed. Next, an ion implantation step is performed to implant P-type ions into the exposed P-type well region 202b to form a P+-type diffusion region 212b. Finally, as shown in FIG. 6E, the photoresist 210b is removed. Next, as shown in FIG. 6F, a photoresist 214b is formed on the P+ diffusion region 212b, and an ion implantation step is performed. N-type ions are implanted into the exposed P-type well region 202b to form an N+ diffusion region 216b. Finally, the photoresist 214b is removed, as shown in FIG. 6G.

Next, referring to FIG. 7B and FIG. 7C , continue to form a solder bump oxide layer 204a and a photoresist 206a, and expose the area where the STI structure is to be formed. Next, using the solder oxide layer 204b and the photoresist 206a as a mask, the P-type well 202a is etched to form a trench, and then the solder oxide layer 204a and the photoresist 206a are removed. Afterwards, the trench is filled with insulating material and planarized to form the STI structure 208a. Referring to FIG. 7D, a photoresist 210a is then formed on part of the P-type well 202a and part of the STI structure 208a, and part of the P-type well region 202a is exposed. Next, an ion implantation step is performed to implant P-type ions into the exposed P-type well region 202a to form a P+-type region 212a. Finally, as shown in FIG. 7E, the photoresist 210a is removed. Next, as shown in FIG. 7F, a photoresist 214a is formed on the P+ region 212a, and an ion implantation step is performed. The photoresist 214a is slightly wider than the underlying overlying P+ region 212a. Next, N-type ions are implanted into the exposed P-type well region 202a to form an N+ region 216a. Finally, the photoresist 212a is removed, as shown in FIG. 7G. Since the photoresist 214a is slightly wider than the underlying overlying P+ region 212a, there will be a P-well region 218 between the N+ region 216a and the P+ region 212a, having a width SP.

As mentioned above, comparing FIG. 6G with FIG. 7G, it can be seen that only the STI-blocking structure (STI-blocking structure) manufacturing process can form adjacent diode structures.

The main parameters affecting the diode of the non-gated STI barrier structure applied to the large-scale CMOS manufacturing process of the ESD protection circuit are the diode size, the concentration of ion implantation in the well region, and the spacing (spacing, SP) between the cathode node and the anode node of the diode. The parameter of the interval SP not only affects the on-resistance of ESD discharge under forward bias of the diode, but also affects the reverse breakdown voltage of the diode. Therefore, by properly controlling the value of the spacing SP, any suitable reverse breakdown voltage value in the ESD protection circuit can be produced.

Figure 8 shows a graph comparing perimeter length and ESD voltage for gated and non-gated SOI diodes. Several conclusions can be drawn from the figure. First: The longer the circumference of the diode, the greater the ESD discharge voltage the component can withstand, and the better it can protect the internal circuit. Second: Obviously, the ESD voltage that non-gated SOI diodes can withstand is greater than that of gated SOI diodes (SOI lubistor diodes). Since the relationship between ESD robustness and the circumference of the diode is linear. Therefore, it is easy to use the SOI non-gated diode of the present invention to estimate and design the ESD level of the electrostatic discharge protection circuit.

9 is a schematic cross-sectional view of a non-gated diode without an STI isolation structure according to another embodiment of the present invention. As shown in FIG. 9 , the SOI gated diode is formed on an SOI substrate, which includes a substrate 90 , an insulating layer 92 and a silicon layer. The substrate 90 can be a P-type or N-type substrate, and the insulating layer 92 can be such as a buried oxide layer. SOI diodes without STI isolation structures are formed in the silicon layer. In the silicon layer, the SOI diode is formed between two STI structures 94 , that is, the ion implantation regions constituting the SOI diode are separated by the two STI structures. Two adjacent well regions of P-type and N-type ions (P-well or N-well) with relatively light concentrations are formed on the insulating layer 92 and between the two STI structures. In addition, a P-type diffusion region (P+) 96b and an N-type diffusion region (N+) 96a with higher concentrations are formed outside the P- and N-well regions 98b, 98a and the STI structure 94, respectively. The difference between this embodiment and the embodiment of FIG. 2 is that the PN junction of the SOI non-gated diode shown in FIG. 9 is located in the middle of the entire structure, while the PN junction shown in FIG. 2 is located at one side.

Next, several examples are used to illustrate the ESD protection circuit using the SOI non-gated diode of the present invention.

FIG. 10 is an ESD protection circuit showing the SOI non-gated diode of FIG. 2 or FIG. 9 to which the present invention is applied. As shown in Figure 10, the ESD protection circuit includes an input pad (input pad) 300, a first diode D1 and a second diode D2, a first diode string 302, a second diode string 304 , the input resistance R, and the high voltage supply line (Vdd voltage supply rail) Vdd and the low voltage supply line (Vssvoltage supply rail) Vss. The internal circuit 306 is connected between the high voltage power supply line Vdd and the low voltage power supply line Vss and the input resistor R. The cathode of the first diode D1 is connected to Vdd, and the anode is connected to the solder bump 300 ; the anode of the second diode D2 is connected to Vss, and the cathode is connected to the solder bump 300 . The first diode string 302 is composed of a plurality of diodes Du1 , Du2 , . The second diode string 304 is composed of a plurality of diodes Dd1 , Dd2 , . The first diode D1 , the second diode D2 , and each diode in the first and second diode strings 302 / 304 may be the SOI non-gated diodes shown in FIG. 2 or FIG. 9 . In addition, the input resistor R can also be connected to an input buffer (not shown) in the internal circuit 306 .

Next, the working mode of the ESD protection circuit in FIG. 10 will be described. When an ESD event with a positive voltage relative to the high voltage supply line Vdd is input to the input pad 300, the first diode D1 is forward biased; and because the low voltage supply line Vss is floating, the second diode Tube D2 has no effect. Therefore, the ESD event (voltage) will be discharged to the high voltage supply line Vdd via the first diode D1. Similarly, when an ESD event with a negative voltage relative to the low-voltage power supply line Vss is input to the input pad 300, the second diode D2 is forward-biased; and because the high-voltage power supply line Vdd is floating, the second diode D2 A diode D1 has no effect. Therefore, the ESD event (voltage) will be discharged to the low voltage supply line Vss via the second diode D2.

When an ESD event with a negative voltage relative to the high voltage supply line Vdd is input to the input pad 300, the first diode D1 is reverse biased. Since the low voltage supply line Vss is floating, the voltage on Vss will follow the negative voltage applied to the input pad 300 . Due to the forward conduction voltage and forward conduction resistance of the second diode D2 , there will be a slight voltage difference between Vss and the input pad 300 . At this time, the first diode string 302 (Du1, Du2, ..., Dun) is forward biased, so the ESD discharge current will pass through the first diode string 302 (Du1, Du2, ..., Dun ) is discharged to Vdd.

When an ESD event with a positive voltage relative to the low voltage supply line Vss is input to the input bump 300, the second diode D2 is reverse biased. Because the high voltage supply line Vdd is floating, the voltage on Vdd will keep up with the positive voltage applied to the input pad 300 . Due to the forward conduction voltage and forward conduction resistance of the first diode D1 , there will be a slight voltage difference between Vdd and the input pad 300 . At this time, because the second diode strings 304 (Dd1, Dd2, . Ddn) is discharged to Vss.

FIG. 11 shows an ESD protection circuit applying the SOI non-gated diode of FIG. 2 or FIG. 9 of the present invention. As shown in Figure 11, the ESD protection circuit comprises an output pad (output pad) 310, a first diode D1 and a second diode D2, a first diode string 312, a second diode string 314, PMOS transistor Mp, NMOS transistor Mn, high voltage supply line (Vdd voltage supply rail) Vdd and low voltage supply line (Vss voltage supply rail) Vss. The pre-driver circuit 316 is connected between the high voltage power supply line Vdd and the low voltage power supply line Vss and the gates of the PMOS transistor Mp and the NMOS transistor Mn. The cathode of the first diode D1 is connected to Vdd, and the anode is connected to the solder bump 310 ; the anode of the second diode D2 is connected to Vss, and the cathode is connected to the solder bump 310 . The first diode string 312 is composed of a plurality of diodes Du1 , Du2 , . The second diode string 314 is composed of a plurality of diodes Dd1, Dd2, . The source of the PMOS transistor Mp is connected to Vdd, and the source of the NMOS transistor Mn is connected to Vss. The drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn are connected together to the pad 310 . The above-mentioned first diode D1, second diode D2, and each diode in the first and second diode strings 302/304 may be SOI non-gated diodes as shown in FIG. 2 or FIG. 9 mentioned above.

Next, the working mode of the ESD protection circuit in FIG. 11 will be described. When an ESD event with a positive voltage relative to the high voltage supply line Vdd is input to the output pad 310, the first diode D1 is forward biased; and because the low voltage supply line Vss is floating, the second diode Tube D2 has no effect. Therefore, the ESD event (voltage) will be discharged to the high voltage supply line Vdd via the first diode D1. Similarly, when an ESD event with a negative voltage relative to the low-voltage power supply line Vss is input to the input pad 310, the second diode D2 is forward-biased; and because the high-voltage power supply line Vdd is floating, the second diode D2 A diode D1 has no effect. Therefore, the ESD event (voltage) will be discharged to the low voltage supply line Vss via the second diode D2.

When an ESD event with a negative voltage relative to the high voltage supply line Vdd is input to the output bump 310, the first diode D1 is reverse biased. Since the low voltage supply line Vss is floating, the voltage on Vss will follow the negative voltage applied to the output pad 310 . At this moment, because the first diode strings 312 (Du1, Du2, . Dun) is discharged to Vdd.

When an ESD event with a positive voltage relative to the low voltage supply line Vss is input to the output pad 310, the second diode D2 is reverse biased. Since the low voltage supply line Vdd is floating, the voltage on Vdd will keep up with the positive voltage applied to the output pad 310 . At this time, because the second diode string 314 (Dd1, Dd2, . Ddn) is discharged to Vss.

FIG. 12 is an ESD protection circuit showing the SOI non-gated diode of FIG. 2 or FIG. 9 to which the present invention is applied. As shown in Figure 12, the ESD protection circuit includes an input pad (input pad) 320, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, an input Resistor R, high voltage supply line (Vdd voltage supply rail) Vdd, low voltage supply line (Vss voltage supply rail) Vss, NMOS transistor Mn and ESD clamp circuit (ESD clamp circuit) 324 . The internal circuit 322 is connected between the high-voltage power supply line Vdd and the low-voltage power supply line Vss, the input resistor R, and the drain of the NMOS transistor Mn. The first diode D1 and the second diode D2 are connected in series, wherein the anode of the first diode D1 is connected to the input pad 330 , and the cathode of the second diode D2 is connected to Vdd. The third diode D3 and the fourth diode D4 are connected in series, wherein the anode of the third diode D3 is connected to Vss, and the cathode of the fourth diode D4 is connected to the input pad 320 . One end of the input resistor R is connected to the solder bump 320 and the other end is connected to the drain of the NMOS transistor Mn and the internal circuit 322 . The gate and source of the NMOS transistor Mn are connected to Vss together. The above-mentioned diodes D1 , D2 , D3 and D4 can all be SOI non-gated diodes as shown in FIG. 2 or FIG. 9 .

The operation of the circuit in FIG. 12 is basically the same as that in FIG. 10 or FIG. 11 , so it will not be further described here. As shown in Figure 12, the first and second diodes D1, D2 are used to replace the diode D1 in Figure 10 or Figure 11, and the third and fourth diodes D3, D4 are used to replace the diode D1 in Figure 10 or Figure 11 Diode D2 in 11. Assume that the parasitic junction capacitance of the diode D1 is C1, the parasitic junction capacitance of the diode D2 is C2, the parasitic junction capacitance of the diode D3 is C3, and the parasitic junction capacitance of the diode D4 is C4. The input capacitance Cin in FIG. 10 is C1+C2, and the input capacitance Cin' in this embodiment (FIG. 12) is [C1C2/(C1+C2)]+[C3C4/(C3+C4)]. If the diodes D1, D2, D3 and D4 are all the same, it means C1=C2=C3=C4=C. Then it can be obtained that Cin=2C, and Cin'=C. Therefore, the input capacitance of the example shown in FIG. 12 is reduced, which also results in a smaller RC time constant. By reducing the input delay, the ESD protection circuit can be applied to high frequency (high frequency, HF) circuits.

FIG. 13 shows a modified example of FIG. 12 . A diode string 334 is formed between Vdd and Vss, and the diode string 334 is used as an ESD clamping circuit. The diode string 334 includes diodes DP1 , Dp2 , .

Therefore, the advantages of the present invention are as follows:

1. The non-gated diodes of the present invention are fully compatible with the manufacturing process. That is, it is applicable regardless of the SOICMOS manufacturing process (as shown in FIGS. 5A to 5G ) or the large-scale CMOS manufacturing process (as shown in FIGS. 7A to 7G ).

2. The SOI non-gated diode provided by the present invention has lower power density due to having more PN junction regions than the gated diode.

3. Since there are more PN junction regions than the gate control diode, the SOI non-gate control diode provided by the present invention has a higher degree of ESD resistance.

4. The SOI non-gated diode provided by the present invention can be used in mixed voltage and analog/digital applications. In addition, the SOI non-gated diode provided by the present invention can be used as an I/O ESD protection circuit, and as a protection circuit between Vdd and Vss in the case of forward bias.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the spirit and scope of the present invention, can carry out various Therefore, the protection scope of the present invention shall be determined by the appended claims.

Claims (47)

1. the non-gate diode structure of an insulator-base epitaxial silicon comprises:

One insulator-base epitaxial silicon substrate comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn;

A pair of isolation structure is arranged in this silicon layer, makes between this is to isolation structure with in this silicon layer to have a well region;

One first type ion implanted region and one second type ion implanted region are arranged in this well region and are close to respectively this isolation structure respectively.

2. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.

3. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this well region injects the P type ion of low concentration.

4. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this well region injects the N type ion of low concentration.

5. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this insulating barrier is the flush type oxide layer.

6. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 1, wherein this is a fleet plough groove isolation structure to isolation structure.

7. the non-gate diode structure of an insulator-base epitaxial silicon comprises:

One insulator-base epitaxial silicon substrate comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn;

A pair of isolation structure is arranged in this silicon layer, makes between this is to isolation structure with in this silicon layer to have one first well region and one second well region, and wherein this first well region is adjacent with this second well region;

One first type ion implanted region and one second type ion implanted region, lay respectively at this first with this second well region in, and next-door neighbour's this isolation structure respectively respectively, with this make in the non-gate diode element of this insulator-base epitaxial silicon become this first with the knot of this second well region.

8. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.

9. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 8, wherein this first injects the P type and the N type ion of low concentration respectively with this second well region.

10. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this insulating barrier is the flush type oxide layer.

11. the non-gate diode element of insulator-base epitaxial silicon as claimed in claim 7, wherein this is a fleet plough groove isolation structure to isolation structure.

12. the non-gate diode structure of extensive COMS comprises:

One substrate, this substrate has a trap;

A pair of isolation structure is arranged in this substrate and is arranged in this trap;

One first type ion implanted region is arranged in this trap, and between this is to isolation structure; And

The a pair of second type ion implanted region is arranged in trap and is close to respectively this isolation structure respectively, wherein should separate with this first type ion implanted region with this trap respectively the second type ion implanted region.

13. the non-gate diode of extensive COMS as claimed in claim 12, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.

14. the non-gate diode of extensive COMS as claimed in claim 12, wherein this well region injects the P type ion of low concentration.

15. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element in 1 to 14, is coupled between an input welding block and the internal circuit, comprising:

An one High Voltage Power Supply line and a low voltage power supply line all are coupled to this internal circuit;

One first diode, its anode are coupled to this High Voltage Power Supply line and its negative electrode is coupled to a node;

One second diode, its negative electrode are coupled to this low voltage power supply line and its anode is coupled to this node;

One first diode string is made of the series connection of a plurality of diodes, and wherein its anode is coupled to this High Voltage Power Supply line and its negative electrode is coupled to this node; And

One second diode string, constitute by a plurality of diode series connection, its negative electrode is coupled to this low voltage power supply line and its anode is coupled to this node, wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.

16. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the positive voltage with respect to this High Voltage Power Supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this first diode to this High Voltage Power Supply line.

17. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the negative voltage with respect to this low voltage power supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this second diode to this low voltage power supply line.

18. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the negative voltage with respect to this High Voltage Power Supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this second diode, this second diode string and this first diode string discharge path to this High Voltage Power Supply line.

19. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein when the positive voltage with respect to this low voltage power supply line put on this input welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this first diode, this first diode string and this second diode string discharge path to this low voltage power supply line.

20. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of insulator-base epitaxial silicon (SOI).

21. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of mass metal oxide semiconductor.

22. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this first measure-alike with this second diode all has equal junction capacitance.

23. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 15, wherein this is first inequality with the size of this second diode, and its junction capacitance is all inequality.

24. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element among the 1-14, is coupled between an output welding block and the pre-driver, comprising:

An one High Voltage Power Supply line and a low voltage power supply line are couple to this pre-driver respectively;

One first diode, its anode are coupled to this High Voltage Power Supply line and its negative electrode is coupled to a node;

One second diode, its negative electrode are coupled to this low voltage power supply line and its anode is coupled to this node;

One first diode string is made of the series connection of a plurality of diodes, and wherein its anode is coupled to this High Voltage Power Supply line and its negative electrode is coupled to this node;

One second diode string is made of a plurality of diode series connection, and its negative electrode is coupled to this low voltage power supply line and its anode is coupled to this node;

One first type MOS transistor, its source electrode are couple to this High Voltage Power Supply line, and its drain electrode is couple to this node, and its grid is couple to this pre-driver; And

One second type MOS transistor, its source electrode are couple to this low voltage power supply line, and its drain electrode is couple to this node, and its grid is couple to this this grid of first type MOS transistor,

Wherein in each diode in this first diode string, each diode in this second diode string, this first diode, this second diode one of them is non-gate diode at least.

25. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the positive voltage with respect to this High Voltage Power Supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this first diode to this High Voltage Power Supply line.

26. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the negative voltage with respect to this low voltage power supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via the discharge path of this second diode to this low voltage power supply line.

27. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the negative voltage with respect to this High Voltage Power Supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this second diode, this second diode string and this first diode string discharge path to this High Voltage Power Supply line.

28. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein when the positive voltage with respect to this low voltage power supply line put on this output welding block, the electrostatic storage deflection (ESD) protection circuit of this non-gate diode element provided one via this first diode, this first diode string and this second diode string discharge path to this low voltage power supply line.

29. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of insulator-base epitaxial silicon (SOI).

30. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first with this second diode with this first with this second diode string in each diode be non-gate diode, and utilize the manufacturing process making of mass metal oxide semiconductor.

31. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first measure-alike with this second diode all has equal junction capacitance.

32. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this is first inequality with the size of this second diode, and its junction capacitance is all inequality.

33. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 24, wherein this first type MOS transistor is the PMOS transistor, and this second type MOS transistor is a nmos pass transistor.

34. an application rights requires the electrostatic storage deflection (ESD) protection circuit of any one described non-gate diode element among the 1-14, is coupled between an input welding block and the internal circuit, comprising:

An one High Voltage Power Supply line and a low voltage power supply line all are coupled to this internal circuit;

One first diode and one second diode are connected together, and wherein the anode of this first diode is coupled to a node, and the negative electrode of this second diode is coupled to this High Voltage Power Supply line;

One the 3rd diode and one the 4th diode are connected together, and wherein the anode of the 3rd diode is coupled to this low voltage power supply line, and the negative electrode of the 4th diode is coupled to this node; And

One ESD (Electrostatic Discharge) clamp circuit is coupled between this High Voltage Power Supply line and this low voltage power supply line,

Wherein this ESD (Electrostatic Discharge) clamp circuit is in series by a plurality of diodes, and its anode is couple to this High Voltage Power Supply line and its negative electrode is couple to this low voltage power supply line,

Wherein in the 3rd diode, the 4th diode, this first diode, this second diode one of them is non-gate diode at least.

35. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd with the 4th diode and this ESD (Electrostatic Discharge) clamp circuit in each diode be non-gate diode, and utilize the manufacturing process of insulator-base epitaxial silicon (SOI) to make.

36. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd is non-gate diode with the 4th diode, and utilizes the manufacturing process of mass metal oxide semiconductor to make.

37. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein each diode in this ESD (Electrostatic Discharge) clamp circuit is non-gate diode, and utilizes the manufacturing process of insulator-base epitaxial silicon (SOI) to make.

38. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein each diode in this ESD (Electrostatic Discharge) clamp circuit is non-gate diode, and utilizes the manufacturing process of mass metal oxide semiconductor to make.

39. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this second, the 3rd measure-alike with the 4th diode, all have equal junction capacitance.

40. the electrostatic storage deflection (ESD) protection circuit of non-gate diode element as claimed in claim 34, wherein this first, this is the second, the 3rd inequality with the size of the 4th diode, its junction capacitance is all inequality.

41. a method that forms the non-gate diode of insulator-base epitaxial silicon comprises:

One insulator-base epitaxial silicon substrate is provided, comprises that a substrate, an insulating barrier and a silicon layer pile up in regular turn; Form a pair of isolation structure in this silicon layer, make between this is to isolation structure with in this silicon layer to have a well region;

Form one first type ion implanted region and one second type ion implanted region in this well region, and be close to respectively this isolation structure respectively.

42. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.

43. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this well region injects the P type ion of low concentration.

44. the method for the non-gate diode of formation insulator-base epitaxial silicon as claimed in claim 41, wherein this well region silicon injects the N type ion of low concentration.

45. a method that forms the non-gate diode of extensive COMS comprises:

One substrate is provided, forms a trap in this substrate;

Form a pair of isolation structure in this substrate, described isolation structure is arranged in this trap;

Form one first type ion implanted region in this trap, and between this is to isolation structure; And

Form a pair of second type ion implanted region in this well region, and be close to respectively this isolation structure respectively, respectively this second type ion implanted region separates with this first type ion implanted region with this trap respectively.

46. the method for the non-gate diode of the extensive COMS of formation as claimed in claim 45, wherein this first type ion implanted region and this second type ion implanted region inject P type and N type ion respectively.

47. the method for the non-gate diode of the extensive COMS of formation as claimed in claim 45, wherein this well region injects the P type ion of low concentration.

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