CN100489784C - Multithreading microprocessor and its novel threading establishment method and multithreading processing system - Google Patents

Abstract

The invention discloses a fork instruction, which is executed on a multi-threaded microprocessor and occupies a time slot for issuing a single instruction. When executed in a parent thread, the fork instruction includes a first operand and a second operand, the first operand specifying an initial instruction fetch address of the new thread. The microprocessor allocates a context for the new thread, copies a first operand to a program counter of the new thread context, copies a second operand to a register of the new thread context, and schedules the new thread Execution to execute the fork instruction. If no new thread contexts are free to allocate, the microprocessor issues an exception to the fork instruction. The fork instruction of the present invention is very efficient because it does not need to copy the entire parent thread general registers to the new thread. The second operand may generally be used as a pointer to a data structure in memory containing the new thread's starting general purpose register set value.

Description

Multi-thread microprocessor and its new thread creation method and multi-thread processing system

Related Application Cross Reference

This application is a continuation-in-part (CIP) of the following pending US non-provisional patent application, which is hereby incorporated by reference in its entirety for all purposes.

Application number (docket number) Date of Application topic 10/684350 (MIPS.0188-01-US) 10/10/03 Mechanism for ensuring the quality of service of programs executing on a multithreaded processor 10/684348 (MIPS.0189-00-US) 10/10/03 Integrated mechanism for suspending and releasing computation threads executing in a processor (INTEGRATEDMECHANISM FOR SUSPENSION ANDDEALLOCATION OF COMPUTATIONALTHREADS OF EXECUTION IN APROCESSOR)

The aforementioned pending US non-provisional patent application claims the benefit of the following US provisional application, which is hereby incorporated by reference in its entirety for all purposes.

Application number (docket number) Date of Application topic 60/499180 (MIPS.0188-00-US) 8/28/03 Multithreaded Application Specific Extension (MULTITHREADING APPLICATIONSPECIFIC EXTENSION) 60/502358 (MIPS.0188-02-US) 9/12/03 MULTITHREADING APPLICATION SPECIFIC EXTENSION TO A PROCESSOR ARCHITECTURE 60/502359 (MIPS.0188-03-US) 9/12/03 MULTITHREADING APPLICATION SPECIFIC EXTENSION TO A PROCESSOR ARCHITECTURE

This application is related to the following concurrently filed US Nonprovisional Patent Application, which is hereby incorporated by reference in its entirety for all purposes.

Application number (docket number) Date of Application topic (MIPS.0189-01-US) 8/27/04 Integrated mechanism for suspending and releasing computation threads executing in a processor (INTEGRATED MECHANISM FORSUSPENSION AND DEALLOCATION OFCOMPUTATIONAL THREADS OFEXECUTION IN A PROCESSOR)

(MIPS.0193-00-US) 8/27/04 Mechanism for dynamically configuring virtual processor resources (MECHANISMS FOR DYNAMICCONFIGURATION OF VIRTUALPROCESSOR RESOURCES) (MIPS.0194-00-US) 8/27/04 APPARATUS, METHOD, AND INSTRUCTION FORSOFTWARE MANAGEMENT OFMULTIPLE COMPUTATIONALCONTEXTS IN A MULTITHREADEDMICROPROCESSOR FOR SOFTWARE MANAGEMENT OF MULTIPLE COMPUTATIONAL CONTEXTS IN A MULTITHREADED MICROPROCESSOR

technical field

The present invention relates generally to the field of multithreaded processors, and in particular to instructions for spawning new threads for execution in multithreaded processors.

Background technique

Microprocessor designers use a number of techniques to increase the performance of microprocessors. Most microprocessors operate using a clock signal that runs at a fixed frequency. Each clock cycle, the circuits in the microprocessor perform their respective functions. According to Hennessy and Patterson, the performance of a microprocessor is actually measured in terms of the time it takes to execute a program or programs. According to this view, the performance of a microprocessor is its clock frequency, the average number of clock cycles required to execute an instruction (or expressed as the average number of instructions executed per clock cycle), and the A function of the number of instructions executed in the program. Semiconductor scientists and engineers are continually enabling microprocessors to run at faster clock frequencies, primarily by reducing transistor size, which results in faster switching times. The number of instructions that can be executed is primarily limited by the tasks the program is trying to perform, although it is also affected by the microprocessor's instruction set architecture. Using the concept of architecture or organization, that is, improving the instructions that can be executed per clock cycle, and especially using the concept of parallel processing, can greatly improve performance.

A parallel processing concept for microprocessors that improves the number of instructions that can be executed per clock cycle and the clock frequency is pipelining, which overlaps the execution of multiple instructions in the microprocessor's pipeline stages. Ideally, each clock cycle, an instruction moves the pipeline down to a new stage that performs a different function of the instruction. Thus, although each individual instruction takes multiple clock cycles to complete, the average clock cycle required per instruction is reduced because the multiple cycles of the single instruction overlap each other. The performance improvement of the pipeline can be realized to the extent that the instructions in the program allow, that is, to the extent that an instruction is executed independently of its predecessor and is therefore executed in parallel with its predecessor, which is called the instruction level. Parallel processing. Another form of instruction-level parallelism used by today's microprocessors is to issue multiple instructions for execution per clock cycle, often referred to as superscalar microprocessors.

The foregoing discussion lends itself to individual instruction-level parallelism, however, there are limits to the performance improvements that can be achieved by using instruction-level parallelism. Various limitations arising from limited instruction-level parallelism and other performance-limiting issues have recently led to the use of block-level parallelism, or parallelism of instruction sequences or streams, which is often referred to as thread-level parallelism. Process, renewed interest. A thread is simply a sequence or stream of program instructions. A multithreaded microprocessor can execute multiple threads in parallel according to a scheduling policy that specifies fetching and issuing of instructions for various threads, such as interleaved, blocked, or concurrent multithreading. A multithreaded microprocessor usually allows multiple threads to share some functional units in the microprocessor at the same time (such as: instruction fetch and decode unit, cache, branch prediction unit, and read/store, integer processing, floating point processing , SIMD and other execution units). However, multithreaded microprocessors also include multiple sets of resources or contexts for storing the unique state of each thread, such as multiple program counters and general-purpose register banks, to facilitate fast switching between threads to fetch and issue ability to command.

An example of a performance limiting problem addressed by multi-threaded microprocessors is the fact that there is usually a relatively long latency when having to access memory external to the microprocessor due to high-speed access failures. For modern microprocessor based computers, it is quite common for the access time of a memory hit (cache hit) to be a multiple of one to two orders of magnitude of the access time of a cache memory hit. Thus, some or all of the pipeline stages of a single-threaded microprocessor must be suspended from performing any useless work for many clock cycles while the pipeline is stalled waiting for data from memory. A multi-threaded microprocessor can solve this problem by issuing instructions from other threads during the latency of memory fetches, thus enabling the next process in the pipeline to perform useful work, somewhat similar to a page fault An operating system that performs task switching, but at a finer granularity. Other examples could be pipeline stalls and their corresponding idle clock cycles due to branch mispredictions and accompanying pipeline flushes, or due to data dependencies, or due to long latency instructions such as split instructions. Likewise, the ability of a multi-threaded microprocessor to issue instructions from other threads to otherwise idle pipeline stages can greatly reduce the time required to execute a program or programs involving multiple threads. Another problem, especially in embedded systems, is said wasteful overhead associated with servicing interrupts. Typically, when an input/output device signals an interrupt event to the microprocessor, the microprocessor switches control of the interrupt service routine, which requires storing the current program state, servicing the interrupt, and Then restore to the current program state. A multi-threaded microprocessor provides the event service code with the ability to have its own thread with its own context. Thus, in response to an event signaled by an I/O device, the multithreaded microprocessor can quickly, possibly within a single clock cycle, switch back to the event service thread, thereby avoiding the overhead of conventional interrupt service routines.

Just as the degree of instruction-level parallelism dictates the extent to which the microprocessor utilizes the benefits of pipelining and excess instruction issuance, the degree of thread-level parallelism dictates the extent to which the microprocessor utilizes multi-threaded execution. An important characteristic of threads is that they are not dependent on other threads executing on a multithreaded microprocessor. A thread is not dependent on another thread such that instructions in that thread do not depend on instructions in other threads. The independent nature of threads enables the microprocessor to execute the instructions of each thread concurrently. That is, the microprocessor can issue instructions for one thread to the execution units without regard to the instructions of other threads being issued. As far as the threads access common data, the threads themselves must be programmed to ensure that data accesses are synchronized with each other to ensure correct operation, so that the microprocessor instruction issue stage does not need to be concerned with the dependencies.

As can be observed from the above description, a processor executing multiple threads simultaneously can reduce the time required to execute a program or programs comprising said multiple threads. However, there is an overhead associated with the creation and distribution of new threads for execution. That is, the microprocessor must spend useful time performing the necessary functions to create a new thread—typically allocating a context for the new thread and copying the parent thread's context to the new thread's context—and scheduling the new thread's Execution, for example, determines when the microprocessor starts fetching and issuing instructions from a new thread. The overhead time is similar to the task switching overhead of a multitasking operating system, and does not contribute to performing the actual task performed by the program or programs, such as multiplying a matrix, or processing a packet received from the network or rendering an image. contribute. Thus, while executing multiple threads in parallel can theoretically improve microprocessor performance, the extent of this performance improvement is limited by the overhead required to create new threads. In other words, the greater the overhead required to create a new thread, the greater the amount of useful work that must be performed by that new thread to offset the cost of creating the new thread. For threads with significant execution times, thread creation overhead may be largely irrelevant to performance. However, certain applications may benefit from relatively frequently created threads with relatively short execution times, in which case the thread creation overhead must be short enough to achieve reasonably high performance from multithreading. Therefore, there is a need for a multithreaded microprocessor that has a lightweight thread creation instruction in its instruction set.

Contents of the invention

The present invention provides a single instruction in a multithreaded microprocessor instruction set that, when executed, allocates a thread context for a new thread and schedules execution of the new thread. In one embodiment, the instructions occupy a single instruction issue slot in a microprocessor in a reduced instruction set computer (RISC) like manner. The instruction has very low overhead because it foregoes copying the entire parent thread context to the thread, which would take a considerable amount of time if copying the thread context sequentially, or would require A huge data path with multiple logic. Instead, the instruction includes a first operand which is an initial instruction fetch address to be stored into the program counter of the new thread context, and a second operand which is stored in In a register (such as a general-purpose register) in the register set of the new thread context. The second operand may be used by the new thread as a pointer to a data structure in memory containing data needed by the new thread, such as an initial general purpose register set value. The second operand causes the new thread to provide only the registers needed by the new thread by reading the registers from the data structure. This is advantageous because the inventors of the present invention noted that new threads typically only need to provide one to five registers. For example, many present-day microprocessors contain 32 general-purpose registers, and the microprocessor of the present invention avoids the useless effort of copying the entire parent thread's register set to the new thread's register set in the usual case.

In one embodiment, the instruction includes a third operand specifying which register in the new thread context is to receive the second operand. In one embodiment, the instructions can be executed by user-mode code, advantageously avoiding the need for the operating system to create new threads in general. Another benefit of having a single instruction that performs new thread context allocation and new thread scheduling is that valuable opcode space in the instruction set can be saved during implementations that require multiple instructions to create and schedule new threads. This instruction can perform two functions within a single instruction by raising an exception to the instruction if no free thread context is available for allocation when the instruction is executed.

In one aspect, the invention provides instructions for execution on a microprocessor configured to execute parallel program threads. The instruction includes an opcode for instructing the microprocessor to allocate resources for the new thread and to schedule execution of the new thread on the microprocessor. The resources include a program counter and a set of registers. The instruction also includes a first operand specifying an initial instruction fetch address to be stored in a program counter allocated for the new thread. The instruction also includes a second operand stored in a register in the set of registers allocated for the new thread.

In another aspect, the invention provides a multithreaded microprocessor. The microprocessor includes a plurality of thread contexts, each thread context configured to store a state of a thread and indicate whether the thread context is available for allocation. The microprocessor also includes a scheduler coupled to the plurality of thread contexts for assigning one of the plurality of thread contexts to a new thread in response to a single instruction in a currently executing thread, and Schedules execution of this new thread. If none of the plurality of thread contexts is available for allocation, the microprocessor issues an exception to the instruction.

In another aspect, the invention provides a multi-threaded microprocessor. The microprocessor includes a first program counter for storing fetch addresses of instructions in the first program thread. The microprocessor also includes a first set of registers including first and second registers specified by the instruction for storing first and second operands respectively, the first operand specifying Fetch address for the second program thread. The microprocessor also includes a second program counter coupled to the first set of registers for receiving a first operand from the first registers in response to the instruction. The microprocessor also includes a second set of registers coupled to the first set of registers including a third register for receiving a second operand from the second register in response to the instruction . The microprocessor also includes a scheduler coupled to the first and second register sets for causing the microprocessor to, in response to the instruction, read from the second program counter The stored second thread initially fetches an address fetch instruction and executes the fetched instruction.

In another aspect, the invention provides a method for creating a new thread of execution on a multithreaded processor. The method includes decoding a single instruction executing in a first program thread. The method also includes allocating a program counter and register set of the microprocessor to a second program thread in response to decoding the instruction. The method also includes storing a first operand of the instruction in a register of the set of registers in response to allocating the program counter and set of registers for the second program thread. The method also includes storing a second operand of the instruction in the program counter in response to allocating the program counter and register bank for the second program thread. The method also includes scheduling execution of a second program thread on the microprocessor after storing the first and second operands.

In another aspect, the invention provides a multithreaded processing system. The system includes a memory configured to store a fork instruction of a first thread and a data structure, the fork instruction specifying a memory address for storing the data structure and an initial instruction address of a second thread register. The data structure includes initial general purpose register values for the second thread. The system also includes a microprocessor coupled to the memory. The microprocessor allocates a free thread context for the second thread, stores the initial instruction address of the second thread in the program counter of the thread context, stores the data structure memory address in the register of the thread context, and responds Based on the fork instruction, the execution of the second thread is scheduled.

In another aspect, the invention provides a computer program product for use with a computer device. The computer program product includes a computer usable medium such that computer readable program code is embodied on the medium to cause a multi-threaded microprocessor. The computer readable program code includes first program code for providing a first program counter to store a fetch address of an instruction in a first program thread. The computer readable program code further includes second program code for providing a first set of registers comprising first and second registers specified by the instruction for storing first and second registers, respectively operands, the first operand specifying a fetch address for a second program thread. The computer readable program code further includes third program code for providing a second program counter coupled to the first register set for receiving a first register from the first register in response to the instruction. operand. The computer-readable program code also includes fourth program code for providing a second set of registers coupled to the first set of registers, including a third register, to read from the second set of registers in response to the instruction. A register receives a second operand. The computer readable program code also includes fifth program code for providing a scheduler coupled to the first and second register sets, responsive to the instructions, causing the microprocessor to The second program thread initially fetches an address stored in a program counter for execution and executes the fetched instruction.

In another aspect, the present invention provides a computer data signal embodied within a transmission medium, the computer data signal including computer readable program code to provide a multi-threaded microprocessor to execute a fork instruction. The program code includes first program code for providing an opcode to instruct the microprocessor to allocate resources for a new thread and to schedule execution of the new thread on the microprocessor, the resources including a program counter and register set. The program code also includes second program code for providing a first operand specifying an initial instruction fetch address to be stored into the program counter allocated for the new thread. The program code also includes third program code for providing a second operand for storage in a register of the set of registers allocated for the new thread.

Description of drawings

1 is a block diagram illustrating a computer system according to the present invention;

FIG. 2 is a block diagram illustrating a multithreaded microprocessor of the computer system in FIG. 1 according to the present invention;

Figure 3 is a block diagram illustrating a fork instruction executed by the microprocessor in Figure 2 according to the present invention;

FIG. 4 is a block diagram illustrating a per-thread control register and a TCStatus register in a graph according to the present invention;

FIG. 5 is a flowchart illustrating the operation of the microprocessor in FIG. 2 executing the fork instruction in FIG. 3 according to the present invention.

Detailed description of the invention

Referring now to FIG. 1, there is shown a block diagram of a computer system 100 in accordance with the present invention. The computer system 100 includes a multithreaded processor 102 coupled to a system interface controller 104 . The system interface controller 104 is coupled to a system memory 108 and a plurality of input/output (I/O) devices 106 . Each input/output (I/O) device 106 provides an interrupt request line 112 to the microprocessor 102 . Described computer system 100 can be but not limited to general programmable computer system, server computer, workstation computer, personal computer, notebook computer, personal digital assistant (PDA) or embedded system (Embedded system), and this embedded system Examples are, but are not limited to, network routers or switches, printers, mass storage controllers, cameras, scanners, automotive control systems, and more.

The system memory 108 includes memory, such as random access memory (RAM) or read-only memory, for storing program instructions executed on the microprocessor 102 and for storing data to be processed by the microprocessor in accordance with the program instructions Memory (ROM). The program instructions may comprise multiple program threads executing concurrently by the microprocessor 102 . A program thread or thread includes an executable sequence or stream of program instructions and an associated sequence of state changes within microprocessor 102 associated with the execution of the instructions. This sequence of instructions usually, but not necessarily, includes one or more program control instructions, such as branch instructions. Therefore, these instructions may or may not have contiguous memory addresses. A sequence of instructions comprising threads originates from a single program. In particular, microprocessor 102 is configured to execute a fork instruction for creating a new program thread, e.g., to allocate microprocessor resources required by microprocessor 102 to execute a thread, and to execute the fork instruction for the thread on microprocessor 102. Execution is scheduled as detailed below.

System interface controller 104 interacts with microprocessor 102 via a processor bus that couples microprocessor 102 to system interface controller 104 . In one embodiment, system interface controller 104 includes a memory controller for controlling system memory 108 . In one embodiment, system interface controller 104 includes a local bus interface controller to provide a bus, such as a PCI bus, to which input/output (I/O) devices 106 are connected.

Input output (I/O) devices 106 may include, but are not limited to, user input devices such as keyboards, mice, scanners, etc.; display devices such as monitors, printers, etc.; storage devices such as disk drives, tape drives , optical drive, etc.; system peripherals, such as direct memory access controller (DMAC), timers, timers, input/output ports, etc.; network devices, such as Ethernet, Fiber Channel, Infiniband or Media access controllers (MAC) for other high-speed network interfaces; data conversion equipment, such as analog/digital (A/D) converters, digital/analog (D/A) converters, etc. Input/output (I/O) devices 106 generate interrupt signals 112 to microprocessor 102 to request service. Advantageously, microprocessor 102 is capable of executing multiple program threads concurrently to handle events represented on interrupt request line 112 without the need to intersect with storing the current state of microprocessor 102, transferring control to an interrupt service routine, and Traditional overhead associated with restoring state after an interrupt service routine completes.

In one embodiment, computer system 100 includes a multiprocessing system including multiple multithreaded microprocessors 102 . In one embodiment, each microprocessor 102 provides two separate but not mutually exclusive multithreading capabilities. First, each microprocessor 102 contains a plurality of logical processing contexts, and for the operating system, each logical processing context appears as an independent processing element by sharing resources in the microprocessor 102, which is called virtual processing here. Element (VPE). To the operating system, the microprocessor 102 of N virtual processing elements (VPEs) behaves like an N-way symmetric multiprocessor (SMP), which allows existing symmetric multiprocessor (SMP)-capable An operating system that can manage multiple virtual processing elements (VPEs). Second, each virtual processing element (VPE) can contain multiple thread contexts to execute multiple threads simultaneously. Thus, the microprocessor 102 can also provide a multi-threaded programming model in which threads can be created or destroyed without operating system intervention in general, and can respond to external conditions such as I/O service event signals ), the system service thread can be scheduled with zero waiting time.

Referring now to FIG. 2, there is shown a block diagram of the multithreaded microprocessor 102 of the computer system 100 of FIG. 1 in accordance with the present invention. The microprocessor 102 is a pipelined microprocessor comprising a plurality of pipeline stages. The microprocessor 102 includes a plurality of thread contexts 228 to store state associated with a plurality of threads. Thread context 228 contains a set of registers of microprocessor 102 and/or bits in registers that describe the execution state of the thread. In one embodiment, thread context 228 includes a register bank 224 , such as a general purpose register (GPR) bank, a program counter (PC) 222 , and per-thread control registers 226 . The content of the per-thread control register 226 will be described in detail below. The embodiment in FIG. 2 shows four thread contexts 228 , each including a program counter 222 , register set 224 , and per-thread control registers 226 . In one embodiment, thread context 228 also includes a multiplication result register. In another embodiment, each of register banks 224 includes two read ports and one write port to support reading from each of the two registers and writing to one register in a single clock cycle . As described below, the FORK instruction 300 includes two source operands and one destination operand. Accordingly, microprocessor 102 may execute FORK instruction 300 within a single time period.

In contrast to thread context 228 , microprocessor 102 also maintains a processor context, which is a larger collection of microprocessor 102 state. In the FIG. 2 embodiment, the processor context is stored in per-processor control registers 218 . Each virtual processing element (VPE) contains its own set 218 of per-processor control registers. In one embodiment, one of the per-processor control registers 218 includes a status register that contains a field specifying the most recently dispatched thread exception raised by the exception signal 234 . Specifically, if a virtual processing element (VPE) issues the fork instruction 300 of the current thread, but currently there is no freely assignable thread context 228 to distribute to the new thread, then this exception field will indicate a thread overflow situation . In one embodiment, microprocessor 102 basically conforms to MIPS 32 or MIPS 64 instruction set architecture (ISA), and each processor control register 218 basically conforms to be used to store MIPS privileged resource architecture (PRA, Privileged Resource Architecture) simultaneously Registers of the processor context, such as the mechanisms necessary for the operating system to manage the resources of the microprocessor 102 (such as virtual memory, cache memory, exceptions, and user context, etc.).

Microprocessor 102 includes a scheduler 216 for scheduling the execution of various threads executed in parallel by the microprocessor. Scheduler 216 is coupled with per-thread control registers 226 and per-processor control registers 218 . In particular, the scheduler 216 is responsible for scheduling the fetching of instructions from the program counters 222 of the various threads and scheduling the issue of the fetched instructions to the execution units of the microprocessor 102, as described below. The scheduler 216 schedules the execution of the threads according to the scheduling policy of the microprocessor 102 . The scheduling policy may include but not limited to any one of the following scheduling policies. In one embodiment, the scheduler 216 uses a round-robin, or time-division multiplexing, or interleaved scheduling strategy, which can allocate a predetermined number of clock cycles or instruction issue slots to each A prepared thread. The round robin strategy is very effective for applications where fairness is required and certain threads (such as real-time application threads) require a minimum quality of service. In one embodiment, the scheduler 216 uses a blocking scheduling strategy. In this blocking scheduling strategy, the scheduler 216 continues to schedule the extraction and issuance of the currently running thread until an event that blocks the further execution of the thread occurs, such as Cache misses, branch mispredictions, data dependencies, or high latency instructions. In one embodiment, the microprocessor 102 includes a superscalar pipeline microprocessor, and the scheduler 216 schedules the issuance of multiple instructions per clock cycle, in particular, issues instructions from multiple threads per clock cycle, usually Called concurrent multithreading.

Microprocessor 102 includes instruction cache memory 202 for caching program instructions fetched from system memory 108 in FIG. 1 , such as fork instruction 300 in FIG. 3 . In one embodiment, the microprocessor 102 provides virtual storage capabilities, while the fetch unit 204 includes a translation lookaside buffer to cache page translations from physical to virtual storage. In one embodiment, each program or task executing on the microprocessor 102 is assigned a unique task ID, or address space ID (ASID), which can be used to perform memory accesses and, in particular, perform memory address translation, and Thread context 228 also includes an address space ID (ASID) for storing the thread. In one embodiment, when a parent thread executes the fork instruction 300 to create a new thread, the new thread inherits the ASID of the parent thread and its address space. In one embodiment, the various threads executing on the microprocessor 102 share the instruction cache memory 202 and the translation monitor register. In another embodiment, each thread contains its own transition monitor buffer.

The microprocessor 102 also includes a fetch unit 204 coupled to the instruction cache memory 202 to fetch program instructions such as the fork instruction 300 from the instruction cache memory 202 and the system memory 108 . Fetch unit 204 fetches the instruction at the instruction fetch address provided by multiplexer 244 . The multiplexer 244 receives a plurality of instruction fetch addresses from corresponding plurality of instruction counters 222 . Each instruction counter 222 stores the current instruction fetch address for a different thread. The embodiment shown in FIG. 2 shows four program counters 222 associated with four different threads. Instead, multiplexer 244 selects one of four program counters 222 based on a selection input provided by scheduler 216 . In one embodiment, fetch unit 204 is shared among threads executing on microprocessor 102 .

The microprocessor 102 also includes a decoding unit 206 coupled to the fetch unit 204 to decode the program instructions (such as the fork instruction 300 ) fetched by the fetch unit 204 . The decode unit 206 decodes the opcode, operands, and other fields of the instruction. In one embodiment, the decode unit 206 is shared among threads executing on the microprocessor 102 .

Microprocessor 102 also includes an execution unit 212 for executing instructions. Execution unit 212 may include, but is not limited to, one or more integer (integer) units for performing integer operations, Boolean operations, shift operations, rotation operations, etc.; floating point units for performing floating point operations; The /storage unit is used to perform memory access, especially to the data cache memory 242 coupled to the execution unit 212; and the branch resolution unit is used to analyze the result and target address of the branch instruction. In one embodiment, data cache memory 242 includes a translation watchdog buffer for caching physical to virtual memory page translations. In addition to operands received from data cache memory 242 , execution units 212 also receive operands from registers of register file 224 . In particular, execution unit 212 receives operands from register set 224 assigned to thread context 228 of the thread to which the instruction belongs. The multiplexer 248 selects operands from the appropriate register file 224 to provide to the execution unit 212 based on the thread context 228 of the instruction being executed by the execution unit 212 . In one embodiment, each execution unit 212 may execute instructions from multiple parallel threads concurrently.

One of execution units 212 is responsible for executing fork instruction 300 and asserts new_thread_request signal 232 , which is provided to scheduler 216 , in response to fork instruction 300 being issued. The new_thread_request signal 232 requests the scheduler 216 to allocate a new thread context 228 and schedule execution of the new thread associated with the thread context 228 . As described in more detail below, if a new thread context 228 is requested for allocation but no freely allocatable threads are available, the scheduler 216 asserts exception signal 234 to issue an exception to the fork instruction 300 . In one embodiment, the scheduler 216 keeps a count of the number of freely allocatable thread contexts 228 , and if the number is less than zero when the new_thread_request signal 232 is generated, the scheduler 216 issues an exception 234 to the fork instruction 300 . In another embodiment, when the new_thread_request signal 232 is generated, the scheduler 216 checks the status bit in the per-thread control register 226 to determine whether a freely assignable thread context 228 is available.

The microprocessor 102 also includes an instruction issuing unit 208, the instruction issuing unit 208 is coupled to the scheduler 216, and is coupled between the decoding unit 206 and the execution unit 212, so as to respond to the instructions of the scheduler 216 and decode The unit 206 decodes the instruction information and issues the instruction to the execution unit 212 . In particular, instruction issue unit 208 ensures that an instruction is not issued to execution unit 212 if the instruction has data dependencies on other instructions previously issued to execution unit 212 . In one embodiment, an instruction queue is imposed between the decode unit 206 and the instruction issue unit 208 to buffer instructions waiting to be issued to the execution unit 212, thereby reducing the possibility of "starvation" of the execution unit 212. In one embodiment, the instruction issue unit 208 is shared among threads executing on the microprocessor 102 .

Microprocessor 102 also includes a write-back unit 214 coupled to execution unit 212 to write results of completed instructions back to register file 224 . Demultiplexer 246 receives the instruction result from writeback unit 214 and stores the instruction result into the appropriate register bank 224 associated with the thread of the completed instruction.

Referring now to FIG. 3, there is shown a block diagram of a fork instruction 300 executed by the microprocessor 102 of FIG. 2 in accordance with the present invention. As shown in the figure, the representation of the FORK instruction 300 is fork rd, rs, rt, where rd, rs, rt are the three operands of the FORK instruction 300. FIG. 3 shows the various fields of the FORK instruction, bits 26 to 31 are the opcode field 302 and bits 0 to 5 are the function field 314 . In one embodiment, opcode field 302 indicates that the instruction is a SPECIAL type 3 instruction in the MIPS instruction set, and function field 314 indicates that the function is a FORK instruction. Therefore, the decode unit 206 in FIG. 2 checks the opcode field 302 and the function field 314 to determine whether the instruction is the FORK instruction 300 . Bits 6 through 10 are reserved as 0.

Bits 21 to 25, 16 to 20, and 11 to 15 are the rs field 304, the rt field 306, and the rd field 308, respectively, which are used to indicate the rs register 324 and the rt register in a group of registers in the register group 224 in FIG. 326 and rd register 328. In one embodiment, each of rs register 324, rt register 326, and rd register 328 is one of 32 general purpose registers in the MIPS ISA. The rs register 324 and the rt register 326 are each one of the registers in the register bank 224 assigned to the thread in which the FORK instruction 300 is contained, referred to as the parent thread, or a descendant thread, or the current thread. The rd register 328 is a register in register bank 224 assigned to the thread created by the FORK instruction 300, which is referred to as a new thread, or child thread.

As shown in Figure 3, the FORK instruction 300 instructs the microprocessor 102 to copy the value of the parent thread's rs register 324 into the new thread's program counter 222. The new thread program counter 222 will be used as the initial instruction fetch address for the new thread.

Additionally, the FORK instruction 300 instructs the microprocessor 102 to copy the value of the parent thread's rt register 326 into the new thread's rd register 328 . In a typical program operation, the program uses the value of the rd register 328 as the memory address of the new thread's data structure. This enables the FORK instruction 300 to forego copying the contents of the entire parent thread's register set 324 to the new thread's register set 324, thereby making the FORK instruction 300 more concise and efficient, and can be executed in a single clock cycle. Instead, the new thread includes instructions to provide only the registers needed by the new thread by reading register values from data structures that have a higher probability of being present in data cache memory 242 . This is because the inventors of the present invention determined that new threads typically only need to provide one to five registers, rather than the large number of registers typically found in many current microprocessors (like the 32 general-purpose registers in the MIPS instruction set). advantageous. To copy the entire register file 324 in a single clock cycle would require an impractically wide data path between the various thread contexts 228 in the microprocessor 102 while simultaneously copying the entire register file 324 sequentially (one per clock cycle). to two registers), takes more time and requires more complexity on the microprocessor 102. However, the FORK instruction 300 can advantageously be executed in a RISC fashion within a single clock cycle.

Advantageously, not only can an operating system executing on microprocessor 102 use FORK instruction 300 to allocate resources for and schedule execution of a new thread, but user-level threads can do the same. This fact is particularly advantageous for programs that create and terminate relatively short threads relatively frequently. For example, a program containing a large number of loops with short loop bodies and no data dependencies between iterations can benefit from the small thread creation overhead of the FORK instruction 300 . Suppose the code loops as follows:

for(i=0; i<N; i++){

  result[i] = FUNCTION(x[i], y[i]);

}

The less overhead of thread creation and destruction, the shorter the sequence of FUNCTION instructions can be and still be usefully parallelized across multiple threads. If the overhead associated with creating and destroying a new thread is on the order of 100 instructions, as is the case with traditional thread creation mechanisms, then FUNCTION must be multiple instructions long so that the loop can be parallelized across multiple Threads gain, if any, more benefit. However, the fact that the FORK instruction 300 overhead is so small (only one clock cycle in one embodiment) favorably suggests that even very small code intervals can benefit from parallelism with multiple threads.

Although Fig. 3 only shows that the value of the rt register 326 and the rs register 324 is copied from the parent thread context 228 to the new thread context 228, other states, or contents, may also be copied in response to the FORK instruction 300, as shown in the following figure 4 for a description.

Referring now to FIG. 4, there is shown a block diagram of one of the per-thread control register 226 and the TCStatus register 400 of FIG. 2 in accordance with the present invention. That is, each thread context 228 contains a TCStatus register 400 . The various fields in the TCStatus register 400 will be described in the table of FIG. 4; however, specific fields that are clearly related to the FORK instruction 300 will be described in more detail.

The TCStatus register 400 contains a TCU field 402 . In one embodiment, microprocessor 102 includes a single microprocessor core and one or more co-processors, in accordance with the MIPS instruction set or Privileged Resource Architecture (PRA). The TCU field 402 controls whether a thread can access or be restricted to a particular coprocessor. In the embodiment of FIG. 4, the TCU field 402 allows control of up to four co-processors. In one embodiment, the FORK instruction 300 instructs the microprocessor 102 to copy the value of the TCU field 402 in the parent thread to the TCU field 402 in the new thread created by the FORK instruction 300 .

The TCStatus register 400 also contains a DT bit 406 that indicates whether the thread context 228 is "dirty." DT bits 406 may be used by the operating system to ensure security between different programs. For example, use the FORK instruction 300 to dynamically allocate the thread context 228, and at the same time use the YIELD instruction of the microprocessor 102 to deallocate the thread context 228 in a different security domain, such as by multiple applications or by Both the operating system and the application, there is a risk of information leakage in the form of register values inherited by the application, which must be managed by a secure operating system. The DT bit 406 associated with the thread context 228 may be cleared by software while being set by the microprocessor 102 regardless of whether the thread context 228 has been modified. The operating system may initialize all thread contexts 228 to a known clean state and clear all DT bits 406 associated with the thread contexts 228 before scheduling tasks. When a task switch occurs, the thread context 228 whose DT bit 406 is set must be cleared to a clean state before other jobs are allowed to allocate and use them. If the secure operating system wishes to dynamically create threads and allocate privileged service threads, the relevant thread contexts 228 must be cleared before delivering them for potential use by applications. The reader is referred to the co-filed U.S. co-pending patent application entitled "Integrated mechanism for suspension and deallocation of computational threads of execution in a processor", docket number MIPS.0189-01US, mentioned at the beginning of this application , in this application, the YIELD instruction is described in detail.

The TCStatus register 400 also includes a DA status bit 412 that indicates whether the thread context 228 was dynamically allocated and scheduled by the FORK instruction 300 and dynamically released by the YIELD instruction. In one embodiment, a portion of the thread context 228 is dynamically allocated by the FORK instruction 300, while another portion of the thread context 228 is not dynamically allocated by the FORK instruction 300, but the thread context 228 is statically allocated to a program. in a permanent thread. For example, one or more thread contexts 228 may be statically allocated as part of the operating system rather than dynamically allocated by the FORK instruction 300 . In another example, in an embedded system, one or more thread contexts 228 may be statically allocated to a privileged service thread, which functions similarly to an interrupt source for servicing an interrupt source in a conventional processor. Interrupt Service Routine, which is well known as an essential part of the application program. For example, in a network router, one or more thread contexts 228 may be statically assigned to threads for processing events issued by a set of input/output ports, which may result in A single time period thread switching efficiently handles a large number of events, but for other microprocessors that have to incur the overhead associated with taking a large number of interrupt events, storing their associated state, and passing control to the interrupt service routine, The microprocessor 102 described herein has advantages.

In one embodiment, DA bit 412 may be used by an operating system to handle sharing of thread context 228 among applications. For example, the microprocessor 102 may issue a thread overflow exception 234 to the FORK instruction 300 when the FORK instruction 300 may attempt to allocate a thread context 228 when no free thread context 228 is available for allocation. In response, the operating system stores a copy of the current value and then clears the DA bit 412 of all thread contexts 228 . The next time the thread context is released by the application, a thread underflow exception 234 will be issued, in response, the operating system will restore the DA bit 412 stored in response to the thread underflow exception 234, and schedule the original thread overflow Replay of FORK instruction 300 of exception 234.

The TCStatus register 400 also includes an A bit 414 that indicates whether the thread associated with the thread context 228 is active. When the thread is in the active state, the scheduler 216 will schedule fetching instructions from its program counter 222 and issuing the instructions according to the scheduling policy of the scheduler 216 . When the FORK instruction 300 dynamically allocates the thread context 228, the scheduler 216 automatically sets the A bit 414, and when a YIELD instruction dynamically releases the thread context 228, the scheduler 216 automatically clears the A bit 414. In one embodiment, when the microprocessor 102 is reset, one of the thread contexts 228 is assigned as the reset thread context 228 to execute the initial thread of the microprocessor 102 . In response to a reset of the microprocessor 102, the A bit 414 of the reset thread context 228 is automatically set.

The TCStatus register 400 also includes a TKSU field 416 that indicates the privilege status or level of the thread context 228 . In one embodiment, this privilege can be at one of three levels: core, supervisor, or user. In one embodiment, the FORK instruction 300 instructs the microprocessor 102 to copy the value of the parent thread's TKSU field 416 into the TKSU field 416 of the new thread created by the FORK instruction 300 .

The TCStatus register 400 also includes a TASID field 422 that specifies the address space ID (ASID), or unique task ID, of the thread context 228 . In one embodiment, the FORK instruction 300 instructs the microprocessor 102 to copy the value of the parent thread's TASID field 422 into the TASID field 422 of the new thread created by the FORK instruction 300 so that the parent thread and the new thread share the same address space.

In one embodiment, the per-thread control register 226 also includes a register for storing a stop bit. By setting the stop bit, software can stop a thread, eg, put the thread context 228 in a stopped state.

Referring now to FIG. 5, there is shown a flow diagram of the execution of the FORK instruction 300 of FIG. 3 by the microprocessor 102 of FIG. 2 in accordance with the present invention. The process starts at block 502 .

In block 502, the extraction unit 204 uses the program counter 222 of the current thread to extract the FORK instruction 300, the decoding unit 206 decodes the FORK instruction 300, and the instruction issuing unit 208 issues the FORK instruction 300 to the execution unit in Fig. 2 212. The flow continues to block 504 .

At block 504 , the execution unit 212 indicates via the new_thread_request signal 232 that the FORK instruction 300 is requesting a new thread context 228 to be allocated and scheduled. The flow continues to block 506 .

At block 506, the scheduler 216 determines whether there are free thread contexts 228 available for allocation. In one embodiment, the scheduler 216 maintains a counter indicating the number of freely allocable thread contexts 228, which is incremented by one each time the YIELD instruction releases the thread context 228, and is incremented by one each time the FORK instruction Once a thread context 228 is allocated 300, the number is decremented by one, and the scheduler 216 determines whether there is a freely assignable thread context 228 by determining whether the value of this counter is greater than zero. In another embodiment, scheduler 216 checks status bits in per-thread control registers 226, such as DA bit 412 and A bit 414 in TCStatus register 400 of FIG. The thread context is allocated 228 . When the thread context 228 is not activated or stopped and is not a statically allocated thread context 228 , then the thread context 228 is a freely allocatable thread context 228 . If the thread context 228 is available for free allocation, the flow continues to block 508 ; otherwise, the flow continues to block 522 .

At block 508 , the scheduler 216 in response to the FORK instruction 300 will allocate a freely assignable thread context 228 for the new thread. The flow continues to block 512 .

In block 512, the value of the rs register 324 of the parent thread context 228 is copied in the program counter 222 of the new thread context 228, and the value of the rt register 326 of the parent thread context 228 will also be copied to the rd register 328 of the new thread context 228 3, and other contexts associated with the FORK instruction 300, as described in FIG. 4, are also copied from the parent thread context 228 to the new thread context 228. The flow continues to block 514 .

At block 514, the scheduler 216 schedules the new thread context 228 for execution. That is, the scheduler 216 adds the thread context 228 to the list of currently ready-to-execute thread contexts 228, so that the fetch unit 204 starts fetching and issuing instructions from the program counter 222 of the thread context 228 according to the restriction of the scheduling policy. The flow continues to block 516 .

At block 516 , the fetch unit 204 begins fetching instructions in the program counter 222 of the new thread context 228 . The flow continues to block 518 .

At block 518, the instructions of the new thread provide the register set 224 to the registers of the new thread context 228 as needed. As previously stated, program instructions for a new thread will typically provide register bank 224 from a data structure in memory specified by the rd register 328 value. The process ends at block 518 .

At block 522, the scheduler 216 issues a thread overflow exception 234 to the FORK instruction 300 to indicate that no free thread context 228 was available for allocation while the FORK instruction 300 was executing. The flow continues to block 524 .

At block 524, the exception handler in the operating system creates a condition under which the allocated thread context 228 is freed for the FORK instruction 300, as previously described for the DA bit 412 in FIG. The flow continues to block 526 .

At block 526, the operating system reissues the FORK instruction 300 that caused the exception 234 in block 522, which can now execute successfully because the freely allocatable thread context 228 is available, as previously done for the DA bit 412 in FIG. describe. The process ends at block 526 .

While the invention and its objects, features, and advantages have been described in detail, the invention encompasses other embodiments. For example, although an embodiment has been described in which the new thread context 228 is allocated on the same VPE as the parent thread context, in another embodiment, if the parent VPE detects that there is no freely assignable thread context on the VPE, then The VPE will attempt a remote FORK command 300 on another VPE. In particular, the VPE determines whether another VPE has a freely assignable thread context and whether it has the same address space as the parent thread context, and if so, sends a FORK instruction message packet to other VPEs so that other VPEs can allocate And schedule this free thread context. Additionally, the FORK instruction described here is not limited to use on a microprocessor that can execute multiple threads concurrently to address specific potential events, but can also be used on a Execute on a multi-threaded microprocessor. Furthermore, the FORK instruction described herein can also be implemented in scalar or superscalar microprocessors. Additionally, the FORK instruction described here can also be implemented in microprocessors with different scheduling policies. In addition, although the embodiment of the FORK instruction in which the rt register value is copied into a register of a new thread context has been described, other embodiments are also contemplated in which the rt register value may be provided to the new thread context in other ways , such as through memory. Finally, while an embodiment has been described where the operand of the FORK instruction is stored in a general purpose register, in other embodiments the operand may be stored by other means, such as via memory or via a non-general purpose register. For example, while an embodiment has been described in which the microprocessor is a register-based microprocessor, other embodiments are contemplated in which the microprocessor may be a stack-based microprocessor, such as a processing The processor is configured to efficiently execute Java Virtual Machine program code. In this embodiment, the operand of the FORK instruction is specified on the operand stack in memory, rather than in a register. For example, each thread context may include a stack pointer register, and the field of the FORK instruction may indicate the offset of the operand of the FORK instruction in stack memory relative to the stack pointer register, rather than specifying an offset in the microprocessor's register space. register.

Instead of implementing the invention in hardware, the invention can also be embodied in software (eg, computer readable code, program code, instructions and/or data) embodied in a computer-usable (eg, readable) medium. Such software enables the function, fabrication, modeling, simulation, description and/or testing of the devices and methods described herein. For example, this can be achieved through the use of general purpose programming languages (such as C, C++, JAVA, etc.), GDSII databases, hardware description languages (HDL) including Vorilog HDL, VHDL, etc., or other available programs, databases, and/or circuits (also That is, the schematic diagram) capture tool to achieve. Such software can be placed on any computer usable (eg, readable) medium, which can include semiconductor memory, magnetic disk, optical disk (such as CD-ROM, DVD-ROM, etc.), etc., and can be included as a computer data signal in a computer usable In a (readable) transmission medium such as a carrier wave or any other medium including digital, optical, or analog-based media. Likewise, software may be transmitted over communication networks including the Internet and intranets. It should be understood that the present invention may be embodied in software, and may be translated into hardware as part of an integrated circuit product, such as in HDL, as part of a semiconductor intellectual property core (such as a microprocessor core), or as System-level design, such as a system-on-chip or SOC. Likewise, the present invention can also be realized by a combination of software and hardware.

Finally, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the invention. Rather, the scope of the invention should be defined by the appended claims.

Claims (34)

1, a kind of multithreaded microprocessor comprises:

A plurality of thread context, whether each thread context is configured to store the state of thread, and indicate described thread context to can be used for distributing; And

Scheduler, it is coupled to described a plurality of thread context, is used for the single instruction in response to the thread of current execution, a thread context in described a plurality of thread context is distributed to new thread, and dispatch the execution of described new thread;

Wherein, if described a plurality of thread context all is not useable for distributing, then described microprocessor can send one and give described single instruction unusually;

Wherein, described single instruction comprises: operational code, first operand and second operand.

2, microprocessor as claimed in claim 1, wherein, each thread context in described a plurality of thread context comprises programmable counter.

3, microprocessor as claimed in claim 2, wherein, described single instruction indicate described microprocessor with the first operand of described instruction store into distribute to described new thread described a plurality of thread context in the described programmable counter of a thread context in.

4, microprocessor as claimed in claim 3, wherein, described single instruction indicate described microprocessor with the second operand of described instruction store into can memory location by described new thread visit in.

5, microprocessor as claimed in claim 4, wherein, in described a plurality of thread context each comprises a plurality of general-purpose registers, and wherein said single instruction indicates described microprocessor described second operand to be stored in the register in described a plurality of general-purpose registers of a described thread context of described a plurality of thread context of distributing to described new thread.

6, microprocessor as claimed in claim 5, wherein, a register in described a plurality of general-purpose registers is specified by the 3-operand of described instruction.

7, microprocessor as claimed in claim 4, wherein, each thread context in described a plurality of thread context comprises the SP that is used to specify stacked memory, and wherein said single instruction indicates described microprocessor that described second operand is stored in the position in the described stacked memory.

8, microprocessor as claimed in claim 7, wherein, the described position in the described stacked memory is specified by the 3-operand of described instruction.

9, microprocessor as claimed in claim 1, wherein, described microprocessor allows described instruction to distribute a thread context in described a plurality of thread context for described new thread, even and the thread of described current execution also dispatch the execution of described new thread when on the user privilege level, carrying out.

10, microprocessor as claimed in claim 1, wherein, time slot is sent in the single instruction that described instruction takies in the described microprocessor.

11, microprocessor as claimed in claim 1, wherein, each in the described registers group comprises two read ports and one and writes inbound port.

12, microprocessor as claimed in claim 1, wherein, maximum two source-register operands and a destination register operand are specified in described fork instruction.

13, a kind of multithreaded microprocessor comprises:

First programmable counter is used for the extraction address of instruction is stored in first program threads; Described instruction comprises operational code, first operand and second operand;

First registers group comprises first and second registers by described instruction appointment, and to store first and second operands respectively, described first operand is specified the extraction address of second program threads;

Second programmable counter, itself and described first registers group couple, and are used in response to described instruction, receive described first operand from described first registers group;

Second registers group, itself and described first registers group couple, and comprise the 3rd register, are used in response to described instruction, receive described second operand from described second registers group; And

Scheduler, itself and described first and second registers group couple, and are used in response to described instruction, make described microprocessor from the extraction address extraction instruction of described second program threads stored described second programmable counter and carry out the instruction of described extraction.

14, microprocessor as claimed in claim 13 also comprises:

Unusual indicator, itself and described scheduler couple, and are used in response to described instruction, if described second programmable counter and registers group should not be used to receive described first and second operands, then make described microprocessor send a unusual extremely described instruction.

15, microprocessor as claimed in claim 13 also comprises:

Unusual indicator, itself and described scheduler couple, and are used in response to described instruction, if described second programmable counter and registers group have been that another thread is used, then make described microprocessor send a unusual extremely described instruction.

16, microprocessor as claimed in claim 13, wherein, described the 3rd register is specified by described instruction.

17, microprocessor as claimed in claim 13, wherein, described first and second registers group comprise general purpose register set, wherein in response to described instruction, described second general purpose register set is only from the described second operand of the described first general-purpose register group of received.

18, a kind of method that is used for creating the new thread that can carry out at multithreaded microprocessor, this method comprises:

The single instruction that decoding is carried out in first program threads; Wherein said single instruction comprises operational code, first operand and second operand;

In response to described decoding, be programmable counter and the registers group that second program threads distributes described microprocessor;

In response to described distribution, the first operand of described instruction is stored in the register in the described registers group;

In response to described distribution, the second operand of described instruction is stored in the described programmable counter; And

After described first and second operands of storage, dispatch the execution of described second program threads on described microprocessor.

19, method as claimed in claim 18 also comprises:

In response to described decoding, determine whether programmable counter and registers group can be used for distributing.

20, method as claimed in claim 19 also comprises:

If do not have programmable counter and registers group to can be used for the branch timing, then send a unusual extremely described instruction.

21, method as claimed in claim 18, wherein, described distribution, described first and second operands of described storage and described scheduling are all finished in the cycle at the single clock of described microprocessor.

22, a kind of method that is used to create the new thread that can on multithreaded microprocessor, carry out, this method comprises:

The single instruction that decoding is carried out in first program threads; Wherein said single instruction comprises operational code, first operand and second operand;

In response to described decoding, be the second program threads allocator counter;

Determine whether described distribution is successful;

If described being allocated successfully, then the operand with described instruction stores in the described programmable counter, and dispatches the execution of second program threads on described microprocessor;

If described distribution is unsuccessful, then send a unusual extremely described instruction.

23, method as claimed in claim 22 also comprises:

If described being allocated successfully, then the second operand with described instruction offers described second thread.

24, method as claimed in claim 23 also comprises:

In response to described decoding, for described second program threads distributes a registers group;

It is wherein said in described second thread provides the described second operand of described instruction to comprise described second operand stored into register in the described registers group of distributing into described second program threads.

25, method as claimed in claim 23 also comprises:

In response to described decoding, for described second program threads distributes a stack pointer, this stack pointer is specified and the relevant stacked memory of described second thread;

Wherein saidly provide the second operand of described instruction to comprise to described second thread described second operand is stored in the described stacked memory.

26, a kind of multithreaded processing system comprises:

Storer, be configured to store the fork instruction and data structure of first thread, described fork instruction comprises operational code, first operand and second operand, be used to specify a register and store the storage address of described data structure and the initial order address of second thread, described data structure comprises the initial generic register value of described second thread; And

Microprocessor, itself and described storer couple, being configured to (1) is described second thread distribution one thread context freely, (2) the described second thread initial order address is stored in the programmable counter of described thread context, (3) storage address with described data structure is stored in the register of described thread context, and (4) instruct the execution of dispatching described second thread in response to described fork.

27, disposal system as claimed in claim 26, wherein, the number of the described initial register value of described second thread in the described data structure is less than the number of the general register values of described thread context.

28, disposal system as claimed in claim 26, wherein, the described thread context that is assigned to described second thread and described first thread thread context different.

29, disposal system as claimed in claim 28, wherein, described storer further is configured to store the programmed instruction of described second thread, with the general-purpose register of described initial register value from described memory copy to described thread context with described data structure, in response to described fork instruction, make described microprocessor abandon the whole thread context of described first thread is copied in the described thread context of described second thread thus.

30, disposal system as claimed in claim 26, wherein, described microprocessor further is configured to, thread context can be assigned to described second thread if do not have freely, then sends a unusual extremely described fork instruction.

31, a kind of method of on multithreaded microprocessor, carrying out the Fork instruction, this Fork instruction comprises operational code, first operand and second operand, this method comprises:

Operational code is provided, and so that to indicate described microprocessor be the new thread Resources allocation and dispatch the execution of this new thread in described microprocessor, described resource comprises programmable counter and registers group;

First operand is provided, extracts the address to specify the initial order that will be stored in the described programmable counter that distributes into described new thread; And

Provide second operand, to be stored in the register in the described registers group of distributing for described new thread.

32, method as claimed in claim 31 also comprises:

3-operand is provided, will be stored in which register in the described registers group to specify described second operand.

33, method as claimed in claim 31 also comprises:

The relevant status register of described registers group that provides and distribute for described new thread, wherein said status register comprises an indicator, does for oneself after the described new thread distribution with indication, whether described registers group is written into.

34, method as claimed in claim 31 also comprises:

Unusual indicator is provided, if not freely programmable counter and registers group can be assigned to described new thread, then send one and give described fork instruction unusually.

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