CN100489605C - Identification chip of display panel and manufacturing method thereof - Google Patents

Abstract

An identification chip of a display panel is provided, which uses a plurality of independent metal blocks divided on a substrate as an identification part and a plurality of test parts, and each test part is connected with a test wire, a protective layer is covered on the metal blocks and the intervals between the metal blocks are filled up, a plurality of through holes are formed in the protective layer to correspondingly expose the surface of the test part, transparent electrodes (ITO) are formed on the protective layer and corresponding to the test parts, and the through holes are filled up by the transparent electrodes. The invention not only gives consideration to the recognition function and the test function, but also can effectively improve the space utilization rate.

Description

Identification chip of display panel and manufacturing method thereof

technical field

The invention relates to an identification chip and a manufacturing method thereof, in particular to a display panel identification chip with testing function and a manufacturing method thereof.

Background technique

Due to the advantages of light and thin appearance, low voltage and low power consumption, no radiation, high brightness, and high contrast ratio, the consumer market of Liquid Crystal Display (LCD) is growing rapidly, and the demand is also increasing. For small and medium-sized liquid crystal display panels, such as mobile phone screens or personal digital assistant (Personal Digital Assistant, PDA) display screens, the layout space of electronic circuit components inside is not wide, so some components such as test pads (Cell Test Pad) There may not be room for it. If certain products must be placed with an identification chip (Chip ID, which contains the chip serial number) due to the requirements of the production line, it will definitely affect the space of the test pad.

Please refer to FIG. 1 , which shows a schematic diagram of a conventional display panel. The display panel 1 has a display area 10 and a non-display area 12 . The non-display area 12 can place some electronic circuit components, such as identification chips or test pads. The placed areas are, for example, the first setting area 14 in the lower left corner and the second setting area 16 in the upper right corner. FIG. 2A is an enlarged schematic view of the first setting area in FIG. 1 . FIG. 2B is an enlarged schematic view of the second setting area in FIG. 1 . The identification chip can be placed in the first setting area 14 or the second setting area 16 .

Generally speaking, the first setting area 14 is used to place the common electrode voltage test pad (V _COM TestPad), the red data test pad (Data Red Test Pad), the green data test pad (Data Green TestPad) and the blue data test pad. Pad (Data Blue Test Pad), to test the source signal (Source Signal) of panel 1, if the identification chip is also placed in the first setting area 14, as shown in position 141, and the common electrode voltage test pad is placed in position 143, then The remaining space (the range framed by the dotted line in the figure) is not enough to place R, G, B and other test pads.

The second setting area 16 is used to place a common electrode voltage test pad (Vcom Test Pad), an even scan line test pad (Scan Even test Pad) and an odd scan line test pad (Scan OddTest Pad) to test the panel 1 scan signal (Scan Signal). If the identification chip is placed on the second setting area 16, as shown in position 161, then the remaining space (the area framed by the dotted line in the figure) is not enough to place these test pads, for example, if the common electrode voltage test pad is placed on The position 163 will conflict with the identification chip 161 .

Contents of the invention

In view of this, the object of the present invention is to provide a display panel identification chip with testing function and a manufacturing method thereof, by integrating the test pad and the identification chip to achieve the best utilization of space.

According to the purpose of the present invention, a kind of manufacturing method of the identification chip with testing function is proposed, wherein the identification chip is arranged on a panel, and the manufacturing method at least includes the following steps:

forming a substrate on the panel;

Forming an identification part and a plurality of test parts on the substrate, and there is a space between the identification part and the test parts, and each test part is connected with a test line;

Covering a protective layer on the identification part and the test parts, and filling the gap;

Forming a plurality of through holes (Through Holes) in the protective layer to expose the surface of the test portion correspondingly; and

A plurality of transparent electrodes (ITO) are formed above the protective layer corresponding to the testing portions, wherein the transparent electrodes fill the through holes.

According to the purpose of the present invention, propose a kind of identification chip (Chip ID) with testing function, be arranged on a board. The identification chip includes: an identification section with a two-dimensional barcode (2D Code); There is an interval between them.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments are exemplified below and described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 shows a schematic diagram of a conventional display panel;

FIG. 2A is an enlarged schematic view of the first setting area in FIG. 1;

FIG. 2B is an enlarged schematic diagram of the second setting area in FIG. 1;

3A to 8B illustrate a method for manufacturing an identification chip with a test function according to a preferred embodiment of the present invention, wherein FIGS. 3A, 4A, 6, 7A, and 8A are side views; FIG. 3B is a top view of FIG. 3A; 4B is a top view of FIG. 4A; FIG. 7B is a top view of FIG. 7A; FIG. 8B is a top view of FIG. 8A;

FIG. 9 shows a schematic diagram of a display panel according to a preferred embodiment of the present invention;

FIG. 10A is an enlarged schematic view of the first setting area in FIG. 9;

FIG. 10B is an enlarged schematic view of the second setting area in FIG. 9 .

Detailed ways

The invention integrates a plurality of test pads and identification chips, and manufactures identification chips with testing functions through a special manufacturing method, thereby achieving the purpose of saving space. The manufacturing method and finished product of the identification chip of the present invention will be described below with preferred embodiments.

Please refer to FIGS. 3A-8B , which illustrate a method of manufacturing an identification chip with testing function according to a preferred embodiment of the present invention. 3A, 4A, 6, 7A, 8A are side views. Fig. 3B is a top view of Fig. 3A. FIG. 4B is a top view of FIG. 4A. Fig. 7B is a top view of Fig. 7A. Fig. 8B is a top view of Fig. 8A.

First, a substrate 31 is provided, and a metal layer 33 is formed on the substrate 31 , as shown in FIGS. 3A and 3B . Next, the metal layer 33 is etched to form a plurality of independent metal blocks as an identification part and a plurality of testing parts. In this embodiment, it is taken as an example to form five independent metal blocks, and these metal blocks include a first test portion 41, a second test portion 42, a third test portion 43, a fourth test portion 44 and an identification unit 45 . And there is a distance d1 between the first test part 41 and the second test part 42, a distance d2 between the second test part 42 and the identification part 45, and a distance d3 between the identification part 45 and the third test part 43 , There is a distance d4 between the third test portion 43 and the fourth test portion 44, as shown in FIGS. 4A and 4B. Wherein, the interval between two pairs may be d1≠d2≠d3≠d4, or d1=d2=d3=d4, which is not particularly limited. In a practical example, when the size of the substrate 31 is 2000 μm×10000 μm, the interval d1=d2=d3=d4=30 μm can effectively isolate each metal block.

The first testing part 41, the second testing part 42, the third testing part 43 and the fourth testing part 44 are respectively connected with a first testing line 51, a second testing line 52, a third testing line 53 and a first testing line. Four test lines 54, as shown in FIG. 5 . The first testing part 41, the second testing part 42, the third testing part 43 and the fourth testing part 44 pass through the first testing line 51, the second testing line 52, the third testing line 53 and the fourth testing line 54 respectively to Provides functionality for testing signals.

Next, a passivation layer (Passivation Layer) 60 is formed above the first test portion 41, the second test portion 42, the third test portion 43, the fourth test portion 44 and the identification portion 45, and the passivation layer 60 is also filled with metal blocks The gap between them is shown in Figure 6.

Then, form a plurality of through holes (Through Holes) in the protective layer 60, for example, the through holes 61 can expose the surface of the first testing portion 41 correspondingly, and the through holes 62 can correspondingly expose the surface of the second testing portion 42, The through hole 63 can correspondingly expose the surface of the third testing part 43 , and the through hole 64 can correspondingly expose the surface of the fourth testing part 44 , as shown in FIGS. 7A and 7B .

Next, above the protective layer 60 corresponding to the first test portion 41, the second test portion 42, the third test portion 43 and the fourth test portion 44, a first transparent electrode (ITO) 81 and a second transparent electrode are formed. 82 , a third transparent electrode 83 and a fourth transparent electrode 84 . And the first transparent electrode 81 fills the through hole 61, the second transparent electrode 82 fills the through hole 62, the third transparent electrode 83 fills the through hole 63, and the fourth transparent electrode 84 fills the through hole 64, as shown in Figures 8A and 8B shown.

8A and 8B are respectively a test diagram and a top view of an identification chip manufactured according to a preferred embodiment of the present invention. Comprise on the substrate 31 of identification chip: have the identification part 45 of two-dimensional bar code (2D Code) and a plurality of testing parts, as first testing part 41, second testing part 42, the 3rd testing part 43 and the 4th testing part 44 , and each test part is connected to a test line respectively, and is separated from each other by an interval to electrically isolate them. There is a protective layer above the identification part and a plurality of test parts, and there are a plurality of through holes (Through Hole) 61, 62, 63, 64 on it, corresponding to the first test part 41, the second test part 42, the third test part respectively. The testing part 43 and the fourth testing part 44 . There are multiple electrodes on the protective layer, such as a first transparent electrode 81 , a second transparent electrode 82 , a third transparent electrode 83 and a fourth transparent electrode 84 , and fill the through holes 61 , 62 , 63 and 64 respectively.

As shown in FIG. 8B , the identification chip with testing function can be applied on the display panel after being manufactured. Please refer to FIG. 9 , which is a schematic diagram of a display panel according to a preferred embodiment of the present invention. The display panel 9 has a display area 90 and a non-display area 92 . The identification chip with testing function can be placed in the first setting area 94 in the lower left corner and the second setting area 96 in the upper right corner. FIG. 10A is an enlarged schematic view of the first setting area in FIG. 9 . FIG. 10B is an enlarged schematic view of the second setting area in FIG. 9 .

If the identification chip is determined to be placed in the first setting area 94, then the identification chip according to the above process has a first testing part 101, a second testing part 102, a third testing part 103, a fourth testing part 104 and an identification part 105. , as shown in Figure 10A. Wherein, by connecting test lines (as shown in Figure 5), the first test section 101, the second test section 102, the third test section 103, and the fourth test section 104 can respectively have a common electrode voltage test pad (V _COM Test Pad), a red data test pad (Data RedTest Pad), a green data test pad (Data Green Test Pad) and a blue data test pad (DataBlue Test Pad), to respectively test the source of the common electrode voltage of panel 9 Signal (SourceSignal), source signal for red data, source signal for green data, and source signal for blue data. As for the identification part 105, there is a two-dimensional barcode (2D Code), indicating the code of the panel 9, for machine interpretation.

If the identification chip is determined to be placed in the second setting area 96, then the first test portion 111, the second test portion 112, and the third test portion 113 on the identification chip according to the above-mentioned process can have a common electrode voltage test pad (V _COM Test Pad), an even scan line test pad (Scan Even test Pad) and an odd scan line test pad (Scan Odd Test Pad), and pass through the test line to respectively test the scanning signal of the common electrode voltage of the panel 9, A scan signal of an even scan line and a scan signal of an odd scan line. As for the identification part 115, there is a two-dimensional barcode (2D Code), indicating the code of the panel 9, for machine interpretation.

Of course, as far as the identification chip arranged in the second setting area 96 is concerned, since only three test pads are needed, the substrate 31 can be divided into four independent metal blocks when etching the metal layer during the process to serve as three test pads. A testing section and a recognition section. Therefore, the number of independent metal blocks on the substrate is not limited, but depends on actual application conditions.

The application of the identification chip of the present invention not only takes into account the functions of the test pad and the serial number of the identification chip, but also effectively integrates the space occupied by the test pad and the identification chip, so that the applied panel can achieve the best space utilization rate.

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (14)

1. A manufacturing method of an identification chip, wherein the identification chip is arranged on a display panel, the manufacturing method at least comprises the following steps: forming a substrate on the display panel; forming a metal layer on the substrate; Etching the metal layer to form a plurality of independent metal blocks, respectively defining the metal blocks as an identification part and a plurality of test parts, and there is a space between the identification part and the test parts, and each test part is connected a test line; Covering a protective layer on the identification part and the testing parts, and filling up the gap; forming a plurality of through holes in the protection layer to expose the surfaces of the testing parts correspondingly; and A plurality of transparent electrodes are formed above the protection layer corresponding to the test portions, wherein the transparent electrodes fill the through holes. 2. A method for manufacturing an identification chip, wherein the identification chip is arranged on a display panel, the manufacturing method at least comprising the following steps: providing a substrate, and forming a metal layer on the substrate; Etching the metal layer to form a plurality of individual metal blocks comprising at least: An identification part with a two-dimensional barcode; a first test part, connected to a first test line; a second test part connected to a second test line; and a third test part, connected to a third test line, wherein the first test part, the second test part and the third test part pass through the first test line, the second test line and the third test line respectively Test line to provide the function of test signal; forming a protective layer to cover the metal blocks; forming a plurality of through holes in the protective layer, and correspondingly exposing the surfaces of the first testing part, the second testing part and the third testing part; and forming a first transparent electrode, a second transparent electrode and a third transparent electrode above the protection layer, and the first transparent electrode corresponds to the first test portion, and the second transparent electrode corresponds to the second test portion And the third transparent electrode corresponds to the third testing portion, wherein the first transparent electrode, the second transparent electrode and the third transparent electrode fill the through holes. 3. The manufacturing method as claimed in claim 2, wherein the metal blocks further comprise a fourth testing part. 4. An identification chip for a display panel, the identification chip comprising: An identification part with a two-dimensional barcode; a plurality of test parts, each test part is connected with a test line; There is an interval between the identification part and the test parts, Wherein the steps of forming the identification part and the test parts are: forming a metal layer on the substrate; The metal layer is etched to form a plurality of independent metal blocks, and the metal blocks are respectively defined as the identification part and the test parts. 5. The identification chip as claimed in claim 4, wherein the test sections include: a first test section, a second test section and a third test section, the first test section is used to test a scanning signal of a common electrode voltage , the second testing part is used for testing the scanning signal of an even scanning line, and the third testing part is used for testing the scanning signal of an odd scanning line. 6. The identification chip as claimed in claim 4, wherein the testing parts include: a first testing part, a second testing part, a third testing part and a fourth testing part. 7. The identification chip as claimed in claim 6, wherein the first test section is used to test a source signal of a common electrode voltage, the second test section is used to test a source signal of red data, and the third test section The part is used to test a source signal of green data, and the fourth test part is used to test a source signal of blue data. 8. The identification chip as claimed in claim 4, wherein the distance between the identification part and the testing parts is about 30 μm. 9. An identification chip arranged on a display panel, the identification chip comprising: a substrate; A plurality of individual metal blocks formed on the substrate, including: a first metal block connected to a first test line; a second metal block connected to a second test line; and a third metal block connected to a third test line; A fourth metal block having a two-dimensional barcode; a protective layer formed on the metal blocks, with a plurality of through holes corresponding to the first metal block, the second metal block and the third metal block; A plurality of electrodes are formed on the protective layer, the electrodes include: a first transparent electrode located above the protection layer and corresponding to the first metal block; a second transparent electrode located above the protective layer corresponding to the second metal block; and A third transparent electrode located above the protective layer corresponds to the third metal block, and the first transparent electrode, the second transparent electrode and the third transparent electrode fill the through holes. 10. The identification chip as claimed in claim 9, wherein the first metal block is used as a common electrode voltage test pad, the second metal block is used as an even scan line test pad, and the third metal block is used as an odd scan line test pad. 11. The identification chip as claimed in claim 10, wherein the common electrode voltage test pad, the even scan line test pad and the odd scan line test pad are scan signals for testing the display panel. 12. The identification chip according to claim 9, further comprising a fifth metal block connected to a fourth test line. 13. The identification chip as claimed in claim 12, wherein the first metal block is used as a common electrode voltage test pad, the second metal block is used as a red data test pad, and the third metal block is used as a green data test pad, And the fourth metal block is used as a blue data test pad. 14. The chip serial number board as claimed in claim 13, wherein the common electrode voltage test pad, the red data test pad, the green data test pad and the blue data test pad are used to test the source signal of the display panel .

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