CN100489540C - Component interface plate used for test of semiconductor integrated circuit - Google Patents

Abstract

The invention discloses a device interface board used in semiconductor integrated circuit testing, wherein, the left side and the right side of a 24-pin dual inline type socket are respectively provided with a jumper structure; therefore, flexible adjustment of the GND terminal and the VDD terminal of a dual inline type semiconductor integrated circuit device with different pin numbers can be realized; moreover, a single universal device interface board can complete the testing function of device with a plurality of pins. The invention not only meets the testing requirements of semiconductor integrated circuit device with different pins, but also reduces testing cost.

Description

Device interface board for semiconductor integrated circuit testing

technical field

The invention relates to a device interface board for semiconductor integrated circuit testing.

Background technique

A semiconductor integrated circuit using a dual in-line package (DIP), which has 14 pins, 16 pins, 20 pins, 24 pins, etc., usually uses different sockets for integrated circuits with different pin numbers. , making different device interface boards (Device Interface Board DIB). If the number of integrated circuits to be tested is small, it is uneconomical to make a device interface board for each pin type of integrated circuit, so it is necessary to consider designing a device interface board that can be used universally.

Contents of the invention

The technical problem to be solved by the present invention is to provide a device interface board for semiconductor integrated circuit testing, which can adapt to the testing requirements of semiconductor integrated circuits with different pins and reduce the cost of testing.

In order to solve the above-mentioned technical problems, the device interface board used for semiconductor integrated circuit testing of the present invention includes a dual-in-line socket with 24 pins, and a jumper structure is respectively arranged on the left and right sides of the socket, and each The jumper structure has 12 rows of jumpers, and each row of jumpers has three jumper pins in the left, middle and right; the jumper structure on the left side, the jumper pins in the middle of each row correspond to the corresponding pins of the socket Connection, the jumper pin on the left is connected to the GND end of the test bench, the jumper pin on the right is connected to the digital channel of the test bench; the jumper structure on the right, the jumper pin in the middle of each row is connected to the socket The corresponding pins are connected, the jumper pin on the right is connected to the VDD terminal of the test bench, and the jumper pin on the left is connected to the digital channel of the test bench.

In the present invention, a jumper structure is arranged on the device interface board, and proper jumper is performed on the tested devices with different pins, so as to correctly connect its power supply (VDD) and ground (GND) terminals.

The test and development cost of the integrated circuit can be reduced by adopting the invention. For example, in general, for four types of devices with 14 pins, 16 pins, 20 pins, and 24 pins (see Figure 1), at least 4 kinds of DIBs are required (see Figure 2). After adopting the invention, only one DIB is needed to meet the test requirements of various products.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment, the present invention is described in further detail:

Fig. 1 is a device schematic diagram of existing four kinds of dual in-line package pins;

FIG. 2 is a schematic diagram of four existing device interface boards for different pins;

Fig. 3 is a schematic diagram of the device interface board of the present invention.

Detailed ways

As shown in FIG. 3 , the device interface board for testing semiconductor integrated circuits of the present invention includes a dual-in-line socket with 24 pins, and a jumper structure is arranged on the left and right sides of the socket.

Each jumper structure has 12 rows of jumper wires, and each row of jumper wires has three jumper lead pins of left, middle and right.

The 12-row jumpers in the jumper structure on the left are numbered from top to bottom in the order of 1 to 12, and the 12-row jumpers in the right jumper structure are numbered in the order of 24 to 13 from top to bottom.

The jumper structure on the left, the jumper pins in the middle of each row are connected to the corresponding pins of the socket, the left jumper pins are connected to the GND end of the test bench, and the right jumper pins are connected to the test bench The jumper structure on the right, the jumper pins in the middle of each row are connected to the corresponding pins of the socket, the jumper pins on the right are connected to the VDD end of the test bench, the jumper pins on the left The pins are connected to the digital channels of the test bench.

When it is necessary to test the 54LS00 device with 14 pins, connect the pins of the left middle jumper at the 7th row of the left jumper structure number together, and connect the right jumper with the right jumper structure number of the 24th row Together, the corresponding pins are connected to the test system GND and VDD. When it is necessary to test the 54LS163 device with 16 pins, connect the pins of the left middle jumper at the 8th row of the left jumper structure number, and connect the right jumper with the right jumper structure number of the 24th row Together, the corresponding pins are connected to the test system GND and VDD. In the same way, if it is a DUT with VDD and GND terminals in the middle, it can also be flexibly solved without a special design of a DIB board. The invention is aimed at integrated circuits in the form of DIP packages, and is especially suitable for testing requirements with many varieties and few quantities.

Claims (1)

1, a kind of component interface plate that is used for the test of semiconductor integrated circuit of dual-in-line package, it is characterized in that: comprise a twin string line-inset socket with 24 pins, at this socket one jumper wire construction is set each side, each jumper wire construction, have 12 row wire jumpers, each row wire jumper has three wire jumpers in left, center, right and draws pin; The jumper wire construction in left side, the wire jumper of each interline draws the pin pin corresponding with described socket and is connected, and the wire jumper on the left side draws pin and is connected with the GND end of test board, and the wire jumper on the right draws pin and links to each other with the digital channel of test board; The jumper wire construction on right side, the wire jumper of each interline draw the pin pin corresponding with described socket and are connected, and the wire jumper on the right draws pin and is connected with the vdd terminal of test board, and the wire jumper on the left side draws pin and links to each other with the digital channel of test board.

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