CN100485890C - Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay - Google Patents
Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay Download PDFInfo
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- CN100485890C CN100485890C CNB2005100992084A CN200510099208A CN100485890C CN 100485890 C CN100485890 C CN 100485890C CN B2005100992084 A CNB2005100992084 A CN B2005100992084A CN 200510099208 A CN200510099208 A CN 200510099208A CN 100485890 C CN100485890 C CN 100485890C
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- 239000013078 crystal Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000005611 electricity Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 238000005224 laser annealing Methods 0.000 claims abstract description 13
- 238000001451 molecular beam epitaxy Methods 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 21
- 239000011521 glass Substances 0.000 claims description 5
- 238000003877 atomic layer epitaxy Methods 0.000 claims description 3
- 238000004943 liquid phase epitaxy Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 2
- 125000006850 spacer group Chemical group 0.000 claims 2
- 230000004927 fusion Effects 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract description 18
- 239000004973 liquid crystal related substance Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 20
- 239000010703 silicon Substances 0.000 description 20
- 239000012528 membrane Substances 0.000 description 17
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本发明提供一种薄膜电晶体的制造方法。首先，形成一缓冲层于基板上，并形成一第一单晶层于缓冲层上。其后，形成一非晶层于第一单晶层上，以一激光退火方法，将非晶层转换成一结晶层。该结晶层为一复晶层或第二单晶层；接着，形成一闸极介电层于复晶层上。后续，形成一闸电极于闸极介电层上。本发明的薄膜电晶体适用于液晶显示器。可提升薄膜电晶体元件的电子移动率，并且可以缩短传统使用分子束磊晶沉积单晶硅的时间。
The invention provides a method for manufacturing a thin film transistor. Firstly, a buffer layer is formed on the substrate, and a first single crystal layer is formed on the buffer layer. Thereafter, an amorphous layer is formed on the first single crystal layer, and the amorphous layer is converted into a crystal layer by a laser annealing method. The crystal layer is a compound crystal layer or a second single crystal layer; then, a gate dielectric layer is formed on the compound crystal layer. Subsequently, a gate electrode is formed on the gate dielectric layer. The thin film transistor of the present invention is suitable for liquid crystal displays. It can improve the electron mobility of thin film transistor components, and can shorten the time of traditionally using molecular beam epitaxy to deposit single crystal silicon.
Description
[technical field]
The invention relates to a kind of manufacture method of membrane transistor, the manufacture method of the particularly relevant membrane transistor that is applicable to LCD and amorphous layer is converted to the method for polycrystalline layer or single crystalline layer.
[background technology]
Present membrane transistor LCD (thin film transistor-liquid crystaldisplay, TFT-LCD) technology is divided into two kinds, and one is traditional amorphous silicon membrane electric crystal, and another is the compound crystal silicon membrane transistor.Since the electronics translational speed of compound crystal silicon membrane transistor be 10 times to 100 times of the amorphous silicon membrane electric crystal between.Therefore, the TFT-LCD industry has taken up to study and develop, with the drive circuit as picture element (pixel) switch element and LCD periphery of compound crystal silicon membrane transistor.
Low temperature compound crystal silicon (lowtemperature polysilicon, LTPS) processing procedure are adopted in the making of above-mentioned compound crystal silicon membrane transistor usually.So-called LTPS processing procedure is to utilize quasi-molecule laser annealing to handle that (excimer laser annealing ELA) makes original amorphous silicon membrane be transformed into the compound crystal silicon structure.
Yet, by traditional quasi-molecule laser annealing technology with amorphous silicon crystallization and the output energy process window that forms compound crystal silicon is very narrow again.Existing excimer laser energy time stability is not good, though equipment can be suppressed at the energy change of (peak to peak) between spike and spike below 15% at present, if yet when irradiation energy change occurs, can cause substrate locality energy height difference.This energy changing can cause compound crystal silicon thin film crystallization particle diameter, and great changes will take place, and the membrane transistor characteristic is produced harmful effect.
[summary of the invention]
Therefore, according to above-mentioned problem, a purpose of the present invention can increase excimer laser energy process window for a kind of manufacture method of membrane transistor is provided, and can be by directly increasing the restriction that the excimer laser energy range overcomes board.
Another object of the present invention converts amorphous layer the method for polycrystalline layer or single crystalline layer to for providing a kind of, and it can obtain uniform compound crystal silicon or monocrystalline silicon thin film.
The invention provides a kind of manufacture method of membrane transistor.At first, form a resilient coating on substrate, and form one first single crystalline layer on resilient coating., form an amorphous layer in first single crystalline layer on,, convert amorphous layer to a crystallizing layer with a laser anneal method thereafter.This crystallizing layer is a polycrystalline layer or second single crystalline layer; Then, form a brake-pole dielectric layer on polycrystalline layer.Follow-up, form a gate electrode on brake-pole dielectric layer.
The present invention also provides a kind of and converts amorphous layer the method for polycrystalline layer or single crystalline layer to, it is characterized in that: comprise the steps:
One substrate is provided; Form a resilient coating on this substrate; Form one first single crystalline layer on this resilient coating; Form an amorphous layer on this single crystalline layer; And, convert this amorphous layer to a crystallizing layer with a laser anneal method, wherein this crystallizing layer is to be one second single crystalline layer or a polycrystalline layer.
[description of drawings]
1A figure～the 1H figure illustrates one embodiment of the invention to make membrane transistor TFT flow chart.
[embodiment]
Below will describe in detail as reference of the present invention, and example is accompanied by graphic explanation with embodiment.In graphic or description, similar or identical part is to use identical figure number.In graphic, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.The part of element will illustrate with description in graphic.Apprehensiblely be that the element that does not illustrate or describe can have the various forms of haveing the knack of known to this skill people.In addition, when narration one deck is when being positioned at a substrate or another layer and going up, this layer can be located immediately on substrate or another layer, or intermediary layer can also be arranged therebetween.
Figure 1A～Fig. 1 H illustrates one embodiment of the invention to make membrane transistor TFT flow chart.Please refer to Figure 1A, a substrate 100 at first is provided.This substrate 100 can be a glass substrate, is preferably a glass with lower alkali content substrate or an alkali-free glass substrate.Deposit a resilient coating 102 in substrate 100 on thereafter.Resilient coating 102 can be the dielectric layer formed of silica, silicon nitride or silicon oxynitride for example.Next, form single crystalline layer 104 on resilient coating 102, shown in Figure 1B.Single crystalline layer 104 can be a monocrystalline silicon, and its formation method can be molecular beam epitaxy (Molecular beamepitaxy), atomic layer brilliant (Atomic layer epitaxy) of heap of stone, gas phase brilliant (Vapor phase epitaxy) of heap of stone or liquid built crystalline substance modes such as (Liquid phase epitaxy) form.The preferably, single crystalline layer 104 is to be the monocrystalline silicon thin film of a thickness between 20 dusts～200 dusts.
Next, please refer to Fig. 1 C, form an amorphous layer 106 on single crystalline layer 104.Amorphous layer 106 can be an amorphous silicon.The preferably, amorphous layer 106 is to be an amorphous silicon, and its thickness is the design alternative of considering for according to product demand or processing procedure.The deposition process of amorphous layer 106 can strengthen chemical vapour deposition technique PECVD, atomic layer deposition method APCVD or similar technology for Low Pressure Chemical Vapor Deposition LPCVD, aumospheric pressure cvd method APCVD, electricity slurry.In preferable enforcement example, amorphous layer 106 is can adopt the lower electricity slurry of process temperatures to strengthen chemical vapour deposition technique (PECVD) to form.
, please refer to Fig. 1 D, amorphous layer 106 is annealed, and make amorphous layer 106 be converted to the crystallizing layer 106 of polycrystalline layer or single crystalline layer for example " with laser beam annealing 108 (for example quasi-molecule laser annealing, ELA, Excimer laser anneal) thereafter.
Tradition quasi-molecule laser annealing technology is with amorphous silicon crystallization and the output energy process window that forms compound crystal silicon is that very narrow reason is in the recrystallized amorphous silicon process again, the amorphous silicon that needs one deck not have to melt is used as crystal seed (seed), and known techniques can't effectively provide this crystal seed that does not melt, and the crystal grain that causes amorphous silicon to form compound crystal silicon diminishes.The reason that the crystal grain that causes amorphous silicon to form compound crystal silicon diminishes has two: (1) if laser energy is crossed when hanging down, the amorphous silicon that can melt fully concentrates on the top layer, and bottom then presents the semi-molten state.Silicon wafer particle diameter during therefore with low-yield crystallization is less and also have portion of amorphous silicon and be entrained in wherein.(2),,, cause homogeneous nucleation from all directions, and the compound crystal silicon crystal grain of crystallization is less owing to there is not the guiding of silicon seed because amorphous silicon presents the state of fusing fully if when laser energy is too high.Because these two reasons make the energy process window of traditional quasi-molecule laser annealing very little.
In one example of the present invention, before deposition of amorphous silicon 106, deposition one deck monocrystalline silicon thin film 104 is as crystal seed earlier.Because the height that the fusing point of monocrystalline silicon (1686 ℃) is more next than amorphous silicon fusing point (1273 ℃), so the present invention can improve excimer laser output energy at least about 15%.According to (energy (E)=specific heat (S) * quality (M) * temperature difference (Δ T)), generally speaking laser radiation generation instantaneous temperature is about 1400 ℃, when increasing energy 15%, the moment high temperature that produces is about 1600 ℃, therefore when arriving monocrystalline silicon thin film 104 via thermal diffusion, temperature is less than 1600 ℃, do not allow monocrystalline silicon 104 fusings and can not make, and makes amorphous silicon 106 recrystallize into crystallizing layer 106 into for example polycrystalline layer or single crystalline layer by monocrystalline silicon 104 crystal seeds ".So just can overcome the output energy unsteadiness influence that crystallization is again caused to amorphous silicon of quasi-molecule laser annealing ELA board.
Next, please refer to Fig. 1 E,, form brake-pole dielectric layer 110 and gate electrode layer 112 in regular turn in crystallizing layer 106 with general little shadow and engraving method " on.Brake-pole dielectric layer 110 can be formed by for example silica, silicon nitride or silicon oxynitride.Gate electrode layer 112 can be a single metal layer, a bimetal structure or polymetal crust.Above-mentioned structure can be selected from following group: W, WN
x, Ti, TiW
x, TiN
x, Ta, TaN
x, Mo, Al, Cu and similar material.The deposition process of any kenel (including but not limited to chemical vapour deposition technique CVD, physical vaporous deposition PVD, evaporation, plating, sputter, reaction sputter (reactive co-sputtering) or above-mentioned combination altogether) can be in order to form this metal level.
After forming gate structure, lightly mixed drain area (LDD), dielectric gap wall and source/drain regions can known techniques form.For instance, shown in the 1F～1H figure, at first, please refer to Fig. 1 F, carry out a light dope ion disposing process with variety classes impurity, implant impurity is in crystallizing layer 106 " in, to form light doping section (light doped region, LDD) 114.The border of light doping section 114 is the sidewalls that approximately are registered to gate structure.The energy of light dope ion disposing process is reducible between 1～100Kev, and its doping is approximately between 1 * 10
13～1 * 10
15Ions/cm
2Afterwards, deposit and dry ecthing procedure, form clearance wall 116 with sidewall along gate structure.Clearance wall 116 can be formed by following material: the alternating layer of silicon nitride layer, silicon oxide layer, silicon oxynitride layer, silicon nitride layer and silicon oxide layer or above-mentioned combination.Afterwards, carries out a heavy doping ion cloth and plant, and gate clearance wall 116 is to be made for cover curtain, plant multiple impurity to crystallizing layer 106 with cloth " in, source/drain regions 118 formed.The border of source/drain regions 118 is the exterior side wall that approximately are registered to the gate clearance wall respectively.Heavy doping ion cloth is planted the energy of processing procedure approximately between 1～100Kev, and doping is approximately between 5 * 10
13～1 * 10
16Ions/cm
2
Therefore, according to the foregoing description, the present invention has following advantage at least:
(1) mode forms in compound crystal silicon or the monocrystalline silicon process thus, and it is about more than 15% to increase excimer laser energy process window significantly.
(2) according to the method for the embodiment of the invention, can be by bottom monocrystalline silicon as crystal seed, via the quasi-molecule laser annealing technology amorphous silicon is recrystallized into again and be monocrystalline silicon or compound crystal silicon, so electronics mobility (Electron mobility) can increase significantly, and can solve the low temperature compound crystal silicon because panel size increased back (〉 at 15 o'clock), the shortcoming that the electronics mobility can't satisfy.In addition, according to the method for the embodiment of the invention, it can promote outside the electronics mobility of membrane transistor element, and can shorten the time that tradition is used molecular beam epitaxy deposition monocrystalline silicon.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and a little change and the retouching done all should belong to protection scope of the present invention.
[symbol description]
100～substrate; 102～cushion;
104～single crystalline layer; 106～amorphous layer;
106 "～crystallizing layer; The annealing of 108～laser beam;
110～brake-pole dielectric layer; 112～gate electrode layer;
114～light doping section; 116～clearance wall;
118～source/drain regions.
Claims (15)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100992084A CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100992084A CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
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| Publication Number | Publication Date |
|---|---|
| CN1929101A CN1929101A (en) | 2007-03-14 |
| CN100485890C true CN100485890C (en) | 2009-05-06 |
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| CNB2005100992084A Expired - Fee Related CN100485890C (en) | 2005-09-09 | 2005-09-09 | Method for manufacturing thin film electricity crystal and method for changing non-crystal inlay to multi-crystal inlay or single-crystal inlay |
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| CN103715269B (en) * | 2013-12-31 | 2015-06-03 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN109801973B (en) | 2018-09-25 | 2021-01-26 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
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