CN100477136C - Circuit board and packaging structure thereof - Google Patents
Circuit board and packaging structure thereof Download PDFInfo
- Publication number
- CN100477136C CN100477136C CNB2006100012150A CN200610001215A CN100477136C CN 100477136 C CN100477136 C CN 100477136C CN B2006100012150 A CNB2006100012150 A CN B2006100012150A CN 200610001215 A CN200610001215 A CN 200610001215A CN 100477136 C CN100477136 C CN 100477136C
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- circuit board
- layer
- cutting path
- semiconductor package
- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A circuit board and its structure, the circuit board includes: a body; and a solder mask layer covering the surface of the body, wherein the solder mask layer forms a groove corresponding to the cutting path to expose the body; the semiconductor packaging structure comprises: the circuit board is provided with a body and a welding-resisting layer covering the surface of the body, a cutting path is arranged on the circuit board, a plurality of circuit board units arranged in an array mode are defined, wherein a groove is formed on the welding-resisting layer corresponding to the cutting path, and the body is exposed; a semiconductor chip, which is connected and electrically connected to each circuit board unit; and a packaging colloid formed on the circuit board for coating the semiconductor chip; the circuit board and the packaging structure thereof can avoid the problems of welding-resisting layer melting, irregular cutting edge, cutting debris residue and pollution of subsequent cutting procedures during laser cutting.
Description
Technical field
The invention relates to a kind of circuit board and assembling structure thereof, particularly about a kind of circuit board and encapsulating structure thereof for Chip Packaging.
Background technology
Undersized integrated circuit encapsulation unit generally in batch mode is built in single the matrix form substrate; This matrix form substrate is pre-defined to go out a plurality of packaging areas, wherein encapsulation unit of each packaging area construction.After finishing the packing colloid operation, then carry out a segmentation procedure (singulation process), with segmentation of structures one-tenth other encapsulation unit of the encapsulation unit of construction in the matrix form substrate.The encapsulation unit of Zhi Zaoing for example comprises thin spherical grid array (Thin ﹠amp by this way; Fine Ball Grid Array, TFBGA) encapsulation unit, quadrangular plan pin-free (Quad Flat Non-leaded, QFN) encapsulation unit or the like.Relevant this utilizes into the technology such as the United States Patent (USP) the 5th, 776,798 and the 6th, 281 of a plurality of semiconductor packages of batch mode construction unit, No. 047 case.
See also Figure 1A and 1B, in the TFBGA packaging process, adopt a matrix base plate module sheet 10 as substrate; These substrate module sheet 10 pre-defined a plurality of base board units 100, TFBGA encapsulation unit of wherein corresponding each base board unit construction, finish on each base board unit put crystalline substance, routing and encapsulation mold pressing after, can cut single job between corresponding each base board unit, form a plurality of TFBGA encapsulation units.
Moreover, flourish along with mobile phone of new generation and various portable product, grow up fast in mini memory card market, for example SD (Secure Digital), MMC (Multi Media Card) card etc., this storage card is a kind of flash memory circuit module of high power capacity, this circuit module can be connected to an electronic information platform, for example personal computer, personal digital assistant device, digital camera, multimedia browser, store the multi-medium data of various digital forms, for example digital photo data, video data or voice data.
See also Fig. 2 A and 2B, the TaiWan, China patent announcement is a kind of manufacture method of storage card No. 570294, it is the array base palte module sheet 20 that has a plurality of base board units 200, corresponding respectively this base board unit 200 carries out connecing of chip 21 and passive device 23 and puts and electrically connect, on this full wafer substrate module sheet, form a packing colloid (not marking) again, then utilize diamond wheel (Grinding wheel cutter) to cut along this base board unit 200 respectively, by becoming batch mode to produce a plurality of rectangular packaging parts 2, again this packaging part 2 is embedded in the shell body 26.Adopt the littler base board unit of length and width size, make in batch, reduce production costs of array way.
For cooperating the development of various light, thin, short, little electronic installation, the design of storage card also so need miniaturization more has from MMC to develop RSMMC and MMC-μ on the market; And the development and application that develops mini SD and μ-SD etc. by SD, therefore, be accompanied by the variation of process variations and product, the demand pattern of storage card package part no longer is confined to above-mentioned traditional upright rectangle that is made of monotonous straight lines, be transformed into and had irregular shape, yet, diamond wheel cutting mode in the above-mentioned operation, only can form the straight cuts path, the real demand that has been unable to cope with erose cassette packaging part.Moreover, need in the above-mentioned prior art after chip is finished encapsulation, extra again capping one shell body, like this, causing this housing need additionally be provided and this shell body is sticked to the cost and the process that cause on the packaging part increases, and is not inconsistent economic benefit.
Therefore, U.S. Pat 2004/0259291 proposes the another kind of operation technology using shell body and can handle irregular storage card package part of not needing, it mainly is to have on the substrate module sheet of a plurality of base board units corresponding each base board unit one to put crystalline substance and routing operation, on this substrate module sheet, carry out the packing colloid operation more comprehensively, then the storage card package part outward appearance of utilizing water cutter or laser mode correspondence to form is again cut, and forms a plurality of erose storage card package parts that have.
In above-mentioned operation, no matter in corresponding this TFBGA of cutting or the cassette packaging part operation, refuse layer owing to wherein be coated with one by what macromolecular material was made in order to the substrate surface of carries chips, when therefore utilizing the laser edge respectively to cut between this base board unit, the normal layer of refusing is met heat generation melting phenomenon because of the influence of Stimulated Light thermal effect, produces irregularly shaped and causes cut surface out-of-flatness problem, cause chip (Chipping) to remain in substrate surface, the subsequent handling pollution problem takes place.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of circuit board and assembling structure thereof, refuses layer melting problem when avoiding laser cutting.
A further object of the present invention is to provide a kind of circuit board and assembling structure thereof, avoids the cut edge that irregular problem takes place.
Another object of the present invention is to provide a kind of circuit board and assembling structure thereof, avoid cutting the chip residue problem.
An also purpose of the present invention is to provide a kind of circuit board and assembling structure thereof, avoids cutting the subsequent handling pollution problem.
For reaching above-mentioned and other purpose, the invention provides a kind of circuit board and assembling structure thereof, wherein the cutting path that is provided with of this circuit board defines a plurality of circuit board units that array way is arranged that are, and this circuit board comprises: a body; And the layer of refusing that covers this body surface, wherein this is refused layer and forms groove corresponding to this cutting path, exposes outside this body.
Wherein the body of this circuit board comprises at least one insulating barrier and the patterned line layer of at least one storehouse on this insulating barrier; This groove width is greater than the cutting width of cutting path in addition.
Cut single job corresponding to the circuit board that above-mentioned array way is arranged, when forming the circuit board unit of single type formula, this circuit board unit comprises that a body and covers the layer of refusing of this body surface, this refuses the planar dimension of layer planar dimension less than this circuit board unit body, exposes outside the marginal portion of this circuit board unit body.
In addition, by the foregoing circuit plate structure, the present invention also discloses a kind of semiconductor package structure, this assembling structure along get final product after this cutting path cuts a plurality of construction units, wherein, this construction unit comprises: circuit board unit, this circuit board unit have the layer of refusing that a body and covers this body surface, this refuses the planar dimension of layer planar dimension less than this circuit board unit body, exposes outside the marginal portion of this circuit board unit body; Connect the semiconductor chip of putting and be electrically connected to this circuit board unit; And be formed on the circuit board unit in order to coat the packing colloid of this semiconductor chip.
In semiconductor package structure of the present invention, cut on the semiconductor package structure edge that corresponding above-mentioned array way is arranged the respectively cutting path between this circuit board unit, form the semiconductor structure structure of single type attitude, it comprises: circuit board unit, this circuit board unit surface coverage is refused layer, this refuses the planar dimension of layer planar dimension greater than the circuit board unit body, exposes outside the marginal portion of this circuit board unit body; Connect the semiconductor chip of putting and be electrically connected to this circuit board unit; And be formed on the circuit board unit in order to coat the packing colloid of this semiconductor chip.
Therefore, circuit board that the present invention discloses and assembling structure thereof mainly are on the circuit board that array way is arranged, make cover this circuit board surface refuse form groove on the cutting path between corresponding each circuit board unit of layer, expose outside the body part of this circuit board, like this when cutting tools such as using laser cuts, can effectively avoid taking place refusing on the circuit board layer because of the influence of Stimulated Light thermal effect, cause and refuse layer on the cutting path and meet hot melting, produce irregularly shaped and cause cut surface out-of-flatness problem, cause chip to remain in substrate surface, cause problems such as subsequent handling pollution.
Description of drawings
Figure 1A and 1B are the schematic diagrames of existing thin spherical grid array (TFBGA) packaging part;
Fig. 2 A and 2B are the storage card operation schematic diagrames that the TaiWan, China patent announcement discloses for No. 570294;
Fig. 3 A is the schematic bottom view of circuit board embodiment 1 of the present invention;
Fig. 3 B is the generalized section of circuit board embodiment 1 of the present invention;
Fig. 4 A and 4B are circuit board that Fig. 3 A and 3B are arrayed forms circuit board unit after cutting section and schematic bottom view;
Fig. 5 is the generalized section of semiconductor package structure of the present invention;
Fig. 6 is the structure dress schematic diagram that the semiconductor package structure of corresponding diagram 5 cuts along the cutting path around each circuit board unit;
Fig. 7 is the generalized section of circuit board embodiment 2 of the present invention; And
Fig. 8 is the schematic bottom view of circuit board embodiment 3 of the present invention.
Embodiment
Fig. 3 A and 3B are bottom surface and the generalized sections of circuit board embodiment 1 of the present invention.
As shown in the figure, this circuit board 30 adopts array way to arrange, it has a plurality of circuit board units 300, what this circuit board 30 comprised a body 301 and covered these body 301 surfaces refuses layer 302, wherein, corresponding to respectively being provided with cutting path S around this circuit board unit 300, this refuses 302 pairs of layers should expose outside this circuit board body 301 by cutting path S formation groove 302a.
This circuit board 30 has a plurality of circuit board units 300, each circuit board unit can be for follow-up electric connection and the encapsulation mold pressing procedure of putting between crystalline substance, chip and circuit board unit, can cut single job by corresponding 300 of each circuit board units afterwards, form a plurality of encapsulation units.This circuit board 30 can for example be the base plate for packaging that is applied in spherical grid array type (BGA) semiconductor package part in addition, the base plate for packaging of using at thin spherical grid array (TFBGA) packaging part especially, but non-as limit.
The body 301 of this circuit board comprises at least one insulating barrier 301a and the patterned line layer 301b of at least one storehouse on this insulating barrier 301a.Wherein this insulating barrier 301a for example is Bismaleimide Triazine (BT.Bismaleimide triazine) or blending epoxy and glass fibre (FR4) etc., and this patterned line layer 301b is a metal copper layer.
This layer 302 of refusing that covers body 301 covers this patterned line layer 301b, avoids being subjected to outside contamination and destruction.This refuses layer 302 is for example to be the macromolecular material of green lacquer, and this refuse layer 302 form openings expose outside in this circuit board pattern line layer as and the electric connection pad 3010b that is electrically conducted of the external world, for example weldering refers to (Finger), solder ball pad etc.
Simultaneously, corresponding to being provided with a cutting path S around each circuit board unit 300, this refuses 302 pairs of layers should form groove 302a by cutting path S, exposes outside the insulating barrier 301a part in this circuit board body 301 on this circuit board 30.This groove 302a mainly is formed on this circuit board 30 for follow-up carrying out and puts plate side (board side) with external device (ED) (as printed circuit board (PCB)) electrically connects in the present embodiment, for follow-up this circuit board put brilliant side (chip side) put crystalline substance and the encapsulation after, can cut at the groove 302a that puts the plate side along this circuit board.Wherein this groove 302a width is greater than the cutting width of cutting path S.
So, follow-up when carrying out cutting action, can make cutting tool, when especially the laser cutting instrument is along each circuit board unit 300 of this cutting path S cutting and separating, directly cut to circuit board body 301, avoid it to touch and refuse layer 302, can avoid causing the layer 302 of refusing of product edge melting to take place because of meeting heat with laser contact, produce irregularly shaped and cause cut surface out-of-flatness problem, avoid chip to remain in substrate surface and cause problems such as subsequent handling pollution.
Fig. 4 A and Fig. 4 B are the above-mentioned circuit board 30 that is arrayed forms a plurality of circuit board units 300 behind cutting operation section and schematic bottom view, what this circuit board unit 300 comprised that a body 301 and covers these body 301 surfaces refuses layer 302, this refuses the planar dimension of layer 302 planar dimensions greater than circuit board unit body 301, exposes outside the marginal portion of this circuit board unit body 301.
See also Fig. 5, it is the semiconductor package structure generalized section that the circuit board shown in application drawing 3A and the 3B carries out the Chip Packaging operation, as shown in the figure, this semiconductor package structure comprises circuit board 30, this circuit board 30 adopts array way to arrange, it has a plurality of circuit board units 300, these circuit board 30 surface coverage one are refused layer 302, corresponding to respectively being provided with cutting path S around this circuit board unit 300, this refuses 302 pairs of layers should expose outside this circuit board body 301 by cutting path S formation groove 302a; Semiconductor chip 31 connects and puts and be electrically connected to respectively this circuit board unit 300; And packing colloid 35, be formed on the circuit board 30 in order to coat this semiconductor chip 31.
This semiconductor chip 31 can utilize gold thread 34 to be electrically connected to and expose outside the electric connection pad 3010b (referring to as weldering) that this refuses layer 302 on this circuit board unit 300, makes packing colloid 35 envelope this semiconductor chip 31 simultaneously and gold thread 34 avoids being subjected to outside contamination, destruction.This semiconductor chip 31 is electrically connected to this circuit board unit 300 except utilizing the routing mode in addition, also can utilize to cover crystal type and be electrically connected to circuit board unit 300, non-ly exceeds with this diagram.
Other sees also Fig. 6, it is the array assembling structure of corresponding diagram 5, the structure dress schematic diagram that cutting path S around each circuit board unit 300 cuts, or put the structure dress schematic diagram of crystalline substance, packaging operation for the circuit board unit 300 of corresponding diagram 4A, as shown in the figure, this assembling structure comprises a circuit board unit 300, these circuit board unit 300 surface coverage are refused layer 302, this refuses the planar dimension of layer 302 planar dimensions greater than circuit board unit body 301, exposes outside the marginal portion of this circuit board unit body 301; Connect the semiconductor chip 31 of putting and be electrically connected to this circuit board unit 300; And be formed on the packing colloid 35 in order to coat this semiconductor chip 31 on the circuit board unit 300.
Fig. 7 is the generalized section of circuit board embodiment 2 of the present invention.
The circuit board of the embodiment of the invention 2 and the foregoing description 1 are roughly the same, main difference is that this refuses on the upper and lower surface (put brilliant side and put the plate side) of layer 302 corresponding to circuit board body 301, all form groove 302a at cutting path S place, expose outside this circuit board body 301 parts, when so respectively the cutting path S of 300 of this circuit board units cuts on follow-up edge, in the time of more can avoiding utilizing laser cutting, touch and refuse layer 302 melting of being heated and produce irregular surface and fines problem.
Embodiment 3
Fig. 8 is the floor map of circuit board embodiment 3 of the present invention.
The circuit board of the embodiment of the invention 3 and the foregoing description 1,2 are roughly the same, and main difference is that this circuit board can be applicable to the cassette encapsulating structure.
As shown in the figure, this circuit board 40 comprises a plurality of circuit board units 400, corresponding to being provided with cutting path S (shown in dotted line) around this circuit board unit 400, make and be formed on refusing 402 pairs of layers and should forming groove 402a in cutting path S place of these circuit board 40 surfaces, expose outside the circuit board body part, wherein along respectively can forming irregular cutting path S around this circuit board unit 400, can the satisfy the demands semiconductor package part (for example cassette packaging part) of shape outward appearance of this irregular cutting path S.For follow-up finish put crystalline substance and packaging operation after, can directly cut this circuit board body along this cutting path S for the cutting tool of laser for example, avoid touching refuse layer 402 parts cause refuse the layer melting, chip produces and problem such as operation pollution.
Therefore on the circuit board that the main corresponding array way of circuit board of the present invention and assembling structure thereof is arranged, make cover this circuit board surface refuse form groove on the cutting path between corresponding each circuit board unit of layer, expose outside this circuit board body part, so when cutting tools such as using laser cuts, can effectively avoid taking place refusing on the circuit board layer because of the influence of Stimulated Light thermal effect, cause and refuse layer on the cutting path and meet hot melting, produce irregularly shaped and cause cut surface out-of-flatness problem, cause chip to remain in substrate surface, cause problems such as subsequent handling pollution.
In addition, circuit board of the present invention is except can be applicable to base plate for packaging ball grid array, and also can be applicable to cassette packaging part or all the other can be for carries chips and the structure that encapsulates, even also can be applicable to general printed circuit board (PCB) etc.
Claims (17)
1. circuit board, this circuit board are provided with cutting path and define a plurality of circuit board units that array way is arranged that are, and it is characterized in that this circuit board comprises:
One body includes at least one insulating barrier, and at least one patterned line layer that is stacked on this insulating barrier; And
One covers the layer of refusing of this body surface, and wherein this is refused layer and forms groove corresponding to this cutting path, and this groove width exposes outside the surface of insulating layer of this body greater than the cutting width of cutting path.
2. circuit board as claimed in claim 1, it is characterized in that, this circuit board along get final product after this cutting path cuts a plurality of circuit board units, this circuit board unit has the layer of refusing that a body and covers this body surface, this refuses the planar dimension of layer planar dimension less than this circuit board unit body, exposes outside the marginal portion of this circuit board unit body.
3. circuit board as claimed in claim 1 is characterized in that, this board application is at the base plate for packaging of ball grid array (BGA) semiconductor package or the circuit board of cassette packaging part.
4. circuit board as claimed in claim 1 is characterized in that, this is refused layer and forms opening and expose outside in this circuit board as the electric connection pad that is electrically conducted with the external world.
5. circuit board as claimed in claim 1 is characterized in that, this is refused the layer groove and is formed on the upper and lower surface of this body.
6. circuit board as claimed in claim 1 is characterized in that, this is refused the layer groove and is formed on the single surface of this body.
7. circuit board as claimed in claim 1 is characterized in that this circuit board cuts with laser mode.
8. circuit board as claimed in claim 1 is characterized in that this circuit board is provided with irregular cutting path.
9. a semiconductor package structure is characterized in that, this semiconductor package structure comprises:
Circuit board, this circuit board has the layer of refusing that a body and covers this body surface, circuit board is provided with cutting path, define a plurality of circuit board units that array way is arranged that are, wherein this body includes at least one insulating barrier, and at least one patterned line layer that is stacked on this insulating barrier, this is refused the layer correspondence and is formed with groove at this cutting path, exposes outside the insulating barrier of this body;
Semiconductor chip connects and puts and be electrically connected to respectively this circuit board unit, and this semiconductor chip is positioned on this circuit board surface of relative this cutting path; And
Packing colloid is formed on the circuit board in order to coat this semiconductor chip.
10. semiconductor package structure as claimed in claim 9 is characterized in that this groove width is greater than the cutting width of cutting path.
11. semiconductor package structure as claimed in claim 9 is characterized in that, this assembling structure along get final product after this cutting path cuts a plurality of construction units, wherein, this construction unit comprises:
Circuit board unit, this circuit board unit have the layer of refusing that a body and covers this body surface, and this refuses the planar dimension of layer planar dimension less than this circuit board unit body, expose outside the marginal portion of this circuit board unit body.
12. semiconductor package structure as claimed in claim 9 is characterized in that, this board application is at the base plate for packaging of ball grid array (BGA) semiconductor package or the circuit board of cassette packaging part.
13. semiconductor package structure as claimed in claim 9 is characterized in that, this is refused layer and forms opening and expose outside in this circuit board as the electric connection pad that is electrically conducted with the external world.
14. semiconductor package structure as claimed in claim 9 is characterized in that, this is refused the layer groove and is formed on the upper and lower surface of this body.
15. semiconductor package structure as claimed in claim 9 is characterized in that, this is refused the layer groove and is formed on the single surface of this body.
16. semiconductor package structure as claimed in claim 9 is characterized in that, this circuit board cuts with laser mode.
17. semiconductor package structure as claimed in claim 9 is characterized in that, this circuit board is provided with irregular cutting path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100012150A CN100477136C (en) | 2006-01-10 | 2006-01-10 | Circuit board and packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100012150A CN100477136C (en) | 2006-01-10 | 2006-01-10 | Circuit board and packaging structure thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101000879A CN101000879A (en) | 2007-07-18 |
| CN100477136C true CN100477136C (en) | 2009-04-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006100012150A Active CN100477136C (en) | 2006-01-10 | 2006-01-10 | Circuit board and packaging structure thereof |
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| CN (1) | CN100477136C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101365297B (en) * | 2007-08-10 | 2010-11-17 | 富葵精密组件(深圳)有限公司 | Circuit board cutting method |
| US9917068B2 (en) * | 2014-03-14 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company | Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices |
| US12009285B2 (en) * | 2019-04-22 | 2024-06-11 | Kyocera Corporation | Substrate having a recessed portion for an electronic component |
| JP7562965B2 (en) * | 2020-03-10 | 2024-10-08 | 富士電機株式会社 | Manufacturing method, manufacturing apparatus, jig assembly, semiconductor module and vehicle |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030153127A1 (en) * | 2002-02-08 | 2003-08-14 | Hitachi, Ltd. Hitachi Ulsi Systems Co., Ltd. | Method of manufacturing a semiconductor device |
| CN1484328A (en) * | 2002-06-24 | 2004-03-24 | ������������ʽ���� | Semiconductor element and its manufacturing method |
| US20050148217A1 (en) * | 2003-07-17 | 2005-07-07 | Takiar Hem P. | Memory card with chamfer |
| CN1658372A (en) * | 2004-02-17 | 2005-08-24 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
-
2006
- 2006-01-10 CN CNB2006100012150A patent/CN100477136C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030153127A1 (en) * | 2002-02-08 | 2003-08-14 | Hitachi, Ltd. Hitachi Ulsi Systems Co., Ltd. | Method of manufacturing a semiconductor device |
| CN1484328A (en) * | 2002-06-24 | 2004-03-24 | ������������ʽ���� | Semiconductor element and its manufacturing method |
| US20050148217A1 (en) * | 2003-07-17 | 2005-07-07 | Takiar Hem P. | Memory card with chamfer |
| CN1658372A (en) * | 2004-02-17 | 2005-08-24 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
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| Publication number | Publication date |
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| CN101000879A (en) | 2007-07-18 |
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